JP2008277827A - Non-volatile memory element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile memory element and its manufacturing method. <P>SOLUTION: The non-volatile memory element comprises a first electrode 12 and a second electrode 17 formed on the substrate 11, conductive organic layers 13 and 16 formed between the first electrode 12 and the second electrode 17, a unit cell formed between the conductive organic layers 13 and 16 and having a nano crystal layer 15 containing a plurality of nano crystals 15A surrounded by a barrier 15B of amorphous nature, and a driving means for applying a predetermined input voltage between the first electrode 12 and the second electrode 17 to drive the unit cell to output any one current out of currents of at least three levels. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a nonvolatile memory device having a structure in which a conductive organic material is interposed between an upper electrode and a lower electrode, such as a PoRAM (Polymer Random Access Memory), and its manufacture Regarding the method.

  At present, volatile DRAMs and nonvolatile flash memories are mainly used as memory devices.

  The DRAM adjusts the channel width under the gate of the cell transistor by the voltage applied to the gate, forms a channel between the source terminal and the drain terminal, and charges or discharges electrons in the cell capacitor connected to the source terminal. Cell data is read according to the charge and discharge states of the cell capacitor. Since such a DRAM is a volatile memory element, the capacitor must be continuously charged, which causes a problem of high power consumption. In addition, when power is not applied, there is a problem that data input to the element is lost due to leakage current.

  On the other hand, in a non-volatile flash memory device such as a NAND flash memory, FN (Fowler-Nordheim) tunneling is generated by a voltage applied to the control gate and the channel region, and this FN tunneling charges electrons in the floating gate. Discharge. The threshold voltage of the channel region changes according to the charge and discharge states of the floating gate, and the flash memory device discriminates 0 and 1 data by reading the change of the threshold voltage. Since such a flash memory device uses FN tunneling, there is a problem that the voltage used in the device is extremely high. Further, since data writing and reading are performed by charging or discharging electrons to a floating gate made of polysilicon by FN tunneling, there is a problem that the data processing speed is slow at the microsecond level.

The conventional memory device as described above has a slightly large memory cell size (8F ² ) and must go through at least several tens of steps. Therefore, it is difficult to improve the integration degree of the device, reduce the cost, and maintain the manufacturing yield. It is.

  Therefore, in order to overcome the above-mentioned problems of conventional DRAMs and flash memories and to realize a next-generation memory device having advantages at the same time, many research institutions and companies in various countries are conducting research.

  Next-generation memory devices have a wide range of research fields depending on the materials constituting the cells, which are the basic units inside. For example, depending on whether the material when cooled after applying an electric current to the phase change material is in a crystalline state having a low resistance value or an amorphous state having a high resistance value, the resistance difference is set to 0. A memory element using a bistable conductive characteristic in which high-resistance and low-resistance exist at the same voltage when a voltage of 1 is formed or a voltage is applied to a conductive organic substance, or a memory using a ferroelectric property Attempts have been made to form data as elements and to store data using N-pole and S-pole ferromagnetic materials. In addition, research on non-volatile memory devices including flat floating gates using nanocrystals of metal, silicon, or compound semiconductors instead of flat silicon has been actively conducted.

  However, it is left as a common problem in next-generation memory devices that these materials make use of their characteristics to find manufacturing conditions that can be applied to highly integrated memory devices.

In particular, among the next generation memories, a non-volatile memory using a conductive organic material (for example, PoRAM) has not been applied to actual mass production, and appropriate manufacturing conditions for manufacturing the non-volatile memory as a memory element. Is difficult to find. That is, since it is difficult to form nanocrystals having a uniform size and distribution in a conductive organic material with good reproducibility, the threshold voltage and bistable conductive characteristics (I _on / I _off ratio) of the device are not uniform. There is a problem of becoming.

The present invention has been made in order to solve the above-described problems of the prior art, and has an object of preventing loss of data even when no voltage is applied, low power consumption, and high integration ( Memory cell size: 4F ² ) is possible, while maintaining the characteristics of a PoRAM device having a high processing speed and forming nanocrystals having a uniform size and distribution by various methods, the threshold within the same device can be obtained. It is an object of the present invention to provide a non-volatile memory device that can maintain a uniform value voltage and I _on / I _off ratio, and a method of manufacturing the same. Furthermore, another object is to provide a non-volatile memory device in which unit cells have multiple levels of data using an intermediate state of bistable conductive characteristics, and a unit cell can be stacked in multiple layers, and a method for manufacturing the same. There is to do.

  In order to solve the above problems, a nonvolatile memory device according to the present invention includes a first electrode and a second electrode formed on a substrate, and a conductive organic material layer formed between the first electrode and the two electrodes. A unit cell including a nanocrystal layer including a plurality of nanocrystals formed in the conductive organic material layer and surrounded by a non-crystalline barrier, and the unit cell has at least three levels of current Drive means for driving the unit cell by applying a predetermined input voltage between the first electrode and the second electrode so as to output one current.

  Another non-volatile memory device according to the present invention for solving the above-described problems is provided with a first electrode and a second electrode formed on a substrate, and a conductive formed between the first electrode and the second electrode. A unit cell comprising a conductive organic layer and a nanocrystal layer including a plurality of nanocrystals formed in the conductive organic layer and surrounded by an amorphous barrier, and the unit cell has a high resistance state, a low resistance Drive means for driving the unit cell by applying a predetermined input voltage between the first electrode and the second electrode so as to be in any one of a resistance state and a negative resistance state. .

  Another nonvolatile memory device according to the present invention for solving the above problems is formed between a first electrode and a second electrode formed on a substrate, and the first electrode and the second electrode. A conductive organic material layer; and a nanocrystal layer formed in the conductive organic material layer and including a plurality of nanocrystals surrounded by an amorphous barrier, and is applied between the first electrode and the second electrode. When the input voltage is in the first voltage range, an input data read operation is performed. When the input voltage is in the second voltage range higher than the first voltage range, a first input data write operation is performed. When the input voltage is in a third voltage range higher than the second voltage range, a write operation of second input data is performed, and when the input voltage is in a fourth voltage range higher than the third voltage range, the first voltage Of the input data or the second input data Operate is configured to be performed.

  Another nonvolatile memory device according to the present invention for solving the above problems is formed between a first electrode and a second electrode formed on a substrate, and the first electrode and the second electrode. A first cell comprising: a first conductive organic material layer; and a first nanocrystal layer formed in the first conductive organic material layer and including a plurality of nanocrystals surrounded by an amorphous barrier; and A second electrode and a third electrode; a second conductive organic layer formed between the second electrode and the third electrode; and a non-crystalline barrier formed in the second conductive organic layer. The second cell includes a second nanocrystal layer including a plurality of enclosed nanocrystals, and the first cell and the second cell are stacked.

  Another non-volatile memory device according to the present invention for solving the above problems is formed between a lower electrode and an upper electrode formed on a substrate and the lower electrode and the upper electrode, and is non-crystalline. And a polymer layer in which a plurality of nanocrystals surrounded by a barrier are dispersed.

  Another nonvolatile memory device according to the present invention for solving the above problems is formed between a first electrode and a second electrode formed on a substrate, and the first electrode and the second electrode. A first cell comprising a first polymer layer dispersed with a plurality of nanocrystals surrounded by an amorphous barrier, and between the second electrode and the third electrode, and between the second electrode and the third electrode; The second cell includes a first polymer layer in which a plurality of nanocrystals surrounded by an amorphous barrier are dispersed, and the first cell and the second cell are stacked.

  According to another aspect of the present invention, there is provided a non-volatile memory device manufacturing method comprising: forming a first electrode on a substrate; and forming a first conductive organic material layer on the substrate including the first electrode. Forming a first nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier on the first conductive organic material layer; and the first nanocrystal layer including the first nanocrystal layer. Forming a first cell by forming a second conductive organic material layer on the conductive organic material layer, and forming a second electrode on the substrate including the second conductive organic material layer; and Forming a third conductive organic layer on the substrate including an electrode; forming a second nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier on the third conductive organic layer; Performing the second nanostructure Forming a fourth cell by forming a fourth conductive organic layer on the third conductive organic layer including the layer, and forming a third electrode on the substrate including the fourth conductive organic layer. Includes steps.

  According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile memory device, comprising: forming a first electrode on a substrate; and a first conductive organic material layer on the substrate including the first electrode. Forming a first barrier material layer on the first conductive organic material layer, forming a predetermined metal layer on the first barrier material layer, and on the predetermined metal layer Forming a second barrier material layer, forming a second conductive organic material layer on the first conductive organic material layer including the second barrier material layer, and including the second conductive organic material layer. Curing the formed laminate, and forming a second electrode on the substrate including the second conductive organic material layer, the first conductive organic material layer and the second conductive organic material layer. Between the non-crystalline barrier A nanocrystal layer including a plurality of enclosed nanocrystals is formed, the nanocrystals are made of metal of the predetermined metal layer, and the non-crystalline barrier is made of the first barrier material and the second barrier material. .

  According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, comprising: forming a lower electrode on a substrate; and enclosing a non-crystalline barrier on the substrate including the lower electrode. Forming a polymer layer in which a plurality of nanocrystals are dispersed, and forming an upper electrode on the substrate including the polymer layer.

  The method for forming a nanocrystal layer according to the present invention for solving the above-described problems includes a step of forming a first barrier material layer on a substrate, a step of forming a metal layer on the first barrier material layer, Forming a second barrier material layer on the metal layer; and curing the formed laminate including the second barrier material layer, and being surrounded by the first barrier material and the second barrier material. A plurality of metal nanocrystals are formed.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings in order to describe in detail to such an extent that a person having ordinary knowledge in the technical field of the present invention can easily implement the technical idea of the present invention. I will explain.

In the present specification, the nonvolatile memory element of the present invention, for example, PoRAM will be described separately depending on the type of the conductive organic material. Specifically, the case where a low molecular substance (for example, AIDCN, Alq ₃ , α-NPD) is used as the conductive organic substance and the case where a high molecular substance (for example, PVK) is used will be described separately. This is because the manufacturing method of the nonvolatile memory element of the present invention is preferably different depending on the type of the conductive organic substance, and the structure of the manufactured element is partially different depending on the manufacturing method. .

  First, a nonvolatile memory element using a low molecular weight material as a conductive organic material will be described with reference to FIGS. 1A to 14B below.

  1A is a cross-sectional view illustrating a configuration of a nonvolatile memory element according to an embodiment of the present invention, and FIG. 1B illustrates a configuration of a nonvolatile memory element according to a modification of the embodiment of the present invention. It is sectional drawing. In particular, these cross-sectional views show the cell array region.

  As shown in FIG. 1A, a nonvolatile memory device according to an embodiment of the present invention is formed between a lower electrode 12 and an upper electrode 17 formed on a substrate 11, and between the lower electrode 12 and the upper electrode 17. A unit cell composed of the first conductive organic material layer 13 and the second conductive organic material layer 16 and the nanocrystal layer 15 formed between the first conductive organic material layer 13 and the second conductive organic material layer 16. It has. Here, the nanocrystal layer 15 includes a plurality of crystalline nanocrystals 15A and an amorphous barrier 15B surrounding the nanocrystals 15A. That is, the non-crystalline barrier 15B is a continuous film including the nanocrystal 15A therein, and functions as a tunneling barrier for electrons charged or discharged in the nanocrystal 15A. Hereinafter, each material layer constituting the nonvolatile memory device of FIG. 1A will be described in detail.

First, as the substrate 11, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. That is, at least one of a plastic substrate, a glass substrate, an Al ₂ O ₃ substrate, a SiC substrate, a ZnO substrate, a Si substrate, a GaAs substrate, a GaP substrate, a LiAl ₂ O ₃ substrate, a BN substrate, an AlN substrate, an SOI substrate, and a GaN substrate. Any one can be used. When a semiconductor substrate or a conductive substrate is used, the substrate 11 and the lower electrode 12 must be separated by an insulator.

  The lower electrode 12 and the upper electrode 17 are materials having electrical conductivity. In particular, it is preferable to use a metal having low electrical resistance and excellent interface characteristics with a conductive organic material. In particular, it is preferable to use any one selected from Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof.

As the first conductive organic material layer 13 and the second conductive organic material layer 16, it is preferable to use any one of AIDCN, α-NPD, and Alq ₃ which are low molecular compounds.

  AIDCN is represented by the following chemical structural formula.

α-NPD is represented by the following chemical structural formula.

Alq ₃ is represented by the following chemical structural formula.

As described above, the nanocrystal layer 15 includes the plurality of nanocrystals 15A and the non-crystalline barrier 15B surrounding the nanocrystal 15A. The nanocrystal layer 15 is formed by forming a first metal layer that can be oxidized and Preferably, the first metal layer is formed by plasma oxidation. This is because the stable device characteristics can be secured by forming the stable nanocrystal 15A having a certain size and distribution, and the amorphous barrier 15B can be formed by an extremely simple process. Thus, the nanocrystal 15A is made of the first metal, and the non-crystalline barrier 15B is made of the oxide of the first metal. For example, when the nanocrystal 15A is Al, the non-crystalline barrier 15B is Al _X O _Y (especially Al ₂ O ₃ ), and when the nanocrystal 15A is Ni, the non-crystalline barrier 15B is Ni _X O _Y (particularly NiO). However, the invention is not limited thereto, and the nanocrystal 15A is made of any one selected from oxidizable metals such as Al, Mg, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof. Thus, the non-crystalline barrier 15B is made of an oxide of a selected metal. The method for forming the nanocrystal layer 15 will be described in more detail with reference to a method for manufacturing a nonvolatile memory element described later (see FIGS. 2A to 3D).

  Here, the thickness of the nanocrystal layer 15 is preferably in the range of 1 nm to 40 nm. In one embodiment, the thickness of the nanocrystal layer 15 is in the range of 10 nm to 15 nm. In this specification, although the single nanocrystal layer 15 is shown as an example, it is not limited to this, You may have the structure where the several nanocrystal layer 15 was laminated | stacked. Preferably, the number of nanocrystal layers 15 included in one unit cell is 2 to 8, more preferably 2 to 4. By laminating the nanocrystal layer 15 in this way, the data retention capability of the element can be improved and an effective energy gap can be maintained. In one embodiment, when a plurality of nanocrystal layers 15 are stacked, the thickness of each nanocrystal layer 15 is preferably the same. As described above, the unit cell including the nanocrystal layer 15 including the nanocrystal 15A and the non-crystalline barrier 15B surrounding the nanocrystal 15A between the first conductive organic material layer 13 and the second conductive organic material layer 16. As described later, the element has a predetermined resistance value according to the voltage applied to the lower electrode 12 and the upper electrode 17, and can output a current at a level corresponding to the resistance value. , Data of 1 bit or more can be stored in the unit cell. The operation characteristics of such an element will be described later (see FIGS. 6A to 7H).

  As shown in FIG. 1B, a nonvolatile memory device having a double cell structure in which two unit cells shown in FIG. 1A are stacked is formed. That is, the nonvolatile memory device shown in FIG. 1B has a stacked structure of a first cell 1C and a second cell 2C. The first cell 1C is formed on the substrate 110, and includes a lower electrode and a first electrode of the first cell 1C. The first electrode 120 and the second electrode 220 corresponding to the upper electrode, the first conductive organic layer 130 and the second conductive organic layer 160 formed between the first electrode 120 and the second electrode 220, and the first The first nanocrystal layer 150 is provided between the conductive organic layer 130 and the second conductive organic layer 160. The second cell 2C includes a second electrode 220 and a third electrode 270 corresponding to the lower electrode and the upper electrode of the second cell 2C, and a third conductivity formed between the second electrode 220 and the third electrode 270. The second nanocrystal layer 250 formed between the conductive organic layer 230 and the fourth conductive organic layer 260 and between the third conductive organic layer 230 and the fourth conductive organic layer 260. Here, the second electrode 220 is used as a common electrode of the first cell 1C and the second cell 2C. In another embodiment, the first cell and the second cell may use different second electrodes. In the nonvolatile memory device having such a double cell structure, each material layer is the same as that described with reference to FIG.

  In this way, by stacking two cells, the degree of integration within a single area can be improved. However, the present invention is not limited to this, and three or more cells may be stacked by the same method. Further, even in the case of a structure in which two or more cells are stacked, each cell has a predetermined resistance value as in the case of a single cell that is not stacked, and a plurality of cells according to the resistance value A level current can be output. The operation characteristics of such an element will be described later (see FIGS. 13A to 14B).

  2A to 2F are views for explaining a method of manufacturing a nonvolatile memory element according to an embodiment of the present invention. In these drawings, the left side is a plan view for explaining a method for manufacturing a nonvolatile memory element, and the right side is a cross-sectional view taken along line AA shown in the left plan view.

  As shown in FIG. 2A, the first electrode 212 is formed on the substrate 211. In this specification, as an example, an example in which the linear first electrode 212 extending in a predetermined direction (lateral direction) is formed on the substrate 211 using a thermal evaporation method will be described.

Specifically, first, the substrate 211 is placed in a chamber (not shown) for vapor deposition of a metal layer, and then the first electrode 212 is formed using a first shadow mask (not shown). The exposed area. Thereafter, the pressure in the chamber is set to a range of 10 ⁻⁶ Pa to 10 ⁻³ Pa, and the deposition metal is maintained at a temperature in the range of 1000 ° C. to 1500 ° C. with the deposition rate maintained in the range of 2 to 7 ° C./s. Is evaporated to form a metal layer on the exposed substrate 211. This metal layer becomes the first electrode 212. Predetermined cleaning may be performed before or after the metal layer for forming the first electrode 212 is deposited.

  Here, it is preferable to use Al as the first electrode 212. However, the present invention is not limited to this, and any one selected from Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof can be used. The thickness of the first electrode 212 is preferably in the range of 50 nm to 100 nm.

  A silicon substrate or a glass substrate is preferably used as the substrate 211. When a silicon substrate is used, an insulating film must be deposited on the entire surface of the substrate. As this insulating film, an oxide or nitride-based substance is preferably used.

  As shown in FIG. 2B, a first conductive organic material layer 213 is formed on a substrate 211 on which a linear first electrode 212 is formed. In this specification, as an example, the first conductive organic material layer 213 which overlaps with a part of the first electrode 212 is formed by a thermal evaporation method.

Specifically, in order to form the first conductive organic material layer 213, after the substrate 211 on which the first electrode 212 is formed is placed in a chamber (not shown) for depositing the conductive organic material, A formation region of the first conductive organic material layer 213 is exposed using a two-shadow mask (not shown). At this time, the exposed region is such that a part of the first conductive organic material layer 213 is formed in a shape surrounding the first electrode 212, and the first electrode 212 is positioned at the center as shown in the figure. It is preferable that the shape is a square. Of course, the shape is not limited to this, and may be a circle, an ellipse, a triangle, a polygon, or the like. Thereafter, the pressure in the chamber is in the range of 10 ⁻⁶ Pa to 10 ⁻³ Pa, and the deposition rate is maintained in the range of 0.2 Å / s to 1.5 Å / s. The source organic material is evaporated at a temperature to form a first conductive organic material layer 213 on the exposed substrate 211 and the first electrode 212.

Here, the first conductive organic material layer 213 is a low molecular weight substance AIDCN, it is preferable to use alpha-NPD or Alq _3. The thickness of the first conductive organic material layer 213 is preferably in the range of 10 nm to 100 nm.

  As shown in FIG. 2C and FIG. 2D, a metal layer 214 is deposited on the first conductive organic material layer 213, and then plasma oxidation is performed, so that a plurality of nanocrystals 215A made of metal and A nanocrystal layer 215 composed of a crystalline barrier 215B is formed. The nanocrystal 215A is made of a metal, and the non-crystalline barrier 215B is made of an oxide of a metal constituting the metal layer 214. The nanocrystal layer 215 has a uniform thickness (for example, in the range of 1 nm to 40 nm) according to the deposition thickness of the metal layer 214. That is, the non-crystalline barrier 215B is a continuous film including nanocrystals 215A therein.

  Specifically, the substrate 211 on which the first conductive organic material layer 213 is formed is placed in a chamber (not shown) for depositing metal. Using a third shadow mask (not shown), the first conductive organic material layer 213 in the region where the nanocrystal layer 215 is formed is exposed. At this time, an exposed region is formed such that a part of the first conductive organic material layer 213 is exposed and at least a part of the first electrode 212 under the first conductive organic material layer 213 overlaps the nanocrystal layer 215. As a result, a part of the nanocrystal layer 215 overlaps a part of the first electrode 212. Thus, the shape of the region exposed by the third shadow mask is preferably the same as or similar to the first conductive organic material layer 213 (for example, a square shape).

Thereafter, the pressure in the chamber is in the range of 10 ⁻⁶ Pa to 10 ⁻³ Pa and the deposition rate is maintained in the range of 0.1 Å / s to 7.0 Å / s. The source metal is evaporated at a temperature to form a metal layer 214 having a thickness in the range of 1 nm to 40 nm on the exposed first conductive organic layer 213. More preferably, when the metal layer 214 is Al, the deposition rate is in the range of 1.0 Å / s to 5.0 Å / s, and when the metal layer 214 is Ni, the deposition rate is 0.1 Å / s to 1.. The range is 0 Å / s. At this time, since the vapor deposition rate is high, the metal layer 214 is not formed in a nanocrystal form but is formed as a metal thin film having a crystal grain boundary (see FIG. 3A).

Next, the substrate 211 on which the metal layer 214 is formed is placed in a plasma oxidation chamber (not shown). An RF power in the range of 50 W to 300 W and an AC bias in the range of 100 V to 200 V are applied to the chamber, and O ₂ gas is introduced at a pressure in the range of 0.5 Pa to 3.0 Pa to perform plasma oxidation. The treatment time at this time is preferably 50 seconds to 500 seconds. As a result, the metal layer 214 having a crystal grain boundary is oxidized by the penetration of O ₂ plasma along the grain boundary, and a plurality of nanocrystals 215A having the same size and an amorphous metal oxide surrounding the nanocrystal 215A. That is, the barrier 215B is formed (see FIGS. 3B to 3D). At this time, as described above, the nanocrystal layer 215 is preferably formed in a range of 1 nm to 40 nm in accordance with the thickness of the metal layer 214. Of course, the thickness of the metal layer 214 may be further increased. However, when the thickness of the metal layer 214 is 50 nm or more, O ₂ plasma does not sufficiently penetrate into the crystal grain boundary of the metal layer 214. The nanocrystal layer 215 having a predetermined characteristic may not be formed. Alternatively, the metal layer 214 may be oxidized in the deposition chamber by a method other than plasma oxidation to form nanocrystals. However, in order to form stable nanocrystals having a certain size and distribution, crystal grains may be used. It is preferable to forcibly oxidize by infiltrating O ₂ plasma along the boundary.

  Here, the multilayer nanocrystal layer 215 having a plurality of nanocrystal thin films can be formed by repeating the deposition and plasma oxidation of the metal layer 214 a plurality of times. At this time, according to the deposition thickness of the metal layer 214, a plurality of nanocrystal thin films constituting the multi-layer nanocrystal layer 215 may be formed to have the same thickness or different thicknesses. You may form in. In one embodiment, it is preferable to form nanocrystal thin films having the same thickness.

  As shown in FIG. 2E, a second conductive organic material layer 216 is formed on the first conductive organic material layer 213 on which the nanocrystal layer 215 is formed. In this specification, as an example, the second conductive organic material layer 216 that overlaps the first conductive organic material layer 213 is formed by a thermal evaporation method.

Specifically, in order to form the second conductive organic material layer 216, the substrate 211 including the nanocrystal layer 215 is disposed in a conductive organic material deposition chamber (not shown). Thereafter, the first conductive organic material layer 213 on which the nanocrystal layer 215 is formed is exposed using the second shadow mask for depositing the first conductive organic material 213 described above. Next, the pressure in the chamber is in the range of 10 ⁻⁶ Pa to 10 ⁻³ Pa, and the deposition rate is maintained in the range of 0.2 Å / s to 1.5 Å / s. The source organic material is evaporated at a temperature to form a second conductive organic material layer 216 on the exposed nanocrystal layer 215 and the first conductive organic material layer 213.

  In the present embodiment, the second conductive organic material layer 216 uses the same material as the first conductive organic material layer 213, and the thickness of the second conductive organic material layer 216 is preferably in the range of 10 nm to 100 nm. It is. The second conductive organic material layer 216 may be formed of a different material in another embodiment. As described above, the nanocrystalline layer 215 is formed on a part of the first conductive organic material layer 213, and the second conductive organic material layer 216 is deposited thereon, so that the second conductive organic material layer 216 becomes a nanocrystal. Surround layer 215. The second conductive organic material layer 216 may be formed to the same thickness as the first conductive organic material layer 213 or may be formed to a thickness smaller than that.

As shown in FIG. 2F, the second electrode 217 is formed on the substrate 211 including the second conductive organic material layer 216. At this time, the second electrode 217 is preferably formed by a thermal evaporation method, and is preferably formed in a straight line extending in a direction (vertical direction) orthogonal to the first electrode 212. In this case, a 4F ² memory cell can be realized.

Specifically, first, the substrate 211 including the second conductive organic material layer 216 is placed in a metal deposition chamber, and then the second electrode 217 is formed using a fourth shadow mask (not shown). Expose the area. That is, a partial region of the second conductive organic material layer 216 and a partial region of the substrate 211 are exposed. At this time, a part of the nanocrystal layer 215 below the second conductive organic material layer 216 and a part of the second electrode 217 are formed to overlap each other. The exposed region is adjusted so that the nanocrystal layer 15 is disposed between the regions where the first electrode 212 and the second electrode 217 overlap. Thereafter, the pressure in the chamber is set to a range of 10 ⁻⁶ Pa to 10 ⁻³ Pa, and the deposition metal is maintained at a temperature in the range of 1000 ° C. to 1500 ° C. with the deposition rate maintained in the range of 2 to 7 ° C./s. Is evaporated to form a metal layer on the exposed second conductive organic material layer 216 and the substrate 211. This metal layer becomes the second electrode 217.

  Here, as the second electrode 217, Al is preferably used. However, the present invention is not limited to this, and any one selected from Al, Ti, Zn, Fe, Ni, Sn, Pb, Cu, and alloys thereof can be used. The thickness of the second electrode 217 is preferably in the range of 60 nm to 100 nm.

  Although not shown, another metal wiring forming step can be performed in order to connect each of the first electrode 212 and the second electrode 217 to the external electrode.

  The formation of the first electrode 212 and the second electrode 217, the first conductive organic material layer 213, the second conductive organic material layer 216, and the nanocrystal layer 15 may be performed in-situ in a vacuum atmosphere. . That is, the chambers for forming the first electrode 212 and the second electrode 217, the first conductive organic material layer 213, the second conductive organic material layer 216, and the nanocrystal layer 215 are included in a single deposition system. It may be. For example, in a single system where a metal deposition chamber, a conductive organic deposition chamber, a plasma generation chamber for plasma oxidation, a cooling chamber, a load lock chamber, and a shadow mask chamber are connected to one transfer module. The vapor deposition can be performed. In such a system, when the substrate is transferred from the metal deposition chamber to the conductive organic deposition chamber, the substrate can be moved in the vacuum transfer module without exposing the substrate to the atmosphere. Of course, the present invention is not limited to this, and the chambers may be provided in different systems.

  In the above description, the nonvolatile layer according to one embodiment of the present invention is formed by forming a metal layer, a conductive organic material layer, and a nanocrystal layer using a shadow mask and a thermal evaporation method without performing etching. An example of manufacturing a memory device has been shown. However, the present invention is not limited to this, and various memory element manufacturing methods can be used. The metal layer, the conductive organic material layer, and the nanocrystal layer can be formed by an electron beam evaporation method, a sputtering method, a CVD method, an ALD method, or the like in addition to the thermal evaporation method. In particular, the metal layer and the conductive organic material layer can be formed on the entire surface of the substrate and then shaped by patterning. That is, after a metal layer or an organic material layer is formed on the entire surface of a substrate, a metal layer or an organic material layer in a region excluding the formation region of the metal layer or the conductive organic material layer is removed by etching using a mask. Can also be used. Alternatively, the oxidation can be performed using wet and dry oxidation methods.

  3A to 3D are cross-sectional views for explaining the concept of the method for forming the nanocrystal layer. In particular, these drawings show an example in which a nanocrystal layer is formed using Al.

  As shown in FIG. 3A, a metal layer 314 for forming a nanocrystal layer is deposited on the first conductive organic material layer 313. At this time, as described above, when the metal layer 314 is deposited, the deposition rate is high, so that a metal thin film having a crystal grain boundary is formed instead of a nanocrystal form.

As shown in FIG. 3B, O ₂ plasma oxidation is performed on the metal layer 314. The O ₂ plasma penetrates along the grain boundaries of the metal layer 314 having crystal grain boundaries. As a result, as shown in FIG. 3C, the grain boundary of the metal layer 314 is oxidized to form a metal oxide 315B ′. As a result, metal nanocrystals 315A ′ of approximately the same size separated from each other are formed.

As shown in FIG. 3D, when the plasma oxidation is completed, a nanocrystal layer 315 including a crystalline metal nanocrystal 315A and a barrier 315B that is an amorphous metal oxide surrounding the nanocrystal 315A is formed. That is, for example, when Al is used as the metal layer 314, the nanocrystal 315A is made of metal Al, and the barrier 315B is made of amorphous Al _X O _Y (eg, Al ₂ O ₃ ). Similarly, when various kinds of oxidizable metals are used as the metal layer 314, the nanocrystal 315A is made of a metal, and the barrier 315B is made of a metal oxide (for example, an amorphous metal oxide). For example, when Ni is used for the metal layer 314, the nanocrystal 315A is made of metal Ni, and the barrier 315B is made of Ni _X O _Y (eg, NiO).

  In the following, in order to describe the nanocrystal layer formed by vapor deposition of metal layer and plasma oxidation method in more detail, an experimental example in which an Al nanocrystal layer and a Ni nanocrystal layer are formed by using this method is shown.

FIGS. 4A to 4D are cross-sectional TEM photographs and lattice photographs of a nonvolatile memory device including an Al nanocrystal layer formed by the method illustrated in FIGS. 2A to 3D. FIGS. It is a figure which shows the graph of the XPS (X-ray Photoelectron Spectroscopy) analysis result, and the graph of an AES (Auger Electron Spectroscopy) analysis result of the non-volatile memory element containing Al nanocrystal layer. 4A and 4B show the case where α-NPD is used as the conductive organic material layer, and FIGS. 4C and 4D show the case where Alq ₃ is used as the conductive organic material layer.

As shown in FIGS. 4A to 4D, the Al nanocrystal layer is composed of crystalline Al nanocrystals and amorphous Al ₂ O ₃ , and the Al nanocrystals are surrounded by amorphous Al ₂ O ₃ . It can be seen that they are separated from each other.

As shown in FIG. 4E, peaks of Al having a binding energy of 72.8 eV and an Al oxide having a binding energy of 75.2 eV appear simultaneously. This indicates that the Al nanocrystal layer is composed of Al nanocrystals and Al oxides (for example, Al ₂ O ₃ ).

As shown in FIG. 4F, in the distribution from the α-NPD layer, which is the upper conductive organic material layer, to the Al nanocrystal layer, oxygen peaks appear at both boundary portions of the Al nanocrystal layer. This is because, during the plasma oxidation for forming the Al nanocrystal layer, O ₂ plasma penetrates from the lower conductive organic material layer along the grain boundary of the metal layer and comes into contact with the lower conductive organic material layer. It is fully oxidized to the lower boundary of the layer. From this result, it was confirmed that the Al nanocrystals were separated by amorphous Al ₂ O ₃ and existed in an isolated form.

FIGS. 5A and 5B are cross-sectional TEM photographs and lattice photographs of a non-volatile memory device including a Ni nanocrystal layer formed by the method illustrated in FIGS. 2A to 3D, and FIGS. It is a figure which shows the graph of the XPS analysis result of a non-volatile memory element containing Ni nanocrystal layer, and the graph of an AES analysis result. In particular, FIGS. 5A to 5D show the case where Alq ₃ is used as the conductive organic material layer.

  As shown in FIGS. 5A and 5B, in the Ni nanocrystal layer, the Ni nanocrystal is much smaller than the Al nanocrystal, so the Ni nanocrystal and the amorphous Ni oxide surrounding it are clearly defined. Not distinguished. However, it can be confirmed that at least nanocrystals of metallic Ni are present.

As shown in FIG. 5C, after the deposition of the Ni metal layer and the O ₂ plasma oxidation, a peak of Ni oxide (NiO) having a binding energy of 854.6 eV appears. It can be seen that Ni is composed of Ni nanocrystals and Ni oxide formed by oxidation of Ni.

  As shown in the graph of FIG. 5D, the Ni nanocrystal layer contains 79.5% Ni and 20.5% O. That is, the Ni nanocrystal layer represents that Ni nanocrystal and Ni oxide are included at the same time. However, the difference from the graph of the Al nanocrystal layer in FIG. 4F is that the Ni nanocrystal is very small, and therefore, during AES analysis, an electron beam or the like causes the Ni nanocrystal and the non-crystalline Ni oxide surrounding the Ni nanocrystal. It is because the part which overlaps is permeate | transmitted.

That is, it was found that even when an Ni metal layer was deposited and O ₂ plasma oxidation was performed, Ni nanocrystals and amorphous Ni oxides surrounding the Ni nanocrystals were formed.

  Hereinafter, the operation of the nonvolatile memory device according to the embodiment of the present invention, that is, the first conductive organic layer / nanocrystalline layer / second conductive organic layer is formed between the lower electrode and the upper electrode. The operation of the nonvolatile memory device having the above structure will be described. In particular, in the present specification, as an example, a case where an Al nanocrystal layer and a Ni nanocrystal layer are formed using the method of FIGS. 2A to 3D will be described.

FIG. 6A is a graph showing voltage-current characteristics of a nonvolatile memory element using α-NPD as the conductive organic material layer according to one embodiment of the present invention and having an Al nanocrystal layer, and FIG. 6B is a conductive organic material. used AIDCN as a layer, and a graph showing the voltage-current characteristics of a nonvolatile memory device having an Al nanocrystal layer, FIG. 6C, the Alq ₃ is used as the conductive organic material layer, and non-volatile memory device having a Al nanocrystal layer FIG. 6D is a graph showing the voltage-current characteristics of a nonvolatile memory element using Alq ₃ as a conductive organic material layer and having a Ni nanocrystal layer. 7A to 7H are diagrams for explaining the mechanism by which the voltage-current characteristics of FIG. 6A are obtained. 6A to 7H relate to a unit cell.

  As shown in FIGS. 6A to 7H, the unit cell exhibits various current states or resistance states within a certain voltage range according to the voltage applied to the lower electrode and the upper electrode.

For example, when the lower electrode is grounded, the upper electrode is connected to a power source having a predetermined voltage, and the voltage of the power source is sequentially increased in the positive direction, the unit cell exponentially reaches the threshold voltage _Vth. Shows a high resistance state I _{off in} which rises slowly. Thereafter, when the potential difference between the lower electrode and the upper electrode becomes equal to or higher than a certain level (critical voltage or threshold voltage V _th ), the low resistance state I _on where the current rapidly increases is shown. As the voltage applied to the upper electrode approaches the maximum current voltage V _p, the output current of the unit cell increases. Further, at a higher maximum current voltage V _p continues to increase the voltage, the unit cell is a negative differential resistance NDR which the current decreases as voltage increases (Negative Differential Resistance, hereinafter referred to as "negative resistance") Indicates the state. The unit cell is in a negative resistance state until the voltage applied to the upper electrode reaches the reset voltage V _e (or the erase voltage). The output current of the unit cell increases as the voltage applied to the upper electrode increases. That is, it has been found that the unit cell exhibits various current states or resistance states depending on the potential difference between the upper electrode and the lower electrode. Here, the maximum current voltage V _p, represents the voltage at the time the voltage at which the current flowing through the element is maximized, or the negative resistance occurs.

As described above, the nonvolatile memory device having various current states or resistance states performs a data read operation in the first voltage range, and a data write operation in the second voltage range higher than the first voltage. The intermediate data write operation is performed in the high third voltage range, and the data erase operation is performed in the fourth voltage range higher than the third voltage range. The first voltage range, the threshold voltage V _th following values, second voltage range, the threshold voltage V _th or more and the maximum current voltage V _p the following values, the third voltage range, maximum The value of the current voltage _Vp or more and a constant reset voltage _Ve or less, and the fourth voltage range is a value of the constant reset voltage _Ve or more. Hereinafter, the mechanism will be described in more detail.

In order for the nonvolatile memory element of the present embodiment to be in the low resistance state I _on , a voltage higher than the threshold voltage V _th (that is, the first program voltage) is applied as shown in FIGS. 7B and 7C. To do. That is, as shown, after increasing the voltage to 0V to 5V, when confirming the state, that has a low resistance state I _on can be seen by further applying a voltage. At this time, when a read operation is performed by applying a voltage equal to or lower than the threshold voltage _Vth (that is, the first voltage range), the memory element storing the data maintains the low resistance state _Ion as it is. A current corresponding to is output. That is, the output current in the case where the read operation is performed after data is written to the element is increased several times or more than the output current in the case where the read operation is performed in a state where data is not written to the element.

Wherein for the memory element is to exhibit negative resistance state applies the maximum current voltage V _p higher and the reset voltage V _e following voltage (i.e., the second program voltage) to the memory device. That is, as shown in FIG. 7D and FIG. 7E, after increasing the voltage from 0 V to 7.5 V, when the voltage is further applied and the state is confirmed, it is found that the intermediate resistance state I _inter is reached. At this time, when a read operation is performed by applying a voltage equal to or lower than the threshold voltage _Vth , the memory element storing data outputs a current corresponding to the intermediate resistance state _Iinter . The intermediate resistance state I _inter has a resistance state corresponding to the middle between the high resistance state I _off and the low resistance state I _on , whereby the memory device outputs a current corresponding to the intermediate resistance state I _inter . That is, in the intermediate resistance state I _inter, a current lower than that in the low resistance state I _on and higher than that in the high resistance state I _off is output. Therefore, in the graph of FIG. 6A, when the current characteristics of the element at the read voltage level (for example, 2 V) are seen, the intermediate resistance state I _inter is the output current in the high resistance state I _{off and} the output current in the low resistance state I _on . It can be seen that an intermediate level output current is output between

When a constant reset voltage _Ve is applied after the negative resistance state, the element changes to the high resistance state. That is, it is reset. As a result, the first program voltage in the low resistance state I _on region is applied, the value corresponding to the first data is stored in the element, the second program voltage in the negative resistance state region is applied, and the second data Can be stored in the element.

In particular, since the output current level changes according to the voltage level applied in the negative resistance state region, various values corresponding to the second data can be stored in the element. For example, as shown in FIG. 6D, when a voltage (about 5 V or 6 V) in the negative resistance state region is applied, various levels of current I _inter1 are set in the voltage for reading operation (about 2 V) according to the applied voltage. , I _inter2 is output. At this time, as described above, the currents I _inter1 and I _inter2 output in accordance with the applied voltage in the negative resistance state region are higher than the output current I _off at the time of erasure and are output at the time of storing the first data. a lower level than the current _{I on.} As a result, the unit cell can realize a multilevel cell having a plurality of levels of three or more.

When carriers are not charged in the nanocrystal due to the energy level difference between the nanocrystal layer including the nanocrystal and the non-crystalline barrier surrounding the nanocrystal and the conductive organic material layer, at a predetermined voltage level. The current increases slightly. However, if the voltage applied between the conductive organic layers is equal to or higher than a predetermined critical voltage (for example, threshold voltage V _th ), carriers are charged in the nanocrystal, and the current rapidly increases. When the carrier is charged in the nanocrystal, the current reaches several tens to several tens of thousands of times compared to the case where the carrier is not charged. In addition, if the voltage applied between the conductive organic layers is a voltage in the negative resistance region, the carrier is partially discharged or charged in the nanocrystal, and the carrier is lower than when the carrier is fully charged. The intermediate resistance state current is higher than when the battery is not charged. When a voltage equal to or higher than the voltage in the negative resistance state region (for example, reset voltage V _e ) is applied, the carriers charged in the nanocrystal are changed into a completely discharged state.

It can also be seen that when the voltage of the power supply is sequentially increased in the negative direction (see FIG. 6A), the operation is almost symmetrical with the case where the voltage is applied in the positive direction. That is, the current increases slightly with respect to the voltage up to a certain level of voltage, and when a voltage equal to or higher than a certain level (for example, threshold voltage V _th ) is applied, the current rapidly increases. Next, when a voltage equal to or higher than the maximum current voltage V _p is applied, a negative resistance state is entered, and then the current increases again with respect to a voltage equal to or higher than the reset voltage V _e . This is due to the symmetrical structure of the element, and the same mechanism as in the case of the voltage in the positive direction described above functions.

  As described above, the nonvolatile memory element according to one embodiment of the present invention can have a double cell structure in which two unit cells are stacked (see FIG. 1B). Further, a multi-cell structure in which three or more unit cells are stacked may be used.

  FIG. 8A to FIG. 9B are diagrams for explaining the operation of the nonvolatile memory device having a double cell structure, in particular, when cells including an Al nanocrystal layer are stacked and including a Ni nanocrystal layer. An experimental example in the case where cells are stacked will be described.

8A and 8B are graphs showing voltage-current characteristics of a nonvolatile memory element when Alq ₃ is used as a conductive organic material layer and two cells each having an Al nanocrystal layer are stacked. 9A and 9B are graphs showing the voltage-current characteristics of the nonvolatile memory element when Alq ₃ is used as the conductive organic material layer and two cells each having a Ni nanocrystal layer are stacked. In particular, FIGS. 8A and 9A show the characteristics of the lower cell, and FIGS. 8B and 9B show the characteristics of the upper cell.

  As shown in FIGS. 8A to 9B, each cell has various levels during a read operation according to an applied voltage, that is, a program state, even in the case of a double cell structure in which two unit cells are stacked. It can be seen that the characteristics of the multi-level cell that outputs a current of 5 are maintained. With such a multi-level cell, more resistance states or current states can be secured. As described above, when a larger number of cells are stacked, high-capacity data can be stored, and elements can be highly integrated.

Hereinafter, the retention capability and durability of such a nonvolatile memory device will be described in detail. FIG. 10A is a graph showing the results of a retention capability test of a nonvolatile memory element using α-NPD as the conductive organic material layer and having an Al nanocrystal layer, FIG. 10B uses AIDCN as the conductive organic material layer, and FIG. 10C is a graph showing the result of the retention capability test of the nonvolatile memory element having the Al nanocrystal layer, and FIG. 10C is a graph of the retention capability test of the nonvolatile memory element having Al nanocrystal layer using Alq ₃ as the conductive organic material layer FIG. 10D is a graph showing the results of a retention test and a durability test of a nonvolatile memory element using Alq ₃ as a conductive organic material layer and having a Ni nanocrystal layer. 10A and 10B relate to the case of a unit cell.

As shown in FIG. 10A, the nonvolatile memory device showing three resistance states, one of the resistance states to store the result of this read more than once, the low-resistance state I _on between 10 ⁵ or more _periodic, intermediate Both the resistance state I _intermediate and the high resistance state I _off are stably maintained. As shown in FIG. 10B, 4 one is a non-volatile memory device having a resistance state, the result of which was read several times to store one resistance state, 10 ⁵ each state during the period is stably maintained Yes. As shown in FIG. 10C, the non-volatile memory device having two resistance states, a result of which a read multiple stores one resistance state, the state between the 10 ^two cycles are stably maintained Yes. As shown in FIG. 10D, the non-volatile memory device having four resistance states stores one resistance state and reads out the resistance state a plurality of times. As a result, each state is stably maintained for 10 ⁵ cycles. Yes.

FIG. 11A and FIG. 11B show results of retention capability and / or durability test of a nonvolatile memory device when Alq ₃ is used as a conductive organic material layer and two cells each having an Al nanocrystal layer are stacked. It is a graph. 12A and 12B show the results of the non-volatile memory element retention capability and / or durability test when Alq ₃ is used as the conductive organic layer and two cells each having a Ni nanocrystal layer are stacked. It is a graph which shows. In particular, FIGS. 11A and 12A show the characteristics of the lower cell, and FIGS. 11B and 12B show the characteristics of the upper cell.

As shown in FIG. 11A to FIG. 12B, in the nonvolatile memory element in which two cells are stacked, each cell has four resistance states, and the result of storing one resistance state and reading this multiple times It can be seen that each resistance state is stably maintained during 10 ⁵ cycles.

  In particular, the lower graphs of FIGS. 10D, 11B, 12A, and 12B show the results of the durability test. In the nonvolatile memory device, data writing, reading, erasing, and reading are performed in one cycle. And the results of repeated measurement of the cycle a plurality of times are shown. As is clear from this, since the resistance state when each read voltage is applied is different, the current level is clearly divided.

On the other hand, a nonvolatile memory element configured with an actual circuit is driven by a pulse signal. FIG. 13 is a graph showing the operating characteristics of the element by applying a pulse signal. As shown in FIG. 13, the non-volatile memory device using α-NPD as the conductive organic material layer and including the Al nanocrystal layer was set to a 5V write voltage, a 2V read voltage, and a −9V erase voltage. When the operation characteristics of the element are observed after the pulse is continuously applied, the ratio between the current value generated by the read voltage after writing and the current value generated by the read voltage after erasing, that is, I _on / I _off While maintaining the ratio at 10 ¹ or more, it can be confirmed that the operation is stable and normal. At this time, as described above, the negative voltage level and the positive voltage level can all be used as the voltage applied to the element because of the symmetrical characteristics of the element. For example, it is possible to apply an erase voltage of + 9V.

FIG. 14A is a diagram showing an energy band of a nonvolatile memory element using Alq ₃ as a conductive organic material layer and including an Al nanocrystal layer, and FIG. 14B is a diagram using Alq ₃ as a conductive organic material layer and a Ni nanocrystal. It is a figure which shows the energy band of the non-volatile memory element containing a layer.

As shown in FIGS. 14A and 14B, since Ni has a work function value larger than that of Al by about 0.87 eV, in the case of a nonvolatile memory element including a Ni nanocrystal layer, a conductive organic material layer and a nanocrystal The depth of the electron well formed by the layer is further deeper than that of the nonvolatile memory element including the Al nanocrystal layer. Thus, _I on _{/ I off} ratio of the nonvolatile memory device containing Al nanocrystal layer is about 10 ² (Fig. 6C, see, FIG. 8A) whereas, in the non-volatile memory device including a Ni nanocrystalline layer _{I on} / I _off ratio was found to increase to about 10 ⁴ (see FIG. 6D, etc. Figure 9A). Therefore, more intermediate resistance states can be shown between the low resistance state and the high resistance state, and the data retention capability can be improved.

  That is, any oxidizable metal may be used to form the nanocrystal layer, but it is preferable to use a metal having a high work function.

As described above, with reference to FIG 1A~ Figure 14B, as the conductive organic material layer, AIDCN, it has been described nonvolatile memory device using the Alq ₃ or alpha-NPD. In particular, in order to form a nanocrystal layer among the material layers constituting the nonvolatile memory element, a method of vapor-depositing a metal layer on the conductive organic material layer and plasma oxidizing the metal layer was employed.

  However, a high molecular compound may be used as the conductive organic material layer, and various methods for forming a nanocrystal surrounded by a barrier can be employed in addition to the deposition of a metal layer and the plasma oxidation method. This will be described with reference to FIGS. In particular, since the high-molecular substance is generally a polymer, the following description uses the terms conductive organic substance, high-molecular substance, and polymer, and these all represent the same thing.

  Hereinafter, detailed description of portions that are the same as those shown in FIGS. 1A to 14B will be omitted, and the differences will be mainly described. In particular, when a polymer compound is used as the conductive organic material layer, there is a great difference in the formation method of the nanocrystal or the nanocrystal layer, and this point will be mainly described. That is, in addition to a method for forming a nanocrystal layer by vapor deposition and plasma oxidation of a metal layer, a method for forming a nanocrystal layer by vapor deposition and curing (see FIGS. 15A to 17B), or a nanocrystal dispersed in a polymer layer The forming method (see FIGS. 18A to 21) will be additionally described.

  15A to 15H are views for explaining a method of manufacturing a nonvolatile memory element according to another embodiment of the present invention. Since the shape of each material layer constituting this nonvolatile memory element is the same as that of each material layer in FIGS. 2A to 2F, detailed description is omitted.

  As shown in FIG. 15A, the lower electrode 22 is formed on the substrate 21. At this time, the material constituting the lower electrode 22 and the formation method thereof are the same as the formation process of the first electrode 212 in FIG. 2A.

  As shown in FIG. 15B, the first polymer layer 23 is formed on the substrate 21 including the lower electrode 22. The first polymer layer 23 is preferably made of PVK (Poly (N-vinylcarbazole) and can be formed by a spin coating method. PVK is represented by the following chemical structural formula.

As shown in FIG. 15C, a first barrier material layer 24 is formed on the first polymer layer 23. Here, the first barrier material layer 24 forms a tunneling barrier for electrons surrounding the nanocrystal in the nanocrystal layer formed in the subsequent process. The first barrier material layer 24 is preferably formed by an ALD method. The first barrier material layer 24 is preferably made of a metal oxide (for example, Al ₂ O ₃ or TiO ₂ ).

  As shown in FIG. 15D, a metal layer 25 is formed on the first barrier material layer 24. The metal layer 25 can be formed by a vapor deposition method. The metal layer 25 can include all oxidizable metals and non-oxidizable metals. The metal layer 25 may be oxidizable or non-oxidizable (for example, Au). The thickness of the metal layer 25 is preferably in the range of 1 nm to 10 nm.

As shown in FIG. 15E, a second barrier material layer 26 is formed on the metal layer 25. Similar to the first barrier material layer 24, the second barrier material layer 26 is for forming an electron tunneling barrier surrounding the nanocrystal. The method for forming the second barrier material layer 26 is preferably the same as the method for forming the first barrier material layer 24. That is, the second barrier material layer 26 is preferably formed by an ALD method, and the second barrier material layer 26 is formed of a metal oxide, for example, Al ₂ O ₃ or TiO ₂ , similarly to the first barrier material layer 24. Preferably it consists of.

  As shown in FIG. 15F, a second polymer layer 27 is formed on the second barrier material layer 26. The method for forming the second polymer layer 27 is preferably the same as the method for forming the first polymer layer 23. The second polymer layer 27 is preferably made of PVK and can be formed by spin coating.

  As shown in FIG. 15G, the laminate formed on the substrate including the second polymer layer 27 is cured. By this curing, the first barrier material layer 24 below the metal layer 25 and the second barrier material layer 26 above the metal layer 25 surround the metal nanocrystals 25A formed in the metal layer 25, and the As a result, as shown in the drawing, the nanocrystal layer 200 including the metal nanocrystal 25A and the surrounding barrier 25B is formed. This curing is preferably performed at a temperature in the range of 150 ° C. to 300 ° C. for 0.5 hours to 4 hours.

  As shown in FIG. 15H, after the nanocrystal layer 200 is formed, the upper electrode 28 is formed on the second polymer layer 27. The material constituting the upper electrode 28 and the formation method thereof are the same as the formation of the second electrode 217 in FIG. 2F.

  The process shown in FIGS. 15A to 15H is different from FIGS. 2A to 3D regarding the formation of the nanocrystal layer. That is, the nanocrystal layer is formed in the polymer layer by curing the structure in which the polymer layer / barrier material layer / metal layer / barrier material layer / polymer layer are sequentially laminated. Also with this method, nanocrystals having a uniform size and distribution can be formed, so that stable device characteristics can be ensured.

16A and 16B are TEM photographs showing a cross section of the nonvolatile memory element formed by the method shown in FIGS. 15A to 15H. In particular, FIG. 16A is a TEM photograph of a non-volatile memory device using a conductive organic material layer, that is, PVK as a polymer layer and including Au nanocrystals surrounded by an Al ₂ O ₃ barrier, and FIG. 16B is a conductive organic material. using PVK as a layer, and is a TEM photograph of the nonvolatile memory device containing Au nanocrystals enclosed in TiO ₂ barrier.

As shown in FIGS. 16A and 16B, it can be seen that the Au nanocrystals are separated from each other by being surrounded by a barrier material, that is, Al ₂ O ₃ or TiO ₂ .

FIG. 17A is a diagram illustrating an energy band of a nonvolatile memory device using Au nanocrystals surrounded by an Al ₂ O ₃ barrier using PVK as a conductive organic material layer, and FIG. using PVK, and a diagram showing the energy band of the nonvolatile memory device containing Au nanocrystals enclosed in TiO ₂ barrier.

17A and 17B are substantially similar to the diagrams showing the energy bands of FIGS. 14A and 14B. That is, due to the energy level difference between the nanocrystal layer including the Au nanocrystal and the non-crystalline barrier (Al ₂ O ₃ or TiO ₂ ) surrounding the Au nanocrystal and the conductive organic layer PVK, the Au nanocrystal Electrons are charged in the crystal, and it is assumed that the current or resistance state and operating characteristics of the device are also similar to the nonvolatile memory device shown in FIGS. 1A to 14B.

  18A to 18C are diagrams for explaining a method of manufacturing a nonvolatile memory element according to still another embodiment. In this method, the formation of the polymer layer and the formation of the nanocrystal surrounded by the barrier are performed at a time, which is different from the above-described embodiment. Therefore, the nanocrystals formed in the polymer layer and the barriers surrounding them are separated from each other.

  As shown in FIG. 18A, the lower electrode 32 is formed on the substrate 31. The material constituting the lower electrode 32 and the method of forming the same are the same as in the case of forming the first electrode 212 in FIG. 2A.

  As shown in FIG. 18B, a polymer layer 34 including a plurality of nanocrystals 33A dispersed therein is formed on the lower electrode 32. Each nanocrystal 33A is surrounded by a barrier 33B around each nanocrystal 33A. As described above, a method for forming the polymer layer 34 in which the nanocrystals 33A surrounded by the barrier 33B are dispersed will be described later (see FIG. 19). Next, as shown in FIG. 18C, the upper electrode 35 is formed on the polymer layer 34. The material constituting the upper electrode 35 and the formation method thereof are the same as in the case of forming the second electrode 217 in FIG. 2F.

  FIG. 19 is a diagram for more specifically explaining the method of forming the polymer layer of FIG. 18B. In particular, FIG. 19 shows, as an example, a method for forming a polymer layer in which Au nanocrystals using CB (carbazole terminated thiol) as a barrier are horizontally dispersed.

As shown in FIG. 19, in order to synthesize the nanocrystal 33A surrounded by the barrier 33B, the processes of steps (A) to (B) are performed. First, in step (A), HAuCl ₄ as a metal salt is dissolved in DI water in an aqueous solvent to produce an aqueous solution of the metal salt. At this time, in the aqueous solution of the metal salt, the metal salt ionizes to H ⁺ and AuCl ₄ ⁻ and functions as a source of Au. In addition, TOAB (tetraoctylammonium) is dissolved in toluene in a non-aqueous solvent to produce a toluene solution containing ionized TOAB. At this time, the ionized TOAB serves as a phase transfer catalyst that moves the metal-containing ions AuCl ₄ ⁻ into the toluene solution in a subsequent step.

Next, in step (B), when the aqueous solution of the metal salt and the toluene solution in which TOAB is dissolved are stirred, AuCl ₄ ⁻ of the metal-containing ions moves to the toluene solution. At this time, stirring is preferably performed at a speed of 500 rpm or more.

CB is added to the toluene solution in this state as a dispersion stabilizer for making the subsequent dispersion of Au nanocrystals uniform, and stirred. This stirring is preferably performed at room temperature for 5 to 20 minutes. The molecular formula of CB as a dispersion stabilizer is C ₂₃ H ₃₁ NS, and its chemical name is 11-Carbazolyl dodecane thiol.

Next, in step (C), NaBH ₄ (sodium brohydride) is added as a reducing agent for reducing AuCl ₄ ⁻ to the toluene solution to which CB has been added in step (B) and stirred. This stirring is preferably performed at a speed of 500 rpm or more at room temperature for 3 to 10 hours.

  As a result, in step (D), a binding substance of Au nanocrystals and CB is formed in the toluene solution. At this time, since CB is formed in a shape surrounding Au nanocrystals, it not only serves as a dispersion stabilizer, but also functions as an electron tunneling barrier in the same manner as a barrier substance.

Next, in step (E), the toluene solvent is evaporated to leave a binding substance of Au nanocrystals and CB. This evaporation is preferably performed under a relatively low pressure condition of -1 Bar or less in a rotary evaporator.
Next, in step (F), the binding substance of Au nanocrystals and CB is dissolved in chloroform. This is for mixing the polymer, and PVK is mixed as a polymer in the chloroform solution.

  Finally, in step (G), a final solution in which Au nanocrystals surrounded by CB and the polymer are mixed is generated. When this solution is spin-coated on the substrate, the structure of the polymer layer 34 shown in FIG. 18B is formed. In the present embodiment, the nanocrystal 33A dispersed in the polymer layer 34 is Au, and the barrier 33B surrounding the nanocrystal 33A is CB.

  Even when the methods shown in FIGS. 18A to 19 are used, nanocrystals having a uniform size and distribution can be formed. In particular, a polymer layer containing nanocrystals can be formed at a time by using a spin coating method. Therefore, there is an advantage that the manufacturing process is simple.

  FIG. 20 is a TEM photograph showing a cross section of the nonvolatile memory element formed by the method shown in FIGS. 18A to 19. As shown in FIG. 20, it can be seen that Au nanocrystals are separated from each other and horizontally dispersed in the PVK polymer layer.

  FIG. 21 is a diagram illustrating an energy band of a nonvolatile memory device including a PVK polymer layer in which Au nanocrystals surrounded by a CB barrier are dispersed. It can be seen that FIG. 21 is substantially similar to the diagram showing the energy bands of FIGS. 14A and 14B. That is, due to the energy level difference between the Au nanocrystal surrounded by the CB barrier and PVK which is the conductive organic material layer, the Au nanocrystal is charged with electrons, thereby the current or resistance state of the device and the operating characteristics. Is presumed to be similar to the nonvolatile memory device shown in FIGS. 1A to 14B.

  FIG. 22 is a block diagram illustrating a nonvolatile memory element according to an embodiment of the present invention. As shown in FIG. 22, the nonvolatile memory element according to this embodiment includes a memory cell 2200, a drive unit 2400, and a control unit 2600.

  Usually, a memory element includes a cell array in which a plurality of cells are arrayed, and a peripheral circuit that performs operations for reading data from the memory cells, writing data into the memory cells, and the like. Since the nonvolatile memory element according to the present invention also has a similar structure, the memory cell 2200 is provided in the cell array, and the driver 2400 and the controller 2600 are provided in the peripheral circuit.

  Specifically, the memory cell 2200 has the same structure as FIG. 1A. That is, the memory cell 2200 includes the lower electrode 12 and the upper electrode 17 shown in FIG. 1A, and the first conductive organic material layer 13 and the second conductive organic material layer 16 formed between the lower electrode 12 and the upper electrode 17. A nanocrystal layer 15 formed between the first conductive organic material layer 13 and the second conductive organic material layer 16 and including a plurality of nanocrystals 15A surrounded by an amorphous barrier 15B. Similarly to FIG. 1B, the memory cell 2200 can include a first cell 1C and a second cell 2C stacked vertically, that is, in the height direction.

  Further, the memory cell 2200 can have the same structure as that in FIG. 18C. That is, the memory cell 2200 is formed between the lower electrode 32 and the upper electrode 35 of FIG. 18C and the lower electrode 32 and the upper electrode 35, and a plurality of nanocrystals 33A surrounded by the non-crystalline barrier 33B are dispersed. And a polymer layer 34. Similarly, the memory cell 2200 can have a structure in which a plurality of the cells in FIG. 18C are stacked in the vertical direction, that is, in the height direction.

  The driver 2400 drives the memory cell 2200 in order to operate the element. The driving unit 2400 applies an input voltage to the lower electrode and the upper electrode of the memory cell 2200, and the memory cell 2200 exhibits a high resistance state, a low resistance state, and a negative resistance state according to the input voltage. That is, the memory cell 2200 outputs a plurality of levels of current during a read operation.

  6A to 7H have described in detail the program, read, and erase operations, the driving unit 2400 applies a bias for these operations. In addition, a plurality of levels of data values are obtained in accordance with the output current or resistance state of the memory cell 2200 when the read operation is driven. The control unit 2600 controls the memory cell 2200 and the drive unit 2400 according to the operation mode of the element.

According to the embodiment of the present invention, the threshold voltage and the I _on / I _off ratio in the same device can be uniformly maintained by various manufacturing methods of nanocrystals. When the method of the present invention is applied, no data is lost even when no power is applied, low power consumption and high integration (memory cell size: 4F ² ) are possible. In addition, it is possible to secure nanocrystals having a uniform size and distribution while maintaining the characteristics of a PoRAM device having a high processing speed. Furthermore, according to the embodiment of the present invention, the unit cell can have a plurality of level data by utilizing the intermediate state of the bistable conductive characteristic, and the unit cells can be stacked in multiple layers.

  Although the technical idea of the present invention has been specifically described by the above-described embodiment, it should be noted that the above-described embodiment is for the purpose of explanation and is not limited thereto. . Moreover, if it is a normal expert in the technical field of this invention, a various change and improvement are possible within the range of the technical idea of this invention, and they also belong to the technical scope of this invention.

It is sectional drawing which shows the structure of the non-volatile memory element which concerns on one embodiment of this invention. It is sectional drawing which shows the structure of the non-volatile memory element which concerns on the modification of one embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on one embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on one embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on one embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on one embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on one embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on one embodiment of this invention. It is sectional drawing for demonstrating the concept of the formation method of a nanocrystal layer. It is sectional drawing for demonstrating the concept of the formation method of a nanocrystal layer. It is sectional drawing for demonstrating the concept of the formation method of a nanocrystal layer. It is sectional drawing for demonstrating the concept of the formation method of a nanocrystal layer. FIG. 4 is a TEM photograph and a lattice photograph showing a cross section of a nonvolatile memory element including an Al nanocrystal layer formed by the method shown in FIGS. 2A to 3D. FIG. 4 is a TEM photograph and a lattice photograph showing a cross section of a nonvolatile memory element including an Al nanocrystal layer formed by the method shown in FIGS. 2A to 3D. FIG. 4 is a TEM photograph and a lattice photograph showing a cross section of a nonvolatile memory element including an Al nanocrystal layer formed by the method shown in FIGS. 2A to 3D. FIG. 4 is a TEM photograph and a lattice photograph showing a cross section of a nonvolatile memory element including an Al nanocrystal layer formed by the method shown in FIGS. 2A to 3D. It is a graph which shows the XPS analysis result of the non-volatile memory element containing Al nanocrystal layer. It is a graph which shows the AES analysis result of the non-volatile memory element containing Al nanocrystal layer. FIG. 4 is a TEM photograph and a lattice photograph showing a cross section of a nonvolatile memory element including a Ni nanocrystal layer formed by the method shown in FIGS. 2A to 3D. FIG. 4 is a TEM photograph and a lattice photograph showing a cross section of a nonvolatile memory element including a Ni nanocrystal layer formed by the method shown in FIGS. 2A to 3D. It is a graph which shows the XPS analysis result of the non-volatile memory element containing Ni nanocrystal layer. It is a graph which shows the AES analysis result of the non-volatile memory element containing Ni nanocrystal layer. It is a graph which shows the voltage-current characteristic of the non-volatile memory element which uses (alpha) -NPD as a conductive organic substance layer which concerns on one embodiment of this invention, and has an Al nanocrystal layer. It is a graph which shows the voltage-current characteristic of the non-volatile memory element which uses AIDCN as a conductive organic substance layer and has an Al nanocrystal layer. The Alq ₃ is used as the conductive organic material layer, and is a graph showing voltage-current characteristics of a nonvolatile memory device having an Al nanocrystal layer. The Alq ₃ is used as the conductive organic material layer, and is a graph showing voltage-current characteristics of a nonvolatile memory device having a Ni nanocrystalline layer. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. It is a figure for demonstrating the mechanism by which the voltage-current characteristic of FIG. 6A is implement | achieved. The Alq ₃ is used as the conductive organic material layer, and is a graph showing voltage-current characteristics of a nonvolatile memory device when a cell having an Al nanocrystal layer which is two laminated. The Alq ₃ is used as the conductive organic material layer, and is a graph showing voltage-current characteristics of a nonvolatile memory device when a cell having an Al nanocrystal layer which is two laminated. The Alq ₃ is used as the conductive organic material layer, and is a graph showing voltage-current characteristics of a nonvolatile memory device when a cell having a Ni nanocrystalline layers 2 stacked. The Alq ₃ is used as the conductive organic material layer, and is a graph showing voltage-current characteristics of a nonvolatile memory device when a cell having a Ni nanocrystalline layers 2 stacked. It is a graph which shows the result of the retention test of the non-volatile memory element which uses (alpha) -NPD as a conductive organic substance layer and has an Al nanocrystal layer. It is a graph which shows the result of the retention capability test of the non-volatile memory element which uses AIDCN as a conductive organic substance layer and has an Al nanocrystal layer. The Alq ₃ is used as the conductive organic material layer, and is a graph showing the results of retention testing of non-volatile memory device having a Al nanocrystal layer. The Alq ₃ used as the conductive organic material layer, and is a graph showing the results of retention and durability test of the nonvolatile memory element having a Ni nanocrystalline layer. The Alq ₃ is used as the conductive organic material layer, and is a graph showing the results of retention and / or durability test of the nonvolatile memory device when a cell having an Al nanocrystal layer which is two laminated. The Alq ₃ is used as the conductive organic material layer, and is a graph showing the results of retention and / or durability test of the nonvolatile memory device when a cell having an Al nanocrystal layer which is two laminated. The Alq ₃ is used as the conductive organic material layer, and is a graph showing the results of retention and / or durability test of the nonvolatile memory device when a cell having a Ni nanocrystalline layers 2 stacked. The Alq ₃ is used as the conductive organic material layer, and is a graph showing the results of retention and / or durability test of the nonvolatile memory device when a cell having a Ni nanocrystalline layers 2 stacked. It is a graph which shows the operation characteristic of an element by application of a pulse signal. The Alq ₃ is used as the conductive organic material layer, and a diagram showing the energy band of the non-volatile memory device including Al nanocrystal layer. The Alq ₃ is used as the conductive organic material layer, and a diagram showing the energy band of the non-volatile memory device including a Ni nanocrystalline layer. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on other embodiment of this invention. 16 is a TEM photograph showing a cross section of a nonvolatile memory element formed by the method shown in FIGS. 15A to 15H. FIG. 16 is a TEM photograph showing a cross section of the nonvolatile memory element formed by the method shown in FIGS. 15A to 15H. FIG. Using PVK as a conductive organic material layer, and a diagram showing the energy band of the non-volatile memory device comprising Al ₂ O ₃ barrier surrounded by Au nanocrystals. Using PVK as a conductive organic material layer, and a diagram showing the energy band of the nonvolatile memory device containing Au nanocrystals enclosed in TiO ₂ barrier. It is a figure for demonstrating the manufacturing method of the non-volatile memory element based on further embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element based on further embodiment of this invention. It is a figure for demonstrating the manufacturing method of the non-volatile memory element which concerns on further embodiment of this invention. It is a figure for demonstrating more specifically the formation method of the polymer layer of FIG. 18B. 20 is a TEM photograph showing a cross section of the nonvolatile memory element formed by the method shown in FIGS. 18A to 19. It is a figure which shows the energy band of the non-volatile memory element containing the PVK polymer layer in which Au nanocrystals surrounded by the CB barrier were dispersed. 1 is a block diagram showing a configuration of a nonvolatile memory element according to an embodiment of the present invention.

Explanation of symbols

11 Substrate 12 Lower electrode 13 First conductive organic material layer 15 Nanocrystal layer 16 Second conductive organic material layer 17 Upper electrode

Claims (104)

A first electrode and a second electrode formed on the substrate;
A conductive organic layer formed between the first electrode and the two electrodes;
A unit cell formed in the conductive organic material layer and including a nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier, and the unit cell is one of at least three levels of current A non-volatile memory device, comprising: a driving unit that drives a unit cell by applying a predetermined input voltage between the first electrode and the second electrode so as to output one signal. The nanocrystal layer is
It is formed by vapor deposition of an oxidizable first metal layer and plasma oxidation of the first metal layer, the nanocrystal is made of the first metal, and the non-crystalline barrier is oxidized of the first metal. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory element is made of a material. The nanocrystal layer is
The nanocrystal is formed by curing a structure including a predetermined material layer constituting the non-crystalline barrier and a second metal layer between the predetermined material layers in the conductive organic material layer. 2. The nonvolatile memory device according to claim 1, wherein the second barrier metal is made of the second metal and the non-crystalline barrier is made of the predetermined substance. The nanocrystal layer is
The nanocrystal composed of any one metal selected from Al, Mg, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof, and the non-crystal composed of an oxide of the selected metal. The non-volatile memory device according to claim 1, further comprising an ionic barrier. The nonvolatile memory device according to claim 1, wherein the nanocrystal is made of Al, and the non-crystalline barrier is made of Al oxide (Al _x O _y ). The nonvolatile memory element according to claim 1, wherein the nanocrystal is made of Ni, and the non-crystalline barrier is made of Ni oxide (Ni _x O _y ). The nonvolatile memory element according to claim 1, wherein the nanocrystal is made of Au. The nonvolatile memory device according to claim 7, wherein the non-crystalline barrier is made of Al ₂ O ₃ or TiO ₂ . The non-volatile memory element according to claim 1, wherein the conductive organic material layer is made of Alq ₃ , α-NPD, or AIDCN.   The non-volatile memory element according to claim 1, wherein the conductive organic material layer is made of a polymer.   The nonvolatile memory device according to claim 10, wherein the polymer is PVK. The input voltage is
A first data voltage in a region from a threshold voltage to a maximum current voltage; a second data voltage in a negative resistance region having a value larger than the maximum current voltage and a current amount decreasing when the input voltage increases; The nonvolatile memory device according to claim 1, comprising: The unit cell has a maximum output current upon application of the first data voltage;
The unit cell is configured to output one or more levels of current lower than the maximum output current according to a voltage level of the applied second data voltage when the second data voltage is applied. The nonvolatile memory element according to claim 12, wherein the nonvolatile memory element is formed.   The nonvolatile memory according to claim 13, wherein the driving unit is configured to erase data stored in the unit cell by applying a voltage level higher than the second data voltage. Memory device.   The nonvolatile memory device of claim 14, wherein the unit cell is configured to output a minimum current at an initial stage or after the erase operation.   The non-volatile device according to claim 12, wherein the driving unit is configured to read data stored in the unit cell by applying a voltage level lower than the threshold voltage. Memory element. A first electrode and a second electrode formed on the substrate;
A conductive organic material layer formed between the first electrode and the second electrode;
A unit cell formed in the conductive organic material layer and including a nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier, and the unit cell has a high resistance state, a low resistance state, and a negative polarity A non-volatile device comprising driving means for driving the unit cell by applying a predetermined input voltage between the first electrode and the second electrode so as to be in any one of the resistance states. Memory element. The nanocrystal layer is
It is formed by vapor deposition of an oxidizable first metal layer and plasma oxidation of the first metal layer, the nanocrystal is made of the first metal, and the non-crystalline barrier is oxidized of the first metal. The nonvolatile memory device according to claim 17, wherein the nonvolatile memory element is made of a material. The nanocrystal layer is
The nanocrystal is formed by curing a structure including a predetermined material layer constituting the non-crystalline barrier and a second metal layer between the predetermined material layers in the conductive organic material layer. The non-volatile memory device according to claim 17, wherein the non-crystalline barrier is made of the second metal, and the non-crystalline barrier is made of the predetermined substance. The nanocrystal layer is
The nanocrystal composed of any one metal selected from Al, Mg, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof, and the non-crystal composed of an oxide of the selected metal. The non-volatile memory device according to claim 17, further comprising an ionic barrier. The nonvolatile memory device according to claim 17, wherein the nanocrystal is made of Al, and the non-crystalline barrier is made of Al oxide (Al _x O _y ). The nanocrystals comprised Ni, non-volatile memory device of claim 17, wherein the non-crystalline barrier is being Ni oxide (Ni x _{O y).}   The nonvolatile memory device according to claim 17, wherein the nanocrystal is made of Au. The nonvolatile memory device of claim 23, wherein the non-crystalline _barrier, characterized in that it consists of Al 2 _{O 3} or TiO _2. Wherein the conductive organic material layer, _Alq 3, nonvolatile memory device according to any one of claims 17,18,20,21 and 22 characterized by comprising the alpha-NPD or AIDCN.   25. The nonvolatile memory element according to claim 17, wherein the conductive organic layer is made of a polymer.   The nonvolatile memory device of claim 26, wherein the polymer is PVK. When the input voltage is in the first voltage range, the unit cell is in the high resistance state,
When the input voltage is in a second voltage range higher than the first voltage range, the unit cell is in the low resistance state,
The nonvolatile memory device of claim 17, wherein the unit cell is configured to be in the negative resistance state when the input voltage is in a third voltage range higher than the second voltage range. .   When the input voltage is in a fourth voltage range higher than the third voltage range, the unit cell is configured to change from the low resistance state or the negative resistance state to the high resistance state. The nonvolatile memory element according to claim 28. The unit cell is
The first output current is the lowest in the high resistance state, the second output current is the highest in the low resistance state, and the third output current is the difference between the first output current and the second output current in the negative resistance state. The non-volatile memory device according to claim 17, wherein the non-volatile memory device is configured to have a current between them.   29. The nonvolatile memory device according to claim 28, wherein the negative resistance state is configured to indicate a plurality of states having different resistance values according to the level of the input voltage. A first electrode and a second electrode formed on the substrate;
A conductive organic material layer formed between the first electrode and the second electrode;
A nanocrystal layer including a plurality of nanocrystals formed in the conductive organic material layer and surrounded by an amorphous barrier;
When the input voltage applied between the first electrode and the second electrode is in the first voltage range, an input data read operation is performed.
When the input voltage is in a second voltage range higher than the first voltage range, a write operation of first input data is performed,
When the input voltage is in a third voltage range higher than the second voltage range, a write operation of second input data is performed,
A non-volatile memory device, wherein the first input data or the second input data is erased when the input voltage is in a fourth voltage range higher than the third voltage range. . The nanocrystal layer is
It is formed by vapor deposition of an oxidizable first metal layer and plasma oxidation of the first metal layer, the nanocrystal is made of the first metal, and the non-crystalline barrier is oxidized of the first metal. The nonvolatile memory device according to claim 32, wherein the nonvolatile memory device is made of a material. The nanocrystal layer is
The nanocrystal is formed by curing a structure including a predetermined material layer constituting the non-crystalline barrier and a second metal layer between the predetermined material layers in the conductive organic material layer. 33. The nonvolatile memory element according to claim 32, wherein the non-volatile barrier is made of the second metal, and the non-crystalline barrier is made of the predetermined substance. The nanocrystal layer is
The nanocrystal composed of any one metal selected from Al, Mg, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof, and the non-crystal composed of an oxide of the selected metal. The non-volatile memory device according to claim 32, further comprising an ionic barrier. The non-volatile memory device according to claim 32, wherein the nanocrystal is made of Al, and the non-crystalline barrier is made of Al oxide (Al _x O _y ). The nonvolatile memory device according to claim 32, wherein the nanocrystal is made of Ni, and the non-crystalline barrier is made of Ni oxide (Ni _x O _y ).   The nonvolatile memory device according to claim 32, wherein the nanocrystal is made of Au. The nonvolatile memory device of claim 38, wherein the non-crystalline _barrier, characterized in that it consists of Al 2 _{O 3} or TiO _2. Wherein the conductive organic material layer, _Alq 3, nonvolatile memory device according to any one of claims 32,33,35,36 and 37 characterized by comprising the alpha-NPD or AIDCN.   40. The nonvolatile memory device according to claim 32, wherein the conductive organic material layer is made of a polymer.   The nonvolatile memory device of claim 41, wherein the polymer is PVK. When the first input data is written, a maximum current is output during the read operation.
When data is erased, a minimum current is output during the read operation,
When the second input data is written, during the read operation, a predetermined level of current is applied between the maximum current and the minimum current according to a voltage level applied within the third voltage range. The nonvolatile memory device according to claim 32, wherein the nonvolatile memory device is configured to be output. The first voltage range is a voltage range from 0.1 V to a threshold voltage;
The second voltage range is a voltage range from the threshold voltage to a maximum current voltage;
The third voltage range is equal to or greater than the maximum current voltage and is a negative resistance region voltage range in which the current decreases when the voltage increases,
The nonvolatile memory element according to claim 32, wherein the fourth voltage range is configured to be a voltage range higher than a voltage of the negative resistance region. A first electrode and a second electrode formed on the substrate;
A first conductive organic material layer formed between the first electrode and the second electrode;
A first cell comprising a first nanocrystal layer including a plurality of nanocrystals formed in the first conductive organic material layer and surrounded by an amorphous barrier; and the second electrode and the third electrode;
A second conductive organic material layer formed between the second electrode and the third electrode;
A second cell comprising a second nanocrystal layer formed in the second conductive organic material layer and including a plurality of nanocrystals surrounded by an amorphous barrier;
A nonvolatile memory element, wherein the first cell and the second cell are stacked. The first cell or the second cell is
According to an input voltage applied between the first electrode and the second electrode or between the second electrode and the third electrode, a plurality of levels of current are output during a read operation. 46. The nonvolatile memory device according to claim 45, wherein: The first cell or the second cell is
According to an input voltage applied between the first electrode and the second electrode or between the second electrode and the third electrode, the high resistance state, the low resistance state, or the negative resistance state is configured. The nonvolatile memory device according to claim 45, wherein the nonvolatile memory device is a non-volatile memory device. The first cell or the second cell is
When the input voltage applied between the first electrode and the second electrode or between the second electrode and the third electrode is in the first voltage range, an input data read operation is performed.
When the input voltage is in a second voltage range higher than the first voltage range, a write operation of first input data is performed,
When the input voltage is in a third voltage range higher than the second voltage range, a write operation of second input data is performed,
46. The method according to claim 45, wherein the first input data or the second input data is erased when the input voltage is in a fourth voltage range higher than the third voltage range. The nonvolatile memory element described. A lower electrode and an upper electrode formed on the substrate;
A non-volatile memory device, comprising: a polymer layer formed between the lower electrode and the upper electrode and having a plurality of nanocrystals dispersed therein surrounded by an amorphous barrier.   50. The nonvolatile memory device according to claim 49, wherein the nanocrystal is made of metal.   51. The nonvolatile memory device according to claim 50, wherein the nanocrystal is made of Au.   50. The nonvolatile memory device according to claim 49, wherein the non-crystalline barrier is made of CB (carbazole terminated thiol).   The nonvolatile memory device of claim 49, wherein the polymer layer is made of PVK.   The nonvolatile memory device according to claim 49, wherein the nonvolatile memory device is configured to output a plurality of levels of current during a read operation according to an input voltage applied between the lower electrode and the upper electrode. .   50. The nonvolatile memory device of claim 49, wherein the nonvolatile memory device has a high resistance state, a low resistance state, or a negative resistance state according to an input voltage applied between the lower electrode and the upper electrode. When the input voltage applied between the lower electrode and the upper electrode is in the first voltage range, an input data read operation is performed,
When the input voltage is in a second voltage range higher than the first voltage range, a write operation of first input data is performed,
When the input voltage is in a third voltage range higher than the second voltage range, a write operation of second input data is performed,
50. The erasing operation of the first input data or the second input data is performed when the input voltage is in a fourth voltage range higher than the third voltage range. The nonvolatile memory element described. A first electrode and a second electrode formed on the substrate;
A first cell comprising a first polymer layer formed by dispersing a plurality of nanocrystals surrounded by a non-crystalline barrier formed between the first electrode and the second electrode; and the second electrode and the third electrode. Electrodes,
A second cell comprising a second polymer layer formed between the second electrode and the third electrode and having a plurality of nanocrystals dispersed therein surrounded by an amorphous barrier;
A nonvolatile memory element, wherein the first cell and the second cell are stacked. The first cell or the second cell is
According to an input voltage applied between the first electrode and the second electrode or between the second electrode and the third electrode, a plurality of levels of current are output during a read operation. 58. The non-volatile memory device according to claim 57, wherein: The first cell or the second cell is
According to an input voltage applied between the first electrode and the second electrode or between the second electrode and the third electrode, the high resistance state, the low resistance state, or the negative resistance state is configured. The nonvolatile memory device according to claim 57, wherein the nonvolatile memory device is a non-volatile memory device. The first cell or the second cell is
When the input voltage applied between the first electrode and the second electrode or between the second electrode and the third electrode is in the first voltage range, an input data read operation is performed.
When the input voltage is in a second voltage range higher than the first voltage range, a write operation of first input data is performed,
When the input voltage is in a third voltage range higher than the second voltage range, a write operation of second input data is performed,
58. The erasure operation of the first input data or the second input data is performed when the input voltage is in a fourth voltage range higher than the third voltage range. The nonvolatile memory element described. Forming a first electrode on a substrate;
Forming a first conductive organic material layer on the substrate including the first electrode;
Forming a first nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier on the first conductive organic material layer;
Forming a second conductive organic material layer on the first conductive organic material layer including the first nanocrystalline layer; and forming a second electrode on the substrate including the second conductive organic material layer. Forming one cell;
Forming a third conductive organic material layer on the substrate including the second electrode;
Forming a second nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier on the third conductive organic material layer;
Forming a fourth conductive organic layer on the third conductive organic layer including the second nanocrystal layer; and forming a third electrode on the substrate including the fourth conductive organic layer. A method of manufacturing a nonvolatile memory device, comprising: forming two cells. Forming the first nanocrystal layer or the second nanocrystal layer comprises:
Depositing an oxidizable first metal layer;
Plasma oxidizing the first metal layer,
62. The method of manufacturing a nonvolatile memory element according to claim 61, wherein the nanocrystal is made of the first metal, and the non-crystalline barrier is made of an oxide of the first metal. Depositing the first metal layer comprises:
The first metal material is subjected to a pressure in the range of 10 ⁻⁶ Pa to 10 ⁻³ Pa, a temperature in the range of 800 ° C. to 1500 ° C., and a deposition rate in the range of 0.1 to 7.0 kg / s. 64. The method of manufacturing a nonvolatile memory device according to claim 62, wherein the method is performed by evaporation. Depositing the first metal layer comprises:
64. The method of manufacturing a nonvolatile memory element according to claim 63, wherein the non-volatile memory element is produced by evaporating Al at a deposition rate in a range of 1.0 to 5.0 / s. Depositing the first metal layer comprises:
64. The method of manufacturing a nonvolatile memory element according to claim 63, wherein the method is performed by evaporating Ni at a deposition rate in a range of 0.1 [deg.] / S to 1.0 [deg.] / S. The plasma oxidation step comprises:
Treatment for 50 seconds to 500 seconds by introducing O ₂ gas under RF power in the range of 50 W to 300 W, AC bias in the range of 100 V to 200 V, and pressure in the range of 0.5 Pa to 3.0 Pa. 64. The method of manufacturing a nonvolatile memory element according to claim 62, wherein: The first nanocrystal layer or the second nanocrystal layer is
The nanocrystal composed of any one metal selected from Al, Mg, Ti, Zn, Fe, Ni, Sn, Pb, Cu and alloys thereof, and the non-crystal composed of an oxide of the selected metal. 62. The method of manufacturing a nonvolatile memory device according to claim 61, further comprising: In the first nanocrystal layer or the second nanocrystal layer,
It said nanocrystals is made of Al, a method of manufacturing a nonvolatile memory device of claim 61, wherein the non-crystalline barrier characterized by comprising the Al oxide (Al x _{O y).} In the first nanocrystal layer or the second nanocrystal layer,
The nanocrystals comprised Ni, a method of manufacturing a nonvolatile memory device of claim 61, wherein the non-crystalline barrier is being Ni oxide (Ni x _{O y).} In the first nanocrystal layer or the second nanocrystal layer,
62. The method of manufacturing a nonvolatile memory element according to claim 61, wherein the nanocrystal is made of Au. In the first nanocrystal layer or the second nanocrystal layer,
Method of manufacturing a nonvolatile memory device of claim 70, wherein the non-crystalline barrier, characterized in that it consists of Al ₂ O ₃ or TiO _2. The first conductive organic layer to the fourth conductive organic layer are:
Alq _3, a method of manufacturing a nonvolatile memory element according to any one of claims 61 to 69, characterized in that it consists of alpha-NPD or AIDCN. The first conductive organic layer to the fourth conductive organic layer are:
72. The method of manufacturing a nonvolatile memory element according to any one of claims 61, 70 and 71, comprising a polymer. Forming a first electrode on a substrate;
Forming a first conductive organic material layer on the substrate including the first electrode;
Forming a first barrier material layer on the first conductive organic material layer;
Forming a predetermined metal layer on the first barrier material layer;
Forming a second barrier material layer on the predetermined metal layer;
Forming a second conductive organic material layer on the first conductive organic material layer including the second barrier material layer;
Curing the formed laminate including the second conductive organic layer;
Forming a second electrode on the substrate including the second conductive organic material layer,
Forming a nanocrystal layer including a plurality of nanocrystals surrounded by an amorphous barrier between the first conductive organic material layer and the second conductive organic material layer;
The method of manufacturing a nonvolatile memory device, wherein the nanocrystal is made of a metal of the predetermined metal layer, and the non-crystalline barrier is made of the first barrier material and the second barrier material.   The method of claim 74, wherein the first conductive organic material layer and the second conductive organic material layer are made of a polymer.   The method of claim 75, wherein the polymer is PVK.   75. The method of claim 74, wherein the first barrier material layer and the second barrier material layer are made of a metal oxide. Method of manufacturing a nonvolatile memory device of claim 77, wherein the metal oxide, characterized in that a Al ₂ O ₃ or TiO _2. Forming the first barrier material layer and the second barrier material layer;
75. The method of manufacturing a nonvolatile memory device according to claim 74, wherein the method is performed by an ALD method.   75. The method of manufacturing a nonvolatile memory element according to claim 74, wherein the predetermined metal layer is made of Au. The curing step comprises:
75. The method of manufacturing a nonvolatile memory element according to claim 74, wherein the treatment is performed at a temperature in the range of 150 [deg.] C. to 300 [deg.] C. for 0.5 hours to 4 hours. Forming a lower electrode on the substrate;
Forming a polymer layer in which a plurality of nanocrystals surrounded by an amorphous barrier are dispersed on a substrate including the lower electrode;
Forming a top electrode on the substrate including the polymer layer. A method for manufacturing a non-volatile memory device.   83. The method of manufacturing a nonvolatile memory element according to claim 82, wherein the nanocrystal is made of Au.   83. The method of manufacturing a nonvolatile memory device according to claim 82, wherein the non-crystalline barrier is made of CB (carbazole terminated thiol). 83. The method of manufacturing a nonvolatile memory element according to claim 82, wherein the polymer layer is made of PVK. Forming the polymer layer comprises:
Synthesizing a plurality of nanocrystals surrounded by the non-crystalline barrier;
Mixing the synthesized material with a polymer;
83. The method of claim 82, further comprising spin-coating the mixed material on the substrate including the lower electrode. Synthesizing the plurality of nanocrystals,
Stirring the aqueous solution of the first metal salt and the first non-aqueous solution to form first metal-containing ions in the first non-aqueous solution;
Adding and stirring a dispersion stabilizer in the first non-aqueous solution containing the first metal-containing ions;
Adding a reducing agent that reduces the first metal-containing ion to the first non-aqueous solution containing the first metal-containing ion, and stirring.
89. The method of claim 86, wherein the nanocrystal is made of the reduced first metal, and the non-crystalline barrier is made of the dispersion stabilizer. Forming a first metal-containing ion in the first non-aqueous solution;
88. The method of manufacturing a nonvolatile memory device according to claim 87, wherein the method is performed in the presence of a phase transfer catalyst. The phase transfer catalyst is TOAB;
90. The method of manufacturing a nonvolatile memory device according to claim 88, wherein the first non-aqueous solution is a toluene solution.   88. The method of manufacturing a nonvolatile memory element according to claim 87, wherein the first metal is Au.   88. The method of manufacturing a nonvolatile memory element according to claim 87, wherein the dispersion stabilizer is CB (carbazole terminated thiol). Method of manufacturing a nonvolatile memory device of claim 87 wherein said reducing agent is NaBH _4. After adding and stirring the reducing agent,
Evaporating the first non-aqueous solution;
88. The method of claim 87, further comprising mixing the nanocrystals surrounded by the non-crystalline barrier remaining after evaporation into a second non-aqueous solution. Method. The first non-aqueous solution is a toluene solution;
94. The method of manufacturing a nonvolatile memory element according to claim 93, wherein the second non-aqueous solution is a chloroform solution. Forming a first metal-containing ion in the first non-aqueous solution;
88. The method of manufacturing a nonvolatile memory element according to claim 87, wherein stirring is performed at a speed of 500 rpm or more. Adding and stirring the dispersion stabilizer,
88. The method of manufacturing a nonvolatile memory element according to claim 87, wherein the process is performed for 5 minutes to 20 minutes at room temperature. Adding and stirring the reducing agent,
88. The method of manufacturing a nonvolatile memory element according to claim 87, wherein the processing is performed at a speed of 500 rpm or more for 3 hours to 10 hours at room temperature. Evaporating the first non-aqueous solution comprises:
94. The method of manufacturing a nonvolatile memory element according to claim 93, wherein the process is performed under a pressure condition of -1 Bar or less in a rotary evaporator. Forming a first barrier material layer on a substrate;
Forming a metal layer on the first barrier material layer;
Forming a second barrier material layer on the metal layer;
Curing the formed laminate including the second barrier material layer;
A method of forming a nanocrystal layer, comprising forming a plurality of metal nanocrystals surrounded by the first barrier material and the second barrier material.   The method of claim 99, wherein the first barrier material layer and the second barrier material layer are made of a metal oxide. Method of forming a nanocrystal layer according to claim 100, wherein the metal oxide _is Al 2 _{O 3} or TiO _2. Forming the first barrier material layer and the second barrier material layer;
The method for forming a nanocrystal layer according to claim 99, which is performed by an ALD method.   The method for forming a nanocrystal layer according to claim 99, wherein the predetermined metal layer is made of Au. The curing step comprises:
The method for forming a nanocrystal layer according to claim 99, wherein the treatment is performed for 0.5 hours to 4 hours at a temperature in the range of 150 ° C to 300 ° C.