KR20080053099A - Non-volatile memory element having charge trap layers and method of fabricating the same - Google Patents

Abstract

A nonvolatile memory device including plural charge trap layers and a manufacturing method thereof are provided to extend a retention time of a memory even though a small defect is produced on a charge trap layer. A nonvolatile memory device includes a tunnel insulating layer(120), a charge trap layer(130), a blocking insulating layer(140) and a gate electrode(150) which are sequentially deposited on a semiconductor substrate(110). The charge trap layer has a first trap layer(131) made of nano-crystal, and a second trap layer(132) formed on the first trap layer and made of nano-crystal having a diameter larger than that of the first trap layer. The first trap layer and the second trap layer are made of any one selected from the group consisting of GaN, AlxGa(1-x)N and AlxInyGa(1-x-y)N.

Description

Non-volatile memory element having charge trap layers and method of fabricating the same}

1 is a cross-sectional view illustrating an example of a conventional nonvolatile memory device.

2 is a cross-sectional view illustrating a configuration of a nonvolatile memory device according to an exemplary embodiment of the present invention.

3 and 4 are electron micrographs of GaN nanocrystals and AlGaN nanocrystals deposited on silicon oxide, respectively.

5 and 6 are graphs of the gate current characteristics according to the gate voltage of the device fabricated using GaN nanocrystals and AlGaN nanocrystals as charge trap layers, respectively.

7 is a C-V characteristic graph of a memory device using GaN nanocrystals or AlGaN nanocrystals as a charge trap layer.

8 is a graph showing room temperature retention characteristics of a nonvolatile memory device using Si ₃ N ₄ , AlGaN, and GaN as a charge trap layer.

* Description of Signs of Major Parts of Drawings *

100: nonvolatile memory device 110: substrate

120 tunnel insulating film 130 charge trap layer

131: first trap layer 132: second trap layer

140: blocking insulating film 150: gate electrode

The present invention relates to a nonvolatile memory device in which a trap layer of electric charge is composed of a plurality of nanocrystal layers.

Recently, various types of memory devices having nonvolatile characteristics have emerged. FIG. 1 is a diagram illustrating a structure of a sonos type memory device 10 using a charge trap layer as a storage node. A tunnel insulating film 12 on the silicon substrate 11 on which the source region S and the drain region D are formed; A charge trap layer 13; The blocking insulating film 14 is laminated | stacked. The gate electrode 15 is formed on the blocking insulating film 14. The tunnel insulating film 12 and the blocking insulating film 14 may be formed of SiO ₂ . The charge trap layer 13 may be, for example, a Si ₃ N ₄ layer. When a positive bias voltage is applied to the gate electrode 15, electrons are collected in the charge trap layer 13, thereby acting on the channel between the source region S and the drain region D. As the state of the electric field changes, the conduction characteristics change. By assigning a value of 1 or 0 to the charge trap layer 13 according to the degree of electron trapping, the memory device 10 may store / read 1-bit information.

However, since the charge trapping layer of the conventional Sonos memory device is formed of a thin film, the charge may be lost even by a single defect, and thus the retention characteristics of the memory may be poor.

On the other hand, US Patent Publication No. 2005-0072989 discloses a non-volatile memory made of a nano-crystal state as a floating gate.

It is an object of the present invention to provide a nonvolatile memory device having a charge trap layer in which nanocrystals made of a group III-nitride material are densely formed.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device having the charge trap layer.

A nonvolatile memory device having a plurality of charge trap layers of the present invention for achieving the above object is:

In a nonvolatile memory device in which a tunnel insulating film, a charge trap layer, a blocking insulating film, and a gate electrode are sequentially stacked on a semiconductor substrate,

The charge trap layer includes a first trap layer made of nanocrystals, and a second trap layer made of nanocrystals having a larger diameter than the first trap layer and formed on the first trap layer.

The first trap layer and the second trap layer are GaN, Al _x Ga _{1 - x} N, In _y Ga _{1 - y} N, Al _x In _y Ga _{1 -x- y} N (0 <x, y, x + y≤1) characterized in that the material is made of.

According to the present invention, the first trap layer is preferably made of nano-crystal of 0.5 ~ 3 nm diameter.

In addition, the first trap layer may be made of Al _x Ga _{1 - x} N nanocrystals ((0 <x ≦ 1).

According to the present invention, the second trap layer may be made of nanocrystals having a diameter of 3 to 20 nm.

In addition, the second trap layer has a smaller band gap than the first trap layer, and preferably, the second trap layer is formed of the GaN nanocrystal or the In _y Ga _{1 - y} N nanocrystal ((0 <y≤ 1) consists of.

According to the present invention, the blocking insulating layer is a hafnium oxide (HfO ₂ ) layer.

According to the present invention, a source region and a drain region are further formed in the semiconductor substrate outside the tunnel insulating layer.

Method of manufacturing a nonvolatile memory device having a plurality of charge trap layer of the present invention for achieving the above another object:

A tunnel insulating film, a charge trap layer, a blocking insulating film, and a gate electrode are sequentially stacked on the semiconductor substrate, and the charge trap layer is formed on the first trap layer made of nanocrystals and the first trap layer. It has a second trap layer made of nano crystals of a larger diameter than the first trap layer,

The first trap layer and the second trap layer are GaN, Al _x Ga _{1 - x} N, In _y Ga _{1 - y} N, Al _x In _y Ga _{1 -x- y} N (0 <x, y, x + In the method of manufacturing a nonvolatile memory device made of a material selected from y≤1),

The first trap layer and the second trap layer are each sequentially deposited at 300 ~ 900 ℃.

According to the present invention, the first trap layer and the second trap layer are supplied to the nitrogen element 10-10000 times more than the corresponding group 3 element, MOCVD, MBE, CBE, MOMBE, sputtering method to be deposited by any one method Can be.

Hereinafter, preferred embodiments of a nonvolatile memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a configuration of a nonvolatile memory device 100 according to an exemplary embodiment of the present invention. The tunnel insulating film 120, the charge trap layer 130, the blocking insulating film 140, and the gate electrode 150 are sequentially stacked on the silicon substrate 110 having the source region S and the drain region D. Have.

The tunnel insulating layer 120 may be formed of SiO ₂ having a thickness of 4 nm.

The charge trap layer 130 includes a first trap layer 131 which is a seed layer having a diameter of 0.5 to 3 nm, and a second trap layer 132 which is formed on the first trap layer 131 and has a diameter of 3 to 20 nm. ). The first trap layer 131 may be formed at a high density on the tunnel insulating layer 120, and the second trap layer 132 may be formed at a high density on the first trap layer 131 of high density.

The first trap layer 131 and the second trap layer 132 are GaN, Al _x Ga _{1 - x} N, In _y Ga _{1 - y} N, Al _x In _y Ga _1-xy N (0 <x, y , x + y ≦ 1), and may be formed of nanocrystals made of a selected material.

The blocking insulating layer 140 has a large dielectric constant, and may be formed to have a thickness of 20 nm with hafnium oxide (HfO ₂ ) having a larger band gap than the first trap layer 131 and the second trap layer 132. In addition, the gate electrode 150 may be formed of aluminum (Al).

3 and 4 are electron microscopy (SEM) photographs of GaN nanocrystals and AlGaN nanocrystals deposited on silicon oxide, respectively.

3 and 4, GaN nanocrystals and AlGaN nanocrystals are well grown on SiO ₂ / Si by MOCVD. The GaN nanocrystals and AlGaN nanocrystals were formed using a source of trimethyl gallium (TMGa), trimethyl aluminum (TMAl) and an NH ₃ nitride source.

GaN nanocrystals were grown on a SiO ₂ / Si substrate at 550 ° C and a V / III atomic ratio of 8000. In general, the nitride based nitride semiconductor thin film is grown at a very low temperature of 550 ℃ in the present invention compared to the growth at 900 ~ 1100 ℃ to suppress the desorption (desorption) of SiO2 as a tunnel insulator. Low temperature growth is important because SiO2 desorption occurs when growing at high temperature like general III-nitride series.

3, GaN nanocrystals are formed in an island shape. On the other hand, as shown in Figure 4, AlGaN nanocrystals are formed at a high density, the diameter thereof is reduced. This shows that AlGaN is 3-dimensional growth at low temperature. Therefore, the first trap layer 131 is formed of a high density layer of AlGaN nanocrystals, and the second trap layer 132 is formed of a material having a smaller band gap than the first trap layer 131, for example, GaN nano crystals or in _y. It is preferable to form Ga _{1 - y} N nanocrystals ((0 <y ≦ 1). Thus, the second trap layer 132 acts as a main trap layer.

In particular, the first trap layer 131 may be formed of a seed layer having a size of 0.5 to 3 nm, and the second trap layer 132 may be formed to have a thickness of about 3 to 20 nm. The AlGaN nanocrystals as the first trap layer 131 are formed at a high density as a seed layer, and thus the second trap layer 132 formed on the first trap layer 131 may be formed at a high density. Accordingly, the first trap layer 131 serves as a seed for forming a high density of the second trap layer 132.

The first trap layer 131 and the second trap layer 132 may be formed by CVD, MBE, MOMBE, CBE, and sputtering methods other than MOCVD.

The first trap layer and the second trap layer may be formed by supplying 10 to 10,000 times more nitride elements than the corresponding Group 5 elements at 300 to 900 ° C., respectively.

5 and 6 are graphs of gate current characteristics according to gate voltages of devices fabricated using GaN nanocrystals and AlGaN nanocrystals as charge trap layers, respectively. It shows that GaN nanocrystals and AlGaN nanocrystals act as charge trap layers.

7 is a C-V characteristic graph of a memory device using GaN nanocrystals or AlGaN nanocrystals as a charge trap layer. It is shown that when the charge is trapped by the application of voltage in the erased state, that is, in the programmed state, the plate band is shifted, which shows that the GaN nanocrystals or AlGaN nanocrystals act as capacitors. .

8 is a graph showing room temperature retention characteristics of a nonvolatile memory device using Si ₃ N ₄ , AlGaN, and GaN as a charge trap layer. The solid graph is a characteristic when the memory device is used for the first time, and the hollow graph is a graph showing the characteristic of the memory that has performed data recording / erasing 1000 times.

Referring to FIG. 8, in a sonos memory device using Si ₃ N ₄ as a charge trap layer, a phenomenon in which a charge leaks is severe over time. In particular, it was found that the retention time of the memory element used repeatedly 1000 times is very short.

On the other hand, memory devices using GaN nanocrystals and AlGaN nanocrystals as the charge trapping layer have a small amount of charge leakage over time, and the retention time of the memory device used 1000 times is also very good. .

This is because when the GaN-based nanocrystals are used as charge trap layers, electrons are trapped at a deep energy level due to a lower conduction band than the Si substrate, thereby minimizing current leakage to the tunnel insulating layer and the blocking insulating layer.

Therefore, when the first trap layer 131 and the second trap layer 132 are formed of GaN nanocrystals and AlGaN nanocrystals, the first trap layer 131 is formed of high density with AlGaN nanocrystals as a seed layer. It is preferable to form the second trap layer 132 with GaN nanocrystals.

In the above embodiment, a charge trap layer having two trap layers has been described, but is not necessarily limited thereto. That is, a second trap layer may be formed on the first trap layer, and a third trap layer made of GaN nanocrystals or InGaN nanocrystals may be formed on the second trap layer.

The nonvolatile memory device having the charge trap layer made of the nanocrystal of the present invention as described above has the advantage that the retention time of the memory is long even if a small defect occurs in the charge trap layer. In addition, the charge trap layer of the present invention includes a first trap layer in a seed state and a second trap layer on the first trap layer, and the first trap layer is densely formed on the tunnel insulating layer to form a nanocrystal having a dense structure. The charge trap layer can be implemented.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

Claims (15)

In a nonvolatile memory device in which a tunnel insulating film, a charge trap layer, a blocking insulating film, and a gate electrode are sequentially stacked on a semiconductor substrate, The charge trap layer includes a first trap layer made of nanocrystals, and a second trap layer made of nanocrystals having a larger diameter than the first trap layer and formed on the first trap layer. The first trap layer and the second trap layer are GaN, Al _x Ga _{1 - x} N, In _y Ga _{1 - y} N, Al _x In _y Ga _{1 -x- y} N (0 <x, y, x + A nonvolatile memory device comprising a material selected from y≤1). The method of claim 1, The first trap layer is a non-volatile memory device, characterized in that made of nano-crystal of 0.5 ~ 3 nm diameter. The method of claim 1, And the first trap layer is made of Al _x Ga _{1 - x} N nanocrystals ((0 <x≤1)). The method of claim 1, The second trap layer is a nonvolatile memory device, characterized in that consisting of nanocrystals of 3 ~ 20 nm diameter. The method of claim 1, The second trap layer has a smaller band gap than the first trap layer. The method of claim 5, wherein And the second trap layer is made of the GaN nanocrystal or the In _y Ga _{1 - y} N nanocrystal ((0 <y≤1)). The method of claim 1, And the blocking insulating layer is a hafnium oxide (HfO ₂ ) layer. The method of claim 1, And a source region and a drain region are further formed in the semiconductor substrate outside the tunnel insulation layer. A tunnel insulating film, a charge trap layer, a blocking insulating film, and a gate electrode are sequentially stacked on the semiconductor substrate, and the charge trap layer is formed on the first trap layer made of nanocrystals and the first trap layer. A second trap layer made of nanocrystals having a larger diameter than the first trap layer; The first trap layer and the second trap layer are GaN, Al _x Ga _{1 - x} N, In _y Ga _{1 - y} N, Al _x In _y Ga _{1 -x- y} N (0 <x, y, x + In the method of manufacturing a nonvolatile memory device made of a material selected from y≤1), The first trap layer and the second trap layer is a method of manufacturing a non-volatile memory device, characterized in that each deposited sequentially at 300 ~ 900 ℃. The method of claim 9, The first trap layer is a method of manufacturing a non-volatile memory device, characterized in that consisting of nano-crystal of 0.5 ~ 3 nm diameter. The method of claim 9, The first trap layer is a method of manufacturing a non-volatile memory device, characterized in that the Al _x Ga _{1 - x} N nano-crystal ((0 <x _{≤ 1} ). The method of claim 9, The second trap layer is a method of manufacturing a nonvolatile memory device, characterized in that consisting of nanocrystals of 3 ~ 20 nm diameter. The method of claim 9, The second trap layer has a smaller band gap than the first trap layer. The method of claim 13, The second trap layer is a method of manufacturing a non-volatile memory device, characterized in that consisting of the GaN nano crystal or the In _y Ga _{1 - y} N nano crystal ((0 <y ≤ 1). The method of claim 9, The first trap layer and the second trap layer is a nitrogen element is supplied 10 to 10,000 times more than the group III element, characterized in that the deposited by any one method of MOCVD, MBE, CBE, MOMBE, sputtering method Method of manufacturing volatile memory device.

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