CN103872059B - P-type channel flush memory device and manufacture method thereof - Google Patents
P-type channel flush memory device and manufacture method thereof Download PDFInfo
- Publication number
- CN103872059B CN103872059B CN201410110060.9A CN201410110060A CN103872059B CN 103872059 B CN103872059 B CN 103872059B CN 201410110060 A CN201410110060 A CN 201410110060A CN 103872059 B CN103872059 B CN 103872059B
- Authority
- CN
- China
- Prior art keywords
- memory device
- type channel
- perform step
- oxide layer
- flush memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
A kind of manufacture method of P-type channel flush memory device, including: step S1: form N trap by ion implantation technology, and deposit tunneling oxide layer, the first multi-crystal silicon floating bar structure and silicon nitride layer；Step S2: form shallow trench by dry etch process and isolate；Step S3: shallow trench isolation is carried out silica dioxide medium layer filling by high-aspect-ratio technique；Step S4: remove silica dioxide medium layer by wet etching part, and deposit ONO dielectric oxide layer；Step S5: deposit the second polysilicon control grid structure；Step S6: form control gate and floating boom by dry etch process etching；Step S7: the doping of various dose p-type is injected in source area and described drain region.The present invention uses autoregistration shallow ditch groove separation process on the basis of P-type channel memory device, not only increases device memory density, and by using higher floating boom, strengthens the voltage coupling effect of device, and then realizes the effects such as reading speed is fast, low in energy consumption.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of P-type channel flush memory device and manufacture method thereof.
Background technology
The application of nonvolatile storage (Non-volatile Memory, NVM) is quite varied in the semiconductor device, its
Feature is the data that the most still can preserve storage.Nonvolatile storage the earliest is Erarable Programmable Read only Memory
(Erasable Programmable Read Only Memory, EPROM), its programming uses thermoelectron to inject, and erasing uses
UV ultraviolet light.But, described Erarable Programmable Read only Memory need to carry out UV ultraviolet light erasing with quartz glass, and cost is high
High.
In order to reduce manufacturing cost, FN tunneling effect is now utilized to carry out the EEPROM of electricity erasing
(Electrically Erasable Programmable Read Only Memory, EEPROM), when electronics injects and stores
Interval scale information " 0 " in floating boom；When electronics is wiped free of interval scale information " 1 " from floating boom.It is apparent that described electric erasable and programmable
Journey read only memory is low compared with erasable programmable memory cost, but the programming of described EEPROM and
Erasing needs byte-by-byte (Byte) to carry out, and speed is too low.
In order to improve device reading speed, the device architecture of described EEPROM carries out electricity
Road design improves, and develops existing conventional flash memory (Flash EEPROM) so that multiple memory element (Cell)
Can be programmed simultaneously and wipe.
Described existing flash memory is the same with EEPROM, and programming all uses thermoelectron injection mode (Channel Hot
Electron Injection, CHEI).In order to produce thermoelectron, usually require that and apply high electricity at described grid and described drain electrode
Pressure.Due to the physical characteristic of thermoelectron injection itself, its power consumption is big, and Carrier Injection Efficiency is low, with the low-power consumption in current market
Demand seriously run counter to, so defect is highlighted further.On the other hand, in order to improve Carrier Injection Efficiency, this area skill
Art personnel propose source thermoelectron method for implanting (the Source-side Channel Hot utilizing grid dividing structure
Electron, SSCHE), and utilize the 2T flash cell that FN tunnelling is programmed.But, described Technology all uses N-type ditch
The flush memory device in road.
P-type channel flash memory is proposed by Hsu., et al etc. the earliest, described P-type channel flash memory and described biography
The N-type channel flash memory of system is different, and described traditional N-type channel flash memory operation is interval at current saturation, and
Described P-type channel flash memory is to be operated in reverse-biased district, therefore power consumption greatly declines.The most described P-type channel flash memory
Utilizing electron tunneling effect, reading speed is fast, has the most important market application foreground now.
It is apparent that as skilled addressee readily understands that ground, in order to make technological knowledge popular and meet the market demand, institute
State P-channel flash memory and improving memory density, improve the voltage coupling efficiency (Couple Ratio) of device, and accelerate
The aspects such as device reading speed need to improve further.
Therefore the problem existed for prior art, this case designer, by being engaged in the industry experience for many years, actively studies
Improvement, has then had one P-type channel flush memory device of the present invention and manufacture method thereof.
Summary of the invention
The present invention be directed in prior art, traditional P-channel flash memory improve memory density, improve device it
Voltage coupling efficiency (Couple Ratio), and the aspect such as faster devices reading speed need the defects such as further raising and carries
For a kind of P-type channel flush memory device.
The present invention is also an object that traditional P-channel flash memory is improving memory density in prior art,
Improve the voltage coupling efficiency (Couple Ratio) of device, and the aspect such as faster devices reading speed need to carry further
High defect provides the manufacture method of a kind of P-type channel flush memory device.
In order to solve the problems referred to above, the present invention provides a kind of P-type channel flush memory device, described P-type channel flush memory device bag
Including: N trap, described N trap is arranged on the P-type silicon sheet that crystal orientation is<110>；Floating boom, described floating boom and described N trap are by described tunnel
Oxide layer spacer is arranged；P-type doping source region and p-type doped drain region, described p-type doping source region and p-type doped drain region
It is separately positioned on the both sides of described floating boom；Control gate, described control gate is disposed on by described ONO dielectric oxide layer
On described floating boom.
Alternatively, the thickness range of described tunneling oxide layer is 6～12nm, and the thickness of described floating boom is 60～120nm, institute
The thickness stating control gate is 150～250nm, the thickness of the ONO dielectric oxide layer between described floating boom and described control gate
It is 10～20nm.
Alternatively, described source area injects BF2, B is injected in described drain region.
For realizing the another purpose of the present invention, the present invention provides the manufacture method of a kind of P-type channel flush memory device, described side
Method includes:
Perform step S1: form described N trap by ion implantation technology, and it is described to be sequentially depositing formation on described N trap
Tunneling oxide layer, the first multi-crystal silicon floating bar structure and silicon nitride layer；
Perform step S2: form described shallow trench by dry etch process and isolate；
Perform step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP) to described
Shallow trench isolation carries out silica dioxide medium layer filling；
Perform step S4: remove described silica dioxide medium layer by wet etching part, and deposit described ONO
(Oxide-Nitride-Oxide) dielectric oxide layer；
Perform step S5: at the described N trap that differs from of described first multi-crystal silicon floating bar structure and described ONO dielectric oxide layer
Second polysilicon control grid structure described in one outgrowth；
Perform step S6: by dry etch process, described second polysilicon control grid structure is performed etching described in formation
Control gate, performs etching the described floating boom of formation to described first multi-crystal silicon floating bar structure；
Perform step S7: be injected separately into the p-type doping of various dose at the source area of described floating boom and described drain region, with
Complete the manufacture of described P-type channel flush memory device.
Alternatively, described N trap uses phosphonium ion to inject, and three roads inject altogether.
Alternatively, described tunneling oxide layer and described ONO(Oxide-Nitride-Oxide) dielectric oxide layer all uses former
Position steam method of formation (In-Situ Steam Generation, ISSG) technique.
Alternatively, the partial etching amount of described silica dioxide medium layer is not to make voltage coupling efficiency not because etching is very few
Enough, it is not limited because of the etched isolation effects reducing device more.
Alternatively, described source area injects BF2, described drain region is injected B, is annealed after ion implanting, real
Existing ion intensifies, to complete the manufacture of described P-type channel flush memory device.
In sum, the manufacture method of P-type channel flush memory device of the present invention is at the base of described P-type channel memory device
Use autoregistration shallow ditch groove separation process on plinth, not only increase device memory density so that it is memory cell area is about 2F2, and
And by using higher floating boom (60～120nm), enhance the voltage coupling effect of device greatly, and then realize voltage coupling
Close that efficiency is high, reading speed is fast, low in energy consumption, and the effect such as memory density is big.
Accompanying drawing explanation
Fig. 1 show the flow chart of the manufacture method of P-type channel flush memory device of the present invention；
Fig. 2 show the electron scanning collection of illustrative plates of P-type channel flush memory device of the present invention；
Fig. 3 (a)～3(g) it show the stage structural representation of the manufacture of P-type channel flush memory device of the present invention.
Detailed description of the invention
By describing the technology contents of the invention, structural feature in detail, being reached purpose and effect, below in conjunction with reality
Execute example and coordinate accompanying drawing to be described in detail.
Refer to the flow chart that Fig. 1, Fig. 1 show the manufacture method of P-type channel flush memory device of the present invention.Described p-type ditch
The manufacture method of road flush memory device comprises the following steps,
Perform step S1: form described N trap by ion implantation technology, and it is described to be sequentially depositing formation on described N trap
Tunneling oxide layer, the first multi-crystal silicon floating bar structure and silicon nitride layer；
Perform step S2: form described shallow trench by dry etch process and isolate；
Perform step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP) to described
Shallow trench isolation carries out silica dioxide medium layer filling；
Perform step S4: remove described silica dioxide medium layer by wet etching part, and deposit described ONO
(Oxide-Nitride-Oxide) dielectric oxide layer；
Perform step S5: at the described N trap that differs from of described first multi-crystal silicon floating bar structure and described ONO dielectric oxide layer
Second polysilicon control grid structure described in one outgrowth；
Perform step S6: by dry etch process, described second polysilicon control grid structure is performed etching described in formation
Control gate, performs etching the described floating boom of formation to described first multi-crystal silicon floating bar structure；
Perform step S7: be injected separately into the p-type doping of various dose at the source area of described floating boom and described drain region, with
Complete the manufacture of described P-type channel flush memory device.
For disclosing the technical scheme of the present invention more intuitively, highlight the beneficial effect of the present invention, in conjunction with concrete enforcement
Mode is illustrated, and involved in a specific embodiment concrete material composition, thickness range are only enumerated, can Poria equal
The material of effect also belongs to the scope that the present invention advocates, is not construed as the restriction to the technical program.
Refer to Fig. 2, Fig. 3 (a)～3(g), Fig. 2 show the electron scanning collection of illustrative plates of P-type channel flush memory device of the present invention.
Fig. 3 (a)～3(g) it show the stage structural representation of the manufacture of P-type channel flush memory device of the present invention.Described P-type channel dodges
Memory device 1 includes: N trap 11；Floating boom 121, described floating boom 121 and described N trap 11 are arranged by described tunneling oxide layer 13 interval；
P-type doping source region 122 and p-type doped drain region 123, described p-type doping source region 122 and p-type doped drain region 123 are respectively
It is arranged on the both sides of described floating boom 121；Control gate 141, between described control gate 141 is by described ONO dielectric oxide layer 15
Every being arranged on described floating boom 121.
The manufacture method of P-type channel flush memory device 1 of the present invention, comprises the following steps:
Perform step S1: form described N trap 11 by ion implantation technology, and be sequentially depositing formation on described N trap 11
Described tunneling oxide layer the 13, first multi-crystal silicon floating bar structure 12 and silicon nitride layer 16；
Without limitation, using P type substrate in the present invention, crystal orientation is that the silicon chip of<110>carries out subsequent process flow.?
In described step S1, described N trap 11 uses phosphonium ion to inject, altogether three roads inject, in order to carry out device threshold voltage regulation and
Device isolation, prevents electric leakage；As specifically embodiment, the thickness of described tunneling oxide layer 13 is 6～12nm；Described first
The thickness of multi-crystal silicon floating bar structure 12 is 60～120nm.Described tunneling oxide layer 13 uses situ steam method of formation (In-Situ
Steam Generation, ISSG) technique, in order to improve film quality, improves the reliability of flush memory device.
Perform step S2: form described shallow trench isolation 17 by dry etch process；
More specifically, while etching forms described shallow trench isolation 17, etching described active area 10, tunnel further
Oxide layer the 13, first multi-crystal silicon floating bar structure 12 and silicon nitride layer 16, and guarantee the described pattern after etching and described shallow trench
The degree of depth of isolation 17.
Perform step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP) to described
Shallow trench isolation 17 carries out silica dioxide medium layer 18 and fills；
Perform step S4: remove described silica dioxide medium layer 18 by wet etching part, and deposit described ONO
(Oxide-Nitride-Oxide) dielectric oxide layer 15；
It is highly preferred that the partial etching amount of described silica dioxide medium layer 18 is optimized, not make because etching is very few
Obtain voltage coupling efficiency inadequate, be not advisable because of the etched isolation effects reducing devices more.Described ONO dielectric oxide layer 15 uses
Situ steam method of formation (In-Situ Steam Generation, ISSG) technique, in order to improve film quality, improves flash memories
The reliability of part.
Perform step S5: differ from described N in described first multi-crystal silicon floating bar structure 12 and described ONO dielectric oxide layer 15
Second polysilicon control grid structure 14 described in one outgrowth of trap 11；
Wherein, between described second polysilicon control grid structure 14 and described first multi-crystal silicon floating bar structure 12
The thickness of ONO dielectric oxide layer 15 is 10～20nm.
Perform step S6: by dry etch process, described second polysilicon control grid structure 14 performed etching formation institute
State control gate 141, described first multi-crystal silicon floating bar structure 12 is performed etching the described floating boom 121 of formation；
More specifically, the thickness of described floating boom 121 is 60～120nm；The thickness of described control gate 141 be 150～
250nm；The thickness of the ONO dielectric oxide layer 15 between described floating boom 121 and described control gate 141 is 10～20nm.
Perform step S7: be injected separately into the P of various dose at the source area 122 of described floating boom 121 and described drain region 123
Type adulterates, to complete the manufacture of described P-type channel flush memory device 1.
More specifically, inject BF at described source area 1222, B is injected in described drain region, complete laggard in ion implanting
Row annealing, it is achieved ion intensifies, to complete the manufacture of described P-type channel flush memory device 1.
As those skilled in the art, it is readily appreciated that ground, the manufacture method of P-type channel flush memory device of the present invention is in institute
Use autoregistration shallow ditch groove separation process on the basis of stating P-type channel memory device, not only increase device memory density so that it is deposit
Storage unit area is about 2F2, and by using higher floating boom (60～120nm), enhance the voltage coupling of device greatly
Close effect, and then realize that voltage coupling efficiency is high, reading speed is fast, low in energy consumption, and the effect such as memory density is big.
In sum, the manufacture method of P-type channel flush memory device of the present invention is at the base of described P-type channel memory device
Use autoregistration shallow ditch groove separation process on plinth, not only increase device memory density so that it is memory cell area is about 2F2, and
And by using higher floating boom (60～120nm), enhance the voltage coupling effect of device greatly, and then realize voltage coupling
Close that efficiency is high, reading speed is fast, low in energy consumption, and the effect such as memory density is big.
Those skilled in the art it will be appreciated that the most without departing from the spirit or scope of the present invention, can be to this
Bright carry out various modifications and variations.Thus, if any amendment or modification fall into the protection of appended claims and equivalent
In the range of time, it is believed that the present invention contain these amendment and modification.
Claims (4)
1. the manufacture method of a P-type channel flush memory device, it is characterised in that described method includes:
Perform step S1: by ion implantation technology formed N trap, and be sequentially depositing on N trap formation tunneling oxide layer, more than first
Crystal silicon FGS floating gate structure and silicon nitride layer；
Perform step S2: form shallow trench by dry etch process and isolate；
Perform step S3: by high-aspect-ratio technique (High Aspect Ratio Process, HARP) shallow trench isolated into
Row silica dioxide medium layer is filled；
Perform step S4: remove silica dioxide medium layer by wet etching part, and deposit ONO (Oxide-Nitride-
Oxide) dielectric oxide layer；
Perform step S5: in described first multi-crystal silicon floating bar structure and the side differing from described N trap of described ONO dielectric oxide layer
Deposit the second polysilicon control grid structure；
Perform step S6: by dry etch process, described second polysilicon control grid structure is performed etching formation control gate
Pole, performs etching formation floating boom to described first multi-crystal silicon floating bar structure；
Perform step S7: be injected separately into the p-type doping of various dose at the source area of described floating boom and drain region, to complete p-type
The manufacture of raceway groove flush memory device.
2. the manufacture method of P-type channel flush memory device as claimed in claim 1, it is characterised in that described N trap uses phosphonium ion
Injecting, three roads inject altogether.
3. the manufacture method of P-type channel flush memory device as claimed in claim 1, it is characterised in that described tunneling oxide layer and
Described ONO (Oxide-Nitride-Oxide) dielectric oxide layer all uses situ steam method of formation (In-Situ Steam
Generation, ISSG) technique.
4. the manufacture method of P-type channel flush memory device as claimed in claim 1, it is characterised in that described source area injects BF2,
B is injected in described drain region, anneals, it is achieved ion intensifies, to complete described P-type channel flash memories after ion implanting
The manufacture of part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410110060.9A CN103872059B (en) | 2014-03-24 | 2014-03-24 | P-type channel flush memory device and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410110060.9A CN103872059B (en) | 2014-03-24 | 2014-03-24 | P-type channel flush memory device and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103872059A CN103872059A (en) | 2014-06-18 |
| CN103872059B true CN103872059B (en) | 2016-08-31 |
Family
ID=50910431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410110060.9A Active CN103872059B (en) | 2014-03-24 | 2014-03-24 | P-type channel flush memory device and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103872059B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733433B (en) * | 2015-03-24 | 2019-06-25 | 上海新储集成电路有限公司 | A kind of structure and method for realizing local interlinkage |
| CN109904069A (en) * | 2019-03-20 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The forming method of ono dielectric layer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101331597A (en) * | 2005-12-13 | 2008-12-24 | 应用材料股份有限公司 | Memory cell having stressed layers |
| CN102176468A (en) * | 2011-01-28 | 2011-09-07 | 上海宏力半导体制造有限公司 | P-type MOS (Metal Oxide Semiconductor) memory cell |
| CN102738244A (en) * | 2011-04-08 | 2012-10-17 | 北京大学 | SONOS flash memory, preparation method thereof, and operation method thereof |
| CN103137626A (en) * | 2011-11-29 | 2013-06-05 | 中国科学院微电子研究所 | Plane floating gate flash memory device and preparation method thereof |
-
2014
- 2014-03-24 CN CN201410110060.9A patent/CN103872059B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101331597A (en) * | 2005-12-13 | 2008-12-24 | 应用材料股份有限公司 | Memory cell having stressed layers |
| CN102176468A (en) * | 2011-01-28 | 2011-09-07 | 上海宏力半导体制造有限公司 | P-type MOS (Metal Oxide Semiconductor) memory cell |
| CN102738244A (en) * | 2011-04-08 | 2012-10-17 | 北京大学 | SONOS flash memory, preparation method thereof, and operation method thereof |
| CN103137626A (en) * | 2011-11-29 | 2013-06-05 | 中国科学院微电子研究所 | Plane floating gate flash memory device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103872059A (en) | 2014-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10192999B2 (en) | Vertical memory cell with non-self-aligned floating drain-source implant | |
| US8669607B1 (en) | Methods and apparatus for non-volatile memory cells with increased programming efficiency | |
| TWI451562B (en) | Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure | |
| CN104882447B (en) | A kind of half floating-gate device and manufacturing method of drain region insertion inversion layer | |
| JP2007511076A (en) | Technology for programming flash memory using gate junction leakage current | |
| CN105720060A (en) | Memory cell having a vertical selection gate formed in an fdsoi substrate | |
| CN103887313A (en) | Semi-floating gate device and manufacturing method | |
| TWI536504B (en) | Non-volatile memory cell, manufacturing method thereof and non-volatile memory array | |
| TW201637018A (en) | Electrically-Erasable Programmable Read-Only Memory of reducing voltage difference and operation method thereof | |
| JP2004214365A (en) | Nonvolatile semiconductor memory device and its operating method | |
| CN101814322B (en) | Method of operating non-volatile memory cell and memory device utilizing the method | |
| Maconi et al. | Impact of lateral charge migration on the retention performance of planar and 3D SONOS devices | |
| CN103872059B (en) | P-type channel flush memory device and manufacture method thereof | |
| US20060023506A1 (en) | Non-volatile memory device and method for programming/erasing the same | |
| CN102376652B (en) | Method for manufacturing split gate flash by reducing writing interference | |
| KR101552921B1 (en) | Method of manufacturing non volatile memory device | |
| CN102800675B (en) | A kind of charge-captured non-volatilization memory and manufacture method thereof | |
| CN101714560A (en) | Eeprom and method for manufacturing the eeprom | |
| CN102945850A (en) | Image flash memory device and operating method thereof | |
| CN112002694B (en) | SONOS memory and manufacturing method thereof | |
| TWI695489B (en) | Low-voltage fast erasing method of electronic writing erasing type rewritable read-only memory | |
| CN109285840B (en) | 3D-NAND flash memory and working method thereof | |
| CN109300904B (en) | Method for forming 3D-NAND flash memory | |
| Fang et al. | A novel symmetrical split-gate structure for 2-bit per cell flash memory | |
| CN116546820A (en) | Preparation method of SONOS memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |