CN105118831A - Double-bit non-junction flash memory and programming, erasing and reading methods thereof - Google Patents
Double-bit non-junction flash memory and programming, erasing and reading methods thereof Download PDFInfo
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Abstract
The invention discloses a double-bit non-junction flash memory. The double-bit non-junction flash memory is an SONOS flash memory utilizing a non-junction transistor, a substrate of the double-bit non-junction flash memory is provided with a source end, a drain end and a channel region, the source end, the drain end and the channel region are respectively provided with uniformly and heavily doped N-type impurities, the double-bit non-junction flash memory does not use a PN junction, a silicon nitride layer of the double-bit non-junction flash memory comprises two storage bits for storing charges, and a heavily doped region of the double-bit non-junction flash memory has a thickness which enables the SONOS flash memory to be capable of completely running out of electrons in the region when the SONOS flash memory is turned off. Programming of the double-bit non-junction flash memory is performed by means of a band-to-band tunneling hot-hole injection mode, erasing operation is performed by utilizing a channel FN tunneling erasing mechanism, reading is performed through adoption of a reverse reading mode, and the defects of the complex circuit structure, the slow reading, writing and erasing speeds and the high requirement for reliability which exist in a traditional floating gate multiple level cell technology can be corrected.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, relate to a kind of dibit without knot flash memories and programming, erasing and read method.
Background technology
Spacing along with the PN junction of modern cmos device has arrived the sub-50nm stage, and high doping content gradient is very necessary, this considerably increases the difficulty of manufacture technics.When device channel length is less than 50nm, for ultra-shallow junctions technology is very effective for suppression short channel effect, but the degree of depth controlling PN junction is very difficult with its section.Further, due to the sky high cost of thermal annealing, make formed for ultra-shallow junctions for the 3D multiple-level stack device in future technique be a bottleneck.
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-oxide-nitride--oxide-silicon) is a kind of and flash memory contact nonvolatile memory comparatively closely.The main distinction of it and main flow flash memory is, it uses silicon nitride (Si
3n
4) instead of polysilicon serve as storage medium.Its branch is SHINOS (silicon-high dielectric-Nitride Oxide-silicon).SONOS allows the programming-number of erase cycles of the program voltage lower than polysilicon flash memory and Geng Gao, is the research comparatively enlivened, exploitation focus.
SONOS is relative to conventional floating gate transistor flash, have better data retention characteristics, silicon nitride layer is the charge storage elements of localization, utilizes conductor polysilicon store electrons different from conventional floating gate transistor, when oxide layer has a small amount of defect, the unexpected loss of total data can not be caused.
Traditional multidigit memory technology brief introduction: Memory Storage Unit relies on the electron number difference of storing in floating boom to distinguish 0 and 1, and have higher reliability, when the erase cycle up to 1e5, the threshold voltage difference of Memory Storage Unit still can reach 4V.This feature makes employing multiplelevelcell (multidigit storage) technology become possibility.So-called multiplelevelcell technology, it is exactly the difference according to institute's store electrons quantity in Memory Storage Unit floating boom, be divided into four grades, for representing 00,01,10,11 4 store status respectively, realize a cell (unit) and storing two bits.Original singlelevelcell technology, in floating boom, electron number is about 250, and threshold voltage remains at low levels, and represents store status 1; And electron number is when being 4000 to 6000, threshold voltage is higher, represents store status 0.And multiplelevelcell technology, except original two kinds of situations represent except store status 00 and 11 respectively, newly add two medians, namely electron number is 1500 to 2500 represent store status 00, and electron number is 3000 to 3500 represent store status 10.So just achieve and store two bits in a cell, more originally had in integrated level and increased exponentially.
, traditional floating boom multidigit memory technology has its inherent shortcoming:
The first, the charge storage that aspire for stability.Between multiplelevelcell technology one of four states, charge number difference is smaller, so require higher to leakage rate, approximately requires that leakage rate is less than 1 electronics every day;
The second, require accurate data reading circuit.The higher electric charge induction of multiplelevelcell technical requirement, to distinguish 00,01,10,11 one of four states, generally will be realized by very complicated circuit, so reading speed is also slower;
3rd, require accurate electron injection mechanism.The electron number that multiplelevelcell technical requirement injects floating boom is more accurate, and will carry out more complicated checking, guarantees the correctness storing data, so circuit structure is more complicated, write is also slower with the speed of erasing.
First by people such as Jean-PierreColinge, in 2010, the article " Nanowiretransistorswithoutjunctions " be published on Nature proposed nodeless mesh body pipe.Its operation principle is to use Uniform Doped substrate to replace source-drain structure, thus eliminates the structure of the original PN junction of transistor, reduces process complexity and improves the performance of transistor.Do not have in the transistor of PN junction this, the conductivity utilizing the on-off action of grid to control transistor reaches the effect of switch.During shutoff, gate voltage is less than threshold voltage, and intermediate channel part is depleted and turn off.During break-over of device, gate voltage is more than or equal to threshold voltage, and intermediate channel part is formed and can conduct electricity.Traditional nodeless mesh body pipe substrate is Uniform Doped and does not have the structure of the PN junction of source and drain, therefore it can save the technological process and ion diffuse thermal process that form source and drain, and does not need to increase new light shield, thus greatly saves processing step and cost.
Therefore, nodeless mesh body tubular construction how is utilized to design a kind of new SONOS flash memory structure, complicated to solve the circuit structure that conventional floating gate multidigit memory technology exists, read, write, erasing speed be slower, the defect higher to reliability requirement, becomes industry problem waiting to solve.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence, there is provided a kind of dibit without knot flash memories and programming, erasing and read method, the circuit structure complexity that conventional floating gate multidigit memory technology exists can be solved, reading, write, erasing speed are comparatively slow, the defect higher to reliability requirement.
For achieving the above object, technical scheme of the present invention is as follows:
A kind of dibit, without knot flash memories, comprising:
P type substrate, has the source of even heavily doped N-type impurity, drain terminal and channel region in described substrate; And
Be based upon the SONOS flash memory structure on the described substrate between described source, drain terminal, described SONOS flash memory structure comprises substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, the heavily doped polysilicon control grid of P type from bottom to top successively, described silicon nitride layer comprises first, second bank bit for stored charge, and described heavily doped region has the thickness making described SONOS flash memory can exhaust this regional Electronic completely when turning off;
Wherein, when described first bank bit programming, by applying negative grid voltage to described control gate, positive drain terminal voltage is applied to described drain terminal, to described source ground connection, to produce highfield between described control gate and drain terminal, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described drain terminal in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the first bank bit place described in drain terminal side and be stored therein programming; When described second bank bit programming, by applying negative grid voltage to described control gate, positive source voltage terminal is applied to described source, to described drain terminal ground connection, to produce highfield between described control gate and source, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described source in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the second bank bit place described in source side and be stored therein programming.
Preferably, the even heavy doping of described source, drain terminal and channel region has N-type impurity arsenic.
Preferably, the doping content of described arsenic is 1E-19 ~ 1.5E-19/cm
3.
Preferably, the thickness of described even heavily doped region is no more than 20nm.
Preferably, the grid of described control gate are long is no more than 40nm.
Dibit is without the knot programming of flash memories, erasing and a read method, and described dibit comprises without knot flash memories: P type substrate, has the source of even heavily doped N-type impurity, drain terminal and channel region in described substrate; And the SONOS flash memory structure on the described substrate being based upon between described source, drain terminal, described SONOS flash memory structure comprises substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, the heavily doped polysilicon control grid of P type from bottom to top successively, described silicon nitride layer comprises first, second bank bit for stored charge, and described heavily doped region has the thickness making described SONOS flash memory can exhaust this regional Electronic completely when turning off;
This programmed method comprises: utilize band-to-band-tunneling hot hole injection mode to carry out, when described first bank bit programming, negative grid voltage is applied to described control gate, positive drain terminal voltage is applied to described drain terminal, to described source ground connection, to produce highfield between described control gate and drain terminal, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described drain terminal in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the first bank bit place described in drain terminal side and be stored therein programming; When described second bank bit programming, negative grid voltage is applied to described control gate, positive source voltage terminal is applied to described source, to described drain terminal ground connection, to produce highfield between described control gate and source, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described source in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the second bank bit place described in source side and be stored therein programming;
This method for deleting comprises: utilize raceway groove FN tunnelling erase mechanism to carry out, positive grid voltage is applied to described control gate, identical negative voltage is applied respectively to described source and drain, to produce highfield between described control gate and source and drain and substrate, form a spatially uniform FN tunneling mechanism, between described control gate and source and drain and substrate highfield effect under, gate oxide described in the duplet in raceway groove has carried out FN tunnelling and first and second bank bit described injecting described silicon nitride layer completes erasing;
This read method comprises: adopt reverse read mode to carry out read operation, when needing the state of reading first bank bit, applying positive source voltage terminal to described source, to described drain terminal ground connection, and described control gate being suspended; When needing the state of reading second bank bit, positive drain terminal voltage being applied to described drain terminal, to described source ground connection, and described control gate being suspended.
Preferably, when described first bank bit programming, described control gate is applied to the grid voltage of-6 ~-4v, described drain terminal is applied to the drain terminal voltage of 4 ~ 6v, to described source ground connection; When described second bank bit programming, described control gate is applied to the grid voltage of-6 ~-4v, described source is applied to the source voltage terminal of 4 ~ 6v, to described drain terminal ground connection.
Preferably, during erasing, described control gate is applied to the grid voltage of 13 ~ 16v, described source and drain is applied respectively to the identical voltage of-4 ~-2v.
Preferably, when needing the state of reading first bank bit, described source being applied to the source voltage terminal of 1.6v, to described drain terminal ground connection, and described control gate being suspended; When needing the state of reading second bank bit, described drain terminal being applied to the drain terminal voltage of 1.6v, to described source ground connection, and described control gate being suspended.
Preferably, the even heavy doping of described source, drain terminal and channel region has N-type impurity arsenic, and the doping content of described arsenic is 1E-19 ~ 1.5E-19/cm
3, Implantation Energy is 2.5 ~ 4kev, and implantation dosage is 1E14 ~ 2E19/cm
2, the thickness of the described even heavily doped region of formation is no more than 20nm, and the grid of described control gate are long is no more than 40nm.
Beneficial effect of the present invention is:
First, in the structure of SONOS flash memory, utilize the transistor arrangement without PN junction, for ultra-shallow junctions technology not using small size MOSFET and small size flash memory to use to reduce short channel effect, can reduce processing step and the cost of sub-below 50nm size SONOS flash memories greatly;
The second, because do not use PN junction, reduce the short channel effect of small size SONOS flash memory, thus can reduce critical size further;
3rd, reduce the coarse mobil-ity degradation problem caused of silicon face of traditional SONOS flash memory;
4th, reduce traditional SONOS flash memory to the needs reducing electrical equivalent oxidated layer thickness;
5th, adopt low-power consumption program/erase method, program/erase power consumption can be reduced;
6th, silicon nitride layer dibit is adopted to store (i.e. first and second bank bit), considerably increase storage density and memory capacity, because the local electronic of silicon nitride layer stores, the programming of the first bank bit and the second bank bit is carried out respectively at drain terminal and source, first and second bank bit is spatially apart from each other, do not affect mutually, therefore, it is possible to accurately read the information of the first bank bit or the second bank bit, thus it is complicated to solve conventional floating gate multidigit memory technology circuit structure, reading, write, erasing speed are comparatively slow, the defect higher to reliability requirement.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of dibit without knot flash memories of a preferred embodiment of the present invention;
Fig. 2 is the principle schematic that a preferred embodiment of the present invention is programmed to the first bank bit;
Fig. 3 is the principle schematic that a preferred embodiment of the present invention is programmed to the second bank bit;
Fig. 4 is that a preferred embodiment of the present invention utilizes raceway groove FN tunnelling erase mechanism to carry out the principle schematic of wiping.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, therefore, should avoid being understood in this, as limitation of the invention.
In following the specific embodiment of the present invention, refer to Fig. 1, Fig. 1 is the structural representation of a kind of dibit without knot flash memories of a preferred embodiment of the present invention.As shown in Figure 1, a kind of dibit of the present invention is without knot flash memories, comprise: P type substrate 1, there is in described substrate 1 source 2 of even heavily doped N-type impurity, drain terminal 5 and raceway groove 6 region, and be based upon the SONOS flash memory structure on the described substrate 1 between described source 2, drain terminal 5.Described SONOS flash memory structure comprises the heavily doped polysilicon control grid 3 of substrate silicon layer, gate oxide, silicon nitride layer 4, oxide layer and P type from bottom to top successively.Silicon nitride layer 4 plays stored charge, comprises first, second bank bit 4-1,4-2 for stored charge, and described first bank bit 4-1 is near drain terminal 5 side, and described second bank bit 4-2 is near source 2 side.First and second bank bit 4-1,4-2 are spatially apart from each other, do not affect mutually.
Please continue to refer to Fig. 1.The present invention uses for reference the people such as Jean-PierreColinge and was published in the concept without junction nanowire transistor that the article " Nanowiretransistorswithoutjunctions " on Nature proposes in 2010, be transplanted on SONOS flash memory device structure, propose a kind of new SONOS flash memory structure utilizing nodeless mesh body tubular construction.Dibit of the present invention is without the key of knot flash memories structure, and the described heavily doped region formed in source 2, drain terminal 5 and raceway groove 6 region is sufficiently thin, with the electronics making described SONOS flash memory can exhaust this N-type heavily doped region completely when turning off.As one preferred embodiment, the thickness H of described even heavily doped region should be no more than 20nm.The grid length of described control gate 3 can be no more than 40nm.
The reason of N-type heavily doped region is used to be SONOS flash memory must be made when ON state to have enough electric currents to pass through, and source and drain has enough little contact resistance.It should be noted that the present invention does not use nano thread structure in order to reduce process complexity.In order to obtain desirable threshold voltage, N-type raceway groove SONOS flash memory must carry out the P type heavy doping of grid, and P type raceway groove SONOS flash memory must carry out the N-type heavy doping of grid.Like this, utilize the work function difference between polysilicon gate and silicon, SONOS flash memory when grid voltage can be enable to be zero is depleted to be turned off.
Above-mentioned this novel SONOS flash memory structure of the present invention does not use PN junction, and all sources, drain terminal and raceway groove are all the regions of Uniform Doped N-type impurity, are formed in P type substrate.As one preferred embodiment, the implanted dopant of raceway groove and source and drain N-type heavily doped region can be arsenic (Arsenic), and its doping content can be 1E-19 ~ 1.5E-19/cm
3, such as, can be 1E-19/cm
3uniform Doped; Implantation Energy can be 2.5 ~ 4kev, and can be such as 3KeV, implantation dosage can be 1E14 ~ 2E19/cm
2, such as, can be 1E14/cm
2.By this injection, the thickness H of N-type heavily doped region can be made to be only and to be no more than 20nm, guarantee when SONOS flash memory turns off depleted.
What propose due to the present invention utilizes the small-sized of the SONOS flash memory of nodeless mesh body tubular construction, usually 50nm is less than, therefore the programming mechanism injected of traditional CHE (ChannelHotElectron, channel hot electron) has been not suitable for very greatly due to power consumption.The low-power consumption program/erase method that the article " PHINES:Anovellowpowerprogram/erase; smallpitch; 2-bitpercellFlashmemory " that we adopt the people such as C.C.Yeh to deliver in 2002 is mentioned, namely uses raceway groove FN erasing (ChannelFowler-NordheimErase) to improve threshold voltage.Programming then relies on BTBHHI (BandtoBandHotHoleInjection, band-to-band-tunneling hot hole injects).
Incorporated by reference to consulting Fig. 1.Specifically, the programmed method that the present invention takes comprises: utilize BTBHHI mode to carry out, when described first bank bit 4-1 programmes, negative grid voltage is applied to described control gate 3, positive drain terminal voltage is applied to described drain terminal 5, to described source 2 ground connection, to produce highfield between described control gate 3 and drain terminal 5, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer 4 is injected by described drain terminal 5 in hole under the effect of described grid voltage, and caught by the trap of the described silicon nitride layer 4 at the first bank bit 4-1 place described in drain terminal side and be stored therein programming, when described second bank bit 4-2 programmes, negative grid voltage is applied to described control gate 3, positive source voltage terminal is applied to described source 2, to described drain terminal 5 ground connection, to produce highfield between described control gate 3 and source 2, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer 4 is injected by described source 2 in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer 4 at the second bank bit 4-2 place described in source side and be stored therein programming.
Refer to Fig. 2, Fig. 2 is the principle schematic that a preferred embodiment of the present invention is programmed to the first bank bit.As shown in Figure 2, as an optional execution mode, in above-mentioned programmed method, when described first bank bit 4-1 programmes, the grid voltage of-6 ~-4v can be applied described control gate, described drain terminal is applied to the drain terminal voltage of 4 ~ 6v, to described source ground connection.In the present embodiment, grid voltage Vg=-5v is adopted, drain terminal voltage Vd=5v, source earthed voltage Vs=0v.Now, under highfield effect between grid and leakage, drain terminal can be with bends, and BTBT hole is tunneling to conduction band (as shown by arrow indication) from valence band, then under the raceway groove electric field action of source Vs=0v, the accelerated formation hot hole in raceway groove depletion region.Under the effect of-5v grid voltage, this hole has enough energy and crosses potential barrier between silicon and gate oxide, and is injected in the first bank bit 4-1 of silicon nitride layer and completes programming.When programming to the first bank bit 4-1, electric hole is caught by the trap of the silicon nitride layer of drain terminal side and is stored therein.
Refer to Fig. 3, Fig. 3 is the principle schematic that a preferred embodiment of the present invention is programmed to the second bank bit.As shown in Figure 3, as an optional execution mode, in above-mentioned programmed method, when described second bank bit 4-2 programmes, the grid voltage of-6 ~-4v can be applied described control gate, described source is applied to the source voltage terminal of 4 ~ 6v, to described drain terminal ground connection.In the present embodiment, grid voltage Vg=-5v is adopted, source voltage terminal Vs=5v, drain terminal earthed voltage Vd=0v.Now, under highfield effect between grid and source, source can be with bends, and BTBT hole is tunneling to conduction band (as shown by arrow indication) from valence band, then under the raceway groove electric field action of drain terminal Vd=0v, the accelerated formation hot hole in raceway groove depletion region.Under the effect of-5v grid voltage, this hole has enough energy and crosses potential barrier between silicon and gate oxide, and is injected in silicon nitride layer second bank bit 4-2 and completes programming.When programming to the second bank bit 4-2, electric hole is caught by the trap of the silicon nitride layer of source side and is stored therein.As can be seen from the electron energy band figure of Fig. 2, Fig. 3 display, under the highfield effect between grid and leakage or between grid and source, when hole is tunneling to conduction band from valence band, downwards, the energy in hole is higher.
Incorporated by reference to consulting Fig. 1.The method for deleting that the present invention takes comprises: utilize raceway groove FN tunnelling erase mechanism to carry out, positive grid voltage is applied to described control gate 3, to described source, drain terminal 2, 5 apply identical negative voltage respectively, with in described control gate 3 and source, drain terminal 2, 5 and substrate 1 between produce highfield, form a spatially uniform FN tunneling mechanism, in described control gate and source, between drain terminal and substrate highfield effect under, gate oxide described in duplet in raceway groove has carried out FN tunnelling and has injected described first of described silicon nitride layer 4, two bank bit 4-1, erasing is completed in 4-2.
Refer to Fig. 4, Fig. 4 is that a preferred embodiment of the present invention utilizes raceway groove FN tunnelling erase mechanism to carry out the principle schematic of wiping.As shown in Figure 4, as an optional execution mode, in above-mentioned method for deleting, during erasing, described control gate is applied to the grid voltage of 13 ~ 16v, described source and drain is applied respectively to the identical voltage of-4 ~-2v.In the present embodiment, control-grid voltage Vg=15v is adopted, drain terminal voltage Vd=-3v, source voltage terminal Vs=-3v.This is a spatially uniform FN tunneling mechanism.Between grid and source and drain and substrate 18v voltage (15v+3v) highfield effect under, can become very bending by band, the duplet gate oxide in raceway groove has carried out FN tunnelling and has fallen in silicon nitride layer 4 completing erasing (as shown by arrow indication).As can be seen from the electron energy band figure of Fig. 4 display, more upwards, then the energy of electronics is higher.
We so define threshold voltage vt h, and as drain terminal voltage Vd=1.6v, for each memory cell (the first or second bank bit), the voltage of control gate during drain terminal electric current I d=1E-7A/ μm is as threshold voltage vt h.At the beginning, FN erasing is carried out to device, Vg=15v, Vd=Vs=-3v.Like this, the first bank bit and the second bank bit are all in high threshold voltage state " 0 ", and total state is " 00 ".If to the first bank bit programming, then its threshold voltage step-down, be state " 1 ", total state is " 10 ".If to the second bank bit programming, then its threshold voltage step-down, be state " 1 ", total state is " 01 ".If successively to the first bank bit and the programming of the second bank bit, then their state is all " 1 ", and total state is " 11 ".
Incorporated by reference to consulting Fig. 1.The read method that the present invention takes comprises: adopt reverse read (reversereadscheme) mode to carry out read operation, be specially, when needing the state of reading first bank bit 4-1, positive source voltage terminal is applied to described source 2, to described drain terminal 5 ground connection, and described control gate 3 is suspended; When needing the state of reading second bank bit 4-2, positive drain terminal voltage being applied to described drain terminal 5, to described source 2 ground connection, and described control gate 3 being suspended.
As an optional execution mode, in above-mentioned read method, when needing the state of reading first bank bit 4-1, applying source voltage terminal Vs=1.6V, drain terminal voltage Vd=0V ground connection, and control-grid voltage Vg=is suspended; When needing the state of reading second bank bit 4-2, applying drain terminal voltage Vd=1.6V, source voltage terminal Vs=0V ground connection, and control-grid voltage Vg=is suspended.If drain terminal electric current I d is more than 1E-7/ μm, then the state of this bank bit is " 1 ", if drain terminal electric current I d is less than 1E-7/ μm, then the state of this bank bit is " 0 ".By the read operation to two bank bits, the information " 00 " of four kinds of different conditions can be responded to, " 01 ", " 10 ", " 11 ".
When making above-mentioned this novel SONOS flash memory structure of the present invention, adopt N-type impurity arsenic (Arsenic) to inject raceway groove and source and drain formation heavily doped region, its doping content can be 1E-19 ~ 1.5E-19/cm
3, Implantation Energy can be 2.5 ~ 4kev, and implantation dosage can be 1E14 ~ 2E19/cm
2.By this injection, all sources, drain terminal and raceway groove all become the region of Uniform Doped N-type impurity.Further, by above-mentioned injection technology, the thickness of N-type heavily doped region can be made to be only and to be no more than 20nm, guarantee when SONOS flash memory turns off depleted.Long being only of the grid of this SONOS flash memory is no more than 40nm.
The dibit SONOS flash memory utilizing nodeless mesh body tubular construction that the present invention proposes, do not increase the light shield number in standard CMOS process, decrease complexity and the cost of technique on the contrary, therefore, it is possible to compatible with existing CMOS technology well, and can in present Semiconductor Manufacturing Company's scale of mass production.
The above-mentioned SONOS flash memory structure utilizing nodeless mesh body tubular construction disclosed by the invention, greatly can reduce processing step and the cost of sub-below 50nm size SONOS flash memory, reduce the short channel effect of small size SONOS flash memory, reduce silicon and the coarse mobil-ity degradation problem caused of oxide interface of traditional SONOS flash memory, reduce traditional SONOS flash memory to the needs reducing electrical equivalent oxidated layer thickness; Low-power consumption program/erase method of the present invention, can reduce program/erase power consumption, adopts the dibit of silicon nitride layer to store, can greatly increase storage density and memory capacity; Simultaneously, the dibit storage of silicon nitride layer has the feature more superior relative to the dibit storage of floating boom, because the local electronic of silicon nitride layer stores, the programming of the first bank bit and the second bank bit is carried out respectively in source and drain terminal, first bank bit and the second bank bit spatially apart from each other, do not affect mutually, thus accurately can read the information of the first bank bit or the second bank bit.Thus.The invention solves conventional floating gate multidigit memory technology circuit structure complicated, reading, write, erasing speed are comparatively slow, the defect higher to reliability requirement.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. dibit is without a knot flash memories, it is characterized in that, comprising:
P type substrate, has the source of even heavily doped N-type impurity, drain terminal and channel region in described substrate; And
Be based upon the SONOS flash memory structure on the described substrate between described source, drain terminal, described SONOS flash memory structure comprises substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, the heavily doped polysilicon control grid of P type from bottom to top successively, described silicon nitride layer comprises first, second bank bit for stored charge, and described heavily doped region has the thickness making described SONOS flash memory can exhaust this regional Electronic completely when turning off;
Wherein, when described first bank bit programming, by applying negative grid voltage to described control gate, positive drain terminal voltage is applied to described drain terminal, to described source ground connection, to produce highfield between described control gate and drain terminal, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described drain terminal in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the first bank bit place described in drain terminal side and be stored therein programming; When described second bank bit programming, by applying negative grid voltage to described control gate, positive source voltage terminal is applied to described source, to described drain terminal ground connection, to produce highfield between described control gate and source, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described source in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the second bank bit place described in source side and be stored therein programming.
2. dibit according to claim 1 is without knot flash memories, and it is characterized in that, the even heavy doping of described source, drain terminal and channel region has N-type impurity arsenic.
3. dibit according to claim 2 is without knot flash memories, and it is characterized in that, the doping content of described arsenic is 1E-19 ~ 1.5E-19/cm
3.
4. dibit according to claim 1 and 2 is without knot flash memories, and it is characterized in that, the thickness of described even heavily doped region is no more than 20nm.
5. dibit according to claim 1 is without knot flash memories, it is characterized in that, the grid of described control gate are long is no more than 40nm.
6. dibit is without the knot programming of flash memories, erasing and a read method, it is characterized in that, described dibit comprises without knot flash memories: P type substrate, has the source of even heavily doped N-type impurity, drain terminal and channel region in described substrate; And the SONOS flash memory structure on the described substrate being based upon between described source, drain terminal, described SONOS flash memory structure comprises substrate silicon layer, gate oxide, silicon nitride layer, oxide layer, the heavily doped polysilicon control grid of P type from bottom to top successively, described silicon nitride layer comprises first, second bank bit for stored charge, and described heavily doped region has the thickness making described SONOS flash memory can exhaust this regional Electronic completely when turning off;
This programmed method comprises: utilize band-to-band-tunneling hot hole injection mode to carry out, when described first bank bit programming, negative grid voltage is applied to described control gate, positive drain terminal voltage is applied to described drain terminal, to described source ground connection, to produce highfield between described control gate and drain terminal, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described drain terminal in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the first bank bit place described in drain terminal side and be stored therein programming; When described second bank bit programming, negative grid voltage is applied to described control gate, positive source voltage terminal is applied to described source, to described drain terminal ground connection, to produce highfield between described control gate and source, cause the band-to-band-tunneling effect of the hot hole of formation, described silicon nitride layer is injected by described source in hole under the effect of described grid voltage, and is caught by the trap of the described silicon nitride layer at the second bank bit place described in source side and be stored therein programming;
This method for deleting comprises: utilize raceway groove FN tunnelling erase mechanism to carry out, positive grid voltage is applied to described control gate, identical negative voltage is applied respectively to described source and drain, to produce highfield between described control gate and source and drain and substrate, form a spatially uniform FN tunneling mechanism, between described control gate and source and drain and substrate highfield effect under, gate oxide described in the duplet in raceway groove has carried out FN tunnelling and first and second bank bit described injecting described silicon nitride layer completes erasing;
This read method comprises: adopt reverse read mode to carry out read operation, when needing the state of reading first bank bit, applying positive source voltage terminal to described source, to described drain terminal ground connection, and described control gate being suspended; When needing the state of reading second bank bit, positive drain terminal voltage being applied to described drain terminal, to described source ground connection, and described control gate being suspended.
7. programming according to claim 6, erasing and read method, is characterized in that, when described first bank bit programming, described control gate applied to the grid voltage of-6 ~-4v, described drain terminal is applied to the drain terminal voltage of 4 ~ 6v, to described source ground connection; When described second bank bit programming, described control gate is applied to the grid voltage of-6 ~-4v, described source is applied to the source voltage terminal of 4 ~ 6v, to described drain terminal ground connection.
8. programming according to claim 6, erasing and read method, is characterized in that, during erasing, described control gate applied to the grid voltage of 13 ~ 16v, described source and drain is applied respectively to the identical voltage of-4 ~-2v.
9. programming according to claim 6, erasing and read method, is characterized in that, when needing the state of reading first bank bit, described source being applied to the source voltage terminal of 1.6v, to described drain terminal ground connection, and described control gate being suspended; When needing the state of reading second bank bit, described drain terminal being applied to the drain terminal voltage of 1.6v, to described source ground connection, and described control gate being suspended.
10. programming according to claim 6, erasing and read method, is characterized in that, the even heavy doping of described source, drain terminal and channel region has N-type impurity arsenic, and the doping content of described arsenic is 1E-19 ~ 1.5E-19/cm
3, Implantation Energy is 2.5 ~ 4kev, and implantation dosage is 1E14 ~ 2E19/cm
2, the thickness of the described even heavily doped region of formation is no more than 20nm, and the grid of described control gate are long is no more than 40nm.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040251490A1 (en) * | 2003-06-16 | 2004-12-16 | Chae Soo-Doo | SONOS memory device and method of erasing data from the same |
| US20080285350A1 (en) * | 2007-05-18 | 2008-11-20 | Chih Chieh Yeh | Circuit and method for a three dimensional non-volatile memory |
| CN101728394A (en) * | 2009-12-01 | 2010-06-09 | 清华大学 | Groove type non-volatilisation memory for multi-digit storage |
| CN102709291A (en) * | 2012-05-22 | 2012-10-03 | 上海宏力半导体制造有限公司 | SONOS storage unit, operation method of SONOS and SONOS storage |
| CN104241334A (en) * | 2014-07-31 | 2014-12-24 | 上海华力微电子有限公司 | Junctionless transistor |
| CN104241396A (en) * | 2014-08-27 | 2014-12-24 | 上海华力微电子有限公司 | N-channel SONOS device and compiling method thereof |
-
2015
- 2015-07-17 CN CN201510422547.5A patent/CN105118831B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040251490A1 (en) * | 2003-06-16 | 2004-12-16 | Chae Soo-Doo | SONOS memory device and method of erasing data from the same |
| US20080285350A1 (en) * | 2007-05-18 | 2008-11-20 | Chih Chieh Yeh | Circuit and method for a three dimensional non-volatile memory |
| CN101728394A (en) * | 2009-12-01 | 2010-06-09 | 清华大学 | Groove type non-volatilisation memory for multi-digit storage |
| CN102709291A (en) * | 2012-05-22 | 2012-10-03 | 上海宏力半导体制造有限公司 | SONOS storage unit, operation method of SONOS and SONOS storage |
| CN104241334A (en) * | 2014-07-31 | 2014-12-24 | 上海华力微电子有限公司 | Junctionless transistor |
| CN104241396A (en) * | 2014-08-27 | 2014-12-24 | 上海华力微电子有限公司 | N-channel SONOS device and compiling method thereof |
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