CN103066131B - Multi-bit nonvolatile memory and method of operation thereof - Google Patents
Multi-bit nonvolatile memory and method of operation thereof Download PDFInfo
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- CN103066131B CN103066131B CN201210590504.4A CN201210590504A CN103066131B CN 103066131 B CN103066131 B CN 103066131B CN 201210590504 A CN201210590504 A CN 201210590504A CN 103066131 B CN103066131 B CN 103066131B
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Abstract
The invention provides a kind of multi-bit nonvolatile memory and method of operation thereof, this memory comprises: Semiconductor substrate; Be formed in the groove in described Semiconductor substrate; Be formed in described Semiconductor substrate, the source region of described groove both sides and drain region; Be formed in the first tunneling medium layer on the lower wall of described groove and diapire, be formed in the regulation and control grid in described first tunneling medium layer; With the grid structure on top being formed in described groove, described grid structure comprises: be formed in the second tunneling medium layer, the electric charge capture layer be formed in described second tunneling medium layer, the block media layer be formed on described electric charge capture layer, the grid be formed on described block media layer on the upper side wall of described groove and described regulation and control grid.According to the nonvolatile memory of the embodiment of the present invention, there is the advantage that programming power consumption is low, program window large, the operating reliability of device is high.
Description
Technical field
The present invention relates to conductor device and technical field of integrated circuits, particularly a kind of multi-bit nonvolatile memory and method of operation thereof and formation method.
Background technology
Utilize silicon nitride as the charge trapping memory of electric charge capture layer, because silicon nitride is dielectric, therefore single in tunnel oxide leakage path can not cause the loss of whole device stored charge, substantially increases the reliability of flush memory device.Thinner silicon nitride accumulation layer is also conducive to reducing further of device size simultaneously.But the nand flash memory device technology of preparing of current Intel has arrived the technology node of 1X ~ 2Xnm.When device physical dimension narrows down to the limit, in order to improve the storage density of array further, adopt a unit to store the method for two or long numeric data, this respect is existing proposes NROM structure and PHINES structure etc.Although multidigit storage means can improve the storage density of array greatly, the reliability of device but declines thereupon, and it is even lower that the fatigue properties of current device drop to 1K by the standard of original 10K time.Meanwhile, due to device dimensions shrink, between adjacent bit, there is larger crosstalk, bring a difficult problem also to the reliability of device.
For PHINES structure, this structure adopts band-to-band-tunneling hot hole to inject (band-to-band hot holeinject ion) and programmes, and adopt F-N tunnelling to carry out erase operation, therefore the programming power consumption of this device is lower.Fig. 1 be the erasing of PHINES device and programming time device in flow of charge schematic diagram and raceway groove can be with schematic diagram.As shown in Figure 1,301 be grid, 302 be source electrode, 303 for drain electrode, 304 is for P type substrate.Wherein, when (a) is erasing bit1 and bit2, in device, flow of charge schematic diagram and raceway groove can be with distribution map; When () is programming bit1 b, in device, flow of charge schematic diagram and raceway groove can be with distribution map; When () is programming bi t2 c, in device, flow of charge schematic diagram and raceway groove can be with distribution map; When () is programming bit1 and bit2 d, in device, flow of charge schematic diagram and raceway groove can be with distribution map.In Fig. 1, three layers in P type substrate are respectively silicon dioxide layer, silicon nitride layer and silicon dioxide layer.This structure is similar to general SONOS device, still adopts silicon nitride layer to carry out electric charge capture.This device is owing to have employed short-channel effect, and when device channel is shorter, reading voltage can reduce further, and reading window also can increase to some extent, so be particularly suitable for small size application.But this size utilizing the reading manner of short channel effect to limit program window on the one hand, also make left and right dibit information produce serious crosstalk when reading on the other hand, therefore the operating reliability of this device is poor.
, there is various weak point in dibit unit (2-bit/cell) structure main at present, as the crosstalk between dibit is large, programming operation window is little, operating reliability is poor.Along with the reduction of device feature size and market are for the demand of high density, mass storage device, develop a kind of non-volatile memory device low in energy consumption, that program window large, device operation reliability is high stores for multidigit and just seem particularly important.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency, particularly provide a kind of multi-bit nonvolatile memory and method of operation thereof, to solve the shortcoming that existing multi-bit memory device power consumption is high, read that the program window that obtains of voltage is young, there is crosstalk, device operation poor reliability between two bits.
For achieving the above object, first aspect present invention provides a kind of multi-bit nonvolatile memory, and this memory comprises: Semiconductor substrate; Be formed in the groove in described Semiconductor substrate; Be formed in described Semiconductor substrate, the source region of described groove both sides and drain region; Be formed in the first tunneling medium layer on the lower wall of described groove and diapire, be formed in the regulation and control grid in described first tunneling medium layer; With the grid structure on top being formed in described groove, described grid structure comprises: be formed in the second tunneling medium layer, the electric charge capture layer be formed in described second tunneling medium layer, the block media layer be formed on described electric charge capture layer, the grid be formed on described block media layer on the upper side wall of described groove and described regulation and control grid.
In one embodiment of the invention, be formed with the well region identical with the doping type of described Semiconductor substrate in described Semiconductor substrate, described groove, described source region and drain region are all formed in described well region.
In one embodiment of the invention, the material of described regulation and control grid is polysilicon.
In one embodiment of the invention, the material of described grid is polysilicon.
In one embodiment of the invention, the shape of described groove is rectangle, trapezoidal, shape of reverse omega or hemisphere.
Second aspect present invention provides a kind of method of operation of multi-bit nonvolatile memory according to a first aspect of the present invention, this method of operation comprises: programming operation, comprise: the first negative voltage is applied to described grid, first positive voltage is applied to one of described source region or drain region, make another floating or the ground connection in described source region or drain region, make described regulation and control grid floating or ground connection; Erase operation, comprising: apply the second positive voltage to described grid, makes described source region and drain region ground connection, makes described regulation and control grid floating or ground connection; And read operation, comprising: tertiary voltage is applied to described grid, the 3rd positive voltage is applied to one of described source region or drain region, makes another ground connection in described source region or drain region, the 4th positive voltage is applied to described regulation and control grid.
In one embodiment of the invention, in described programming operation, erase operation and read operation, described well region ground connection.
In one embodiment of the invention, the scope of described first negative voltage is-4V to-15V, and the scope of described first positive voltage is 2V to 6V.
In one embodiment of the invention, the scope of described second positive voltage is 5V to 20V.
In one embodiment of the invention, the scope of described tertiary voltage be-5V to 5V, the scope of described 3rd positive voltage is 1V to 4V, and the scope of described 4th positive voltage is 1V to 5V.
The invention provides a kind of multi-bit nonvolatile memory and method of operation thereof, according to the nonvolatile memory of the embodiment of the present invention, adopt band-to-band-tunneling hot hole injecting principle to realize programming operation, adopt F-N tunnel to realize erase operation.By arranging regulation and control grid under grid structure, the degeneration of the fatigue properties of device can be reduced in erase operation; The program window read out can be increased in read operation, reduce to read crosstalk, and by regulating the performance of the maximum optimised devices of voltage of regulation and control grid, make the operation of device have flexibility.Compared with traditional similar device, significantly can provide the operating reliability of device according to the nonvolatile memory of the embodiment of the present invention.
The aspect that the present invention adds and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 be PHINES device of the prior art erasing and programming time device in flow of charge schematic diagram and raceway groove can be with schematic diagram;
Fig. 2 is the section of structure of the multi-bit nonvolatile memory of the embodiment of the present invention;
Each bias voltage schematic diagram when Fig. 3 is the drain region information bit programming operation to the multi-bit nonvolatile memory of the embodiment of the present invention;
Fig. 4 is to each bias voltage schematic diagram when the source region of the multi-bit nonvolatile memory of the embodiment of the present invention and drain region information bit erase operation;
Each bias voltage schematic diagram when Fig. 5 is the drain region information bit read operation to the multi-bit nonvolatile memory of the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", orientation or the position relationship of the instruction such as " outward " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
It should be noted that, in addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise one or more these features.
Fig. 2 is the section of structure of the multi-bit nonvolatile memory of the embodiment of the present invention.As shown in Figure 2, this memory 401 comprises: Semiconductor substrate 411; Be formed in the groove 402 in Semiconductor substrate 411; Be formed in Semiconductor substrate 411, the source region 408 of groove 402 both sides and drain region 409; Be formed in the first tunneling medium layer 404 on the lower wall of groove 402 and diapire, be formed in the regulation and control grid 403 in the first tunneling medium layer 404; With the grid structure on top being formed in groove 402.
In the present embodiment, the material of Semiconductor substrate 411 can be silicon, and Semiconductor substrate 411 can be known P type or N type semiconductor substrate, can comprise doping configuration alternatively, such as, adulterated by P type or N-type to form P trap or N trap.For convenience of description, in various embodiments of the present invention, to have the P type semiconductor substrate 411 of P type trap zone 410.Those skilled in the art should understand that; above-mentioned citing only for explaining the present invention, is not limited to protection scope of the present invention, for the multi-bit nonvolatile memory formed on the N type semiconductor substrate with N trap; can carry out with reference to the embodiment of the present invention, not repeat them here.
In the present embodiment, source region 408 and drain region 409 are formed in the P trap 410 of Semiconductor substrate 411, and the charge trapping region of source region 408 and drain region 409 correspondence is information bank bit, therefore this device is the nonvolatile memory that can be used for dibit storage.Wherein, source region 408 and drain region 409 can, by carrying out tilt-angle ion injection to Semiconductor substrate 411 surface, then be annealed to activate adulterated impurity, to form source/drain region.
Groove 402 is formed in the P trap 410 of Semiconductor substrate 411.Groove 402 can be rectangle, trapezoidal, shape of reverse omega, hemisphere or other shape.In the preferred embodiment of the invention, groove 402 is rectangle.
Grid structure comprises: the upper side wall being formed in groove 402 and the second tunneling medium layer 404 (can be dielectric layer that material is identical due to the first tunneling medium layer and the second tunneling medium layer and mutually border on, therefore represent with identical label 404 in fig. 2) on regulation and control grid 403, the electric charge capture layer 405 be formed in the second tunneling medium layer 404, the block media layer 406 be formed on electric charge capture layer 405, the grid 407 be formed on block media layer 406.In the present embodiment, the material of tunneling medium layer 404 can silicon dioxide; The material of electric charge capture layer 405 can be silicon nitride; Block media layer 406 for the migration of block charge between electric charge capture layer 405 and grid 407, the material of block media layer 406 can be silicon dioxide or other there is the insulating dielectric materials of charge barrier ability; Grid 407 is for controlling conducting between source region 408 and drain region 409 and disconnection, and the material of grid 407 can be polysilicon.When being applied to the voltage on polysilicon gate 407 and being less than on state threshold voltage, two P type channel regions not conducting of groove 402 both sides, now this non-volatile memory device is not opened, and does not have electric current to flow through between source region 408 and drain region 409; When being applied to the voltage on polysilicon gate 407 and being greater than on state threshold voltage, two P type channel region transoids of groove 402 both sides, form N-type communication channel, and now this non-volatile memory device is opened.Wherein, described on state threshold voltage can be positive voltage also can be negative voltage, and is subject to the impact of programming operation and erase operation iunjected charge and changes.
In the present embodiment, the material being formed in the regulation and control grid 403 of groove 402 bottom can be polysilicon.The effect of regulation and control grid 403 specifically describes in the method for operation of following device.
Below in conjunction with Fig. 3-5, further mode is applied to the programming operation of the multi-bit nonvolatile memory of the embodiment of the present invention, erase operation and read operation bias voltage and be described.
Each bias voltage schematic diagram when Fig. 3 is the drain region information bit programming operation to the multi-bit nonvolatile memory of the embodiment of the present invention.Programming operation injects (band-to-band hot hole injection) effect based on band-to-band-tunneling hot hole.In the present embodiment, in programming operation, each bias voltage is as follows: drain region 409 applies the first positive voltage, its scope preferably 2V to 6V; Source region 408 floating or ground connection; Grid 407 applies the first negative voltage, and its scope is-4V to-15V preferably; Regulation and control grid 403 floating or ground connection; Well region 410 ground connection.
When drain region 409 applies positive voltage, grid 407 connect higher negative voltage and Substrate ground time, set up a high longitudinal electric field at the crossover area in grid structure and drain region 409, under the pn knot of drain junction and substrate is then biased in high reverse landscape electric field.Under the acting in conjunction of longitudinal electric field and transverse electric field, being with of drain junction limit is bent upwards, and occurs deeply to exhaust.When band curvature amount is greater than the energy gap of silicon, in valence band, electronics can pass through to be with to be tunneling in conduction band and form electron-hole pair, namely there occurs band-to-band-tunneling effect.The electronics that band-to-band-tunneling produces will be collected by drain region 409, and hole major part under pn ties the acceleration of transverse electric field can be crossed interface by substrate and collected, the hole that wherein small part energy is higher can be crossed silicon/silicon dioxide potential barrier and is injected in silicon nitride layer 405 under the attraction of grid structure electric field, namely there occurs band-to-band-tunneling hot hole and injects.Hole is injected in the silicon nitride layer 405 above drain region 409, due to injection can change by band along raceway groove in hole, the part corresponding with hole injection regions can be with and be bent downwardly, and break-over of device threshold voltage reduces, thus achieves the programming operation of drain region information bit.It should be noted that, to the programming operation of source region information bit with similar to the programming operation of drain region information bit, the voltage in source region 408 and drain region 409 is applied relation and exchanges, do not repeat them here.
Fig. 4 is to each bias voltage schematic diagram when the source region of the multi-bit nonvolatile memory of the embodiment of the present invention and drain region information bit erase operation.Erase operation method is based on raceway groove F-N tunneling injection effect.In the present embodiment, in erase operation, each bias voltage is as follows: apply the second positive voltage to grid 407, range preferably from 5V to 20V; Source region 408 and drain region 409 ground connection; Regulation and control grid 403 floating or ground connection; Well region 410 ground connection.In erase process, have in electron injection silicon nitride layer 405, neutralize with hole wherein, cause device threshold voltage to raise, thus achieve the erase operation of source region and drain region information bit.
In erase process, regulation and control grid 403 are in floating or ground state.Owing to regulating and controlling the existence of grid 403, avoid when raceway groove FN injects electronics, be arranged in above regulation and control grid 403, the silicon nitride layer 405 of grid structural base injects electronics.Such one side prevents device after repeatedly wiping, and accumulates unnecessary electronics, affects the threshold voltage of device, the fatigue properties of device are degenerated in the silicon nitride layer 405 of grid structural base; On the other hand, because electronics and hole can be moved gradually in electric charge capture layer 405, and the trap that hole stores in electric charge capture layer 405 is more shallow, more easily produces migration and distribution again phenomenon occurs.And the having to cause and neutralize with the hole in electric charge capture layer 405 of excess electron, thus the degeneration of device programming state retention performance can be aggravated.So, the reliability of device can be improved significantly according to the device architecture of the embodiment of the present invention.
Each bias voltage schematic diagram when Fig. 5 is the drain region information bit read operation to the multi-bit nonvolatile memory of the embodiment of the present invention.Read operation is based on reverse read.In the present embodiment, in read operation, each bias voltage is as follows: apply tertiary voltage to grid 407, ranges preferably from-5V to 5V; 3rd positive voltage is applied to one of source region 408 or drain region 409, ranges preferably from 1V to 4V; Another ground connection in source region 408 or drain region 409; 4th positive voltage is applied to regulation and control grid 403, ranges preferably from 1V to 5V; Well region 410 ground connection.Under the voltage bias condition applied, source region 408 is owing to being applied with a larger positive voltage, therefore the information conductively-closed in source region 408 is fallen.Meanwhile, there are the impact of regulation and control grid 403 malleation in raceway groove central authorities, and raceway groove zone line can be with and be bent downwardly, and effectively can increase the reading window to drain region programmed state.The result now read is the information that drain region 409 stores.It should be noted that, to the read operation of source region information bit with similar to the read operation of drain region information bit, the voltage in source region 408 and drain region 409 is applied relation and exchanges, do not repeat them here.
Reading window by adopting regulation and control grid 403 to increase, device channel intermediate band can be made to be bent downwardly on the one hand, reduce to read crosstalk, increase the program window read out; On the other hand because the voltage of these regulation and control grid can change, therefore by regulating the voltage of regulation and control grid to most suitable operating voltage, can the performance of maximum optimised devices, make the operation of device have flexibility.When repeatedly programming to device and after erase operation, not mating due to injected electrons VOID POSITIONS and cause the read threshold voltages window of device to diminish, at this moment also can increase reading window by the voltage increased on regulation and control grid, improve the reliability of device.In addition, reading window by adopting regulation and control grid 403 to increase, making device have higher Punchthrough voltage.
The invention provides a kind of multi-bit nonvolatile memory and method of operation thereof, according to the nonvolatile memory of the embodiment of the present invention, adopt band-to-band-tunneling hot hole injecting principle to realize programming operation, adopt F-N tunneling injection to realize erase operation.By arranging regulation and control grid under grid structure, the degeneration of the fatigue properties of device can be reduced in erase operation; The program window read out can be increased in read operation, reduce to read crosstalk, and by regulating the performance of the maximum optimised devices of voltage of regulation and control grid, make the operation of device have flexibility.Compared with traditional similar device, significantly can provide the operating reliability of device according to the nonvolatile memory of the embodiment of the present invention.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention, for the ordinary skill in the art, be appreciated that and can carry out multiple change, amendment, replacement and modification to these embodiments without departing from the principles and spirit of the present invention, scope of the present invention is by claims and equivalency thereof.
Claims (10)
1. a multi-bit nonvolatile memory, is characterized in that, comprising:
Semiconductor substrate;
Be formed in the groove in described Semiconductor substrate;
Be formed in described Semiconductor substrate, the source region of described groove both sides and drain region;
Be formed in the first tunneling medium layer on the lower wall of described groove and diapire, be formed in the regulation and control grid in described first tunneling medium layer; With
Be formed in the grid structure on the top of described groove, described grid structure comprises: be formed in the second tunneling medium layer, the electric charge capture layer be formed in described second tunneling medium layer, the block media layer be formed on described electric charge capture layer, the grid be formed on described block media layer on the upper side wall of described groove and described regulation and control grid.
2. multi-bit nonvolatile memory as claimed in claim 1, it is characterized in that, be formed with the well region identical with the doping type of described Semiconductor substrate in described Semiconductor substrate, described groove, described source region and drain region are all formed in described well region.
3. multi-bit nonvolatile memory as claimed in claim 1, it is characterized in that, the material of described regulation and control grid is polysilicon.
4. multi-bit nonvolatile memory as claimed in claim 1, it is characterized in that, the material of described grid is polysilicon.
5. multi-bit nonvolatile memory as claimed in claim 1, is characterized in that, the shape of described groove is rectangle, trapezoidal, shape of reverse omega or hemisphere.
6. a method of operation for the multi-bit nonvolatile memory as described in any one of claim 1-5, is characterized in that, comprising:
Programming operation, comprising: apply the first negative voltage to described grid, applies the first positive voltage, make another floating or the ground connection in described source region or drain region, make described regulation and control grid floating or ground connection one of described source region or drain region;
Erase operation, comprising: apply the second positive voltage to described grid, makes described source region and drain region ground connection, makes described regulation and control grid floating or ground connection; With
Read operation, comprising: apply tertiary voltage to described grid, applies the 3rd positive voltage, make another ground connection in described source region or drain region to one of described source region or drain region, applies the 4th positive voltage to described regulation and control grid.
7. the method for operation of multi-bit nonvolatile memory as claimed in claim 6, it is characterized in that, the well region identical with the doping type of described Semiconductor substrate is formed in described Semiconductor substrate, described groove, described source region and drain region are all formed in described well region, and in described programming operation, erase operation and read operation, described well region ground connection.
8. the method for operation of multi-bit nonvolatile memory as claimed in claim 6, is characterized in that, the scope of described first negative voltage is-4V to-15V, and the scope of described first positive voltage is 2V to 6V.
9. the method for operation of multi-bit nonvolatile memory as claimed in claim 6, it is characterized in that, the scope of described second positive voltage is 5V to 20V.
10. the method for operation of multi-bit nonvolatile memory as claimed in claim 6, is characterized in that, the scope of described tertiary voltage be-5V to 5V, the scope of described 3rd positive voltage is 1V to 4V, and the scope of described 4th positive voltage is 1V to 5V.
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Effective date of registration: 20190705 Address after: 361022 Unit 0206, Unit 109, 62 Chengyi North Street, Xiamen Software Park Phase III, Fujian Province Patentee after: Xiamen Semiconductor Industry Technology Research and Development Co., Ltd. Address before: 100084 Haidian District 100084-82 mailbox in Beijing Patentee before: Tsinghua University |