CN104183273B - Programming method of flash memory device - Google Patents
Programming method of flash memory device Download PDFInfo
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- CN104183273B CN104183273B CN201410427436.9A CN201410427436A CN104183273B CN 104183273 B CN104183273 B CN 104183273B CN 201410427436 A CN201410427436 A CN 201410427436A CN 104183273 B CN104183273 B CN 104183273B
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Abstract
The present invention provides a programming method of a flash memory device, the flash memory device including: the programming method of the flash memory device comprises the following steps that a semiconductor substrate is provided with a source end and a drain end which are arranged at intervals, a control grid and a floating grid are arranged above a gap between the source end and the drain end, and the programming method of the flash memory device comprises the following steps: when programming operation is carried out, voltages are respectively applied to the drain terminal, the floating gate, the control gate and the semiconductor substrate, wherein the applied voltage ranges of the drain terminal and the floating gate are both 2V-3V, the applied voltage range of the control gate is 0.7V-1.0V, and the applied voltage range of the semiconductor substrate is 1V-1.5V. The method provided by the invention can avoid channel punch-through effect caused by applying high voltage to the drain terminal, effectively shorten the key size of the split-gate floating gate flash memory, increase the cell density of a NOR type or NAND type flash memory array which takes the split-gate floating gate flash memory as a cell device, further increase the storage capacity and density of the flash memory and improve the reliability of the device.
Description
Technical Field
The present invention relates to semiconductor integrated circuits and manufacturing thereof, and more particularly, to a programming method of a flash memory device.
Background
Among semiconductor memory devices, a flash memory (flash memory) is a type of non-volatile memory and belongs to an erasable programmable read-only memory (EPROM). Generally, a flash memory has two gates (a floating gate and a control gate), wherein the floating gate is used for storing charges, and the control gate is used for controlling data input and output. The floating gate is positioned under the control gate and is in a floating state since it is not connected to an external circuit. The control gate is typically connected to a word line (word line). The advantage of flash memory is that it can be erased for the entire memory block and the erase speed is fast, about 1 to 2 seconds. Generally, a flash memory is a split gate structure or a stacked gate structure or a combination of the two structures. Due to the special structure of the split-gate flash memory, the split-gate flash memory shows unique performance advantages when being programmed and erased compared with a stacked gate flash memory, and in recent years, the split-gate flash memory is widely applied to various electronic consumer products.
In the fabrication of high-density semiconductor devices on an integrated circuit chip, how to reduce the size and power consumption of each memory cell (memory cell) is considered to increase the operating speed. However, when the existing flash memory has a step towards higher storage density, the storage density can be improved by reducing the size of the device due to the limitation of the programming voltage. When the conventional flash memory moves to higher storage density, it is limited by the structure, and therefore, the further reduction of the programming voltage of the device is very challenging to achieve.
U.S. patent publication No. US 5300803A discloses a non-volatile memory structure with a compilation mechanism ssi (source device injection), which solves the problems of inefficient injection and high power consumption of floating gate flash memory devices. The background art of this patent introduces a conventional floating gate flash memory device, and in order to ensure a high channel hot electron generation rate and a high hot electron injection efficiency, a high voltage is applied to the drain terminal and the gate, electrons flow from the source to the drain and accelerate to generate hot electrons under the action of a high electric field near the drain, and a part of the hot electrons pass through an oxide layer under the floating gate and enter the floating gate, thereby completing a programming operation. However, the conventional floating gate flash memory device has the problems of low channel hot electron injection efficiency and large current power consumption, and in order to solve the problems, the patent proposes a split gate flash memory device in which a left gate is a control gate and a right gate is a floating gate, and the floating gate and the control gate are arranged in a spatially staggered manner, wherein a high voltage is applied to the floating gate, a low voltage is applied to the control gate, and a high voltage is applied to a drain terminal. The control gate voltage is reduced, so that the number of induced inversion charges is small, the electron acceleration distance is shortened, the number of hot electrons is reduced, the programming current is reduced, and the electrons injected into the floating gate are increased, so that the channel hot electron injection efficiency is improved, and the current power consumption is reduced.
However, the technical solution in the above patent has another problem: because the drain terminal applies a higher voltage, the width of a depletion layer extending from the drain terminal to the substrate is larger, and the source terminal and the depletion region are easily contacted together under the condition of high voltage, so that the device is penetrated and failed, namely, a Channel punch-through effect (Channel punch-through effect) is generated, and is a phenomenon that the source terminal is communicated with the depletion region of the drain terminal, and the defect usually limits the upgrading of a technical node and the reduction of a key size of a flash memory device in the process.
Disclosure of Invention
The invention aims to provide a programming method of a flash memory device, which can effectively avoid the defect of channel punch-through, reduce the key size of the flash memory device and improve the reliability of the flash memory device.
In order to solve the above problems, the present invention provides a programming method of a flash memory device, the flash memory device including: the semiconductor device comprises a semiconductor substrate, a control grid and a floating grid, wherein the semiconductor substrate is provided with a source end and a drain end which are arranged at intervals, the control grid and the floating grid are arranged above a gap between the source end and the drain end, and an oxide layer is arranged between the floating grid and the source end and the drain end; the programming method of the flash memory device includes:
when programming operation is carried out, voltages are respectively applied to the drain terminal, the floating gate, the control gate and the semiconductor substrate, wherein the applied voltage ranges of the drain terminal and the floating gate are both 2V-3V, the applied voltage range of the control gate is 0.7V-1.0V, and the applied voltage range of the semiconductor substrate is 1V-1.5V.
Preferably, the voltage applied to the drain terminal is 2V, the voltage applied to the floating gate is 3V, the voltage applied to the control gate is 0.7V, and the voltage applied to the semiconductor substrate is 1.5V.
Preferably, the source terminal applies a voltage of 0V.
Preferably, the control gate applied voltage is equal to a threshold voltage value of the flash memory device.
Preferably, the floating gate applied voltage is greater than a threshold voltage value of the flash memory device.
Preferably, the control gate is partially overlapped with the floating gate and is disposed above the gap between the source terminal and the drain terminal.
Preferably, the control gate and the floating gate are arranged above the gap between the source terminal and the drain terminal with an interval.
Preferably, the thickness of the oxide layer is 2nm to 3.5 nm.
Preferably, the oxide layer is silicon dioxide.
Preferably, the control gate and the floating gate are made of polysilicon.
According to the technical scheme, the programming method of the flash memory device provided by the invention has the advantages that the applied voltage values of the drain terminal, the floating gate and the control gate are adjusted, and the voltage is applied to the semiconductor substrate, so that electrons of a thinner channel electron layer in a substrate area under the control gate are accelerated to generate hot electrons under the action of a high electric field of the semiconductor substrate, and the hot electrons penetrate through an oxide layer under the floating gate to enter the floating gate under the action of high voltage of the floating gate, so that the programming operation is completed. The method provided by the invention can avoid channel punch-through effect caused by applying high voltage to the drain terminal, effectively shorten the key size of the split-gate floating gate flash memory, increase the cell density of a NOR type or NAND type flash memory array which takes the split-gate floating gate flash memory as a cell device, further increase the storage capacity and density of the flash memory and improve the reliability of the device.
Drawings
FIG. 1 is a schematic cross-sectional view of a split-gate flash memory according to the present invention;
fig. 2 is a schematic diagram illustrating a programming method of a flash memory device according to the present invention.
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention. The present invention is described in detail with reference to the drawings, and the drawings are not to be considered as limiting the invention, but are enlarged partially in accordance with the general scale for convenience of explanation.
The above and other features and advantages of the present invention will be described in detail with reference to the embodiments and fig. 1 to 2. FIG. 1 is a schematic cross-sectional view of a split-gate flash memory according to the present invention; fig. 2 is a schematic diagram illustrating a programming method of a flash memory device according to the present invention.
Referring to fig. 1, in the present embodiment, the present invention provides a programming method of a flash memory device, wherein the flash memory device includes: a semiconductor substrate 10 having a source terminal 20 and a drain terminal 30 spaced apart from each other, a control gate 40 and a floating gate 50 being disposed above a gap between the source terminal 20 and the drain terminal 30, and an oxide layer (not shown) being interposed between the floating gate 50 and the source terminal 20 and the drain terminal 30; the control gate 40 is partially overlapped or spaced apart from the floating gate 50 and is disposed over the gap between the source terminal 20 and the drain terminal 30.
The programming method of the flash memory device includes: when programming operation is carried out, voltages are respectively applied to the drain terminal 30, the floating gate 50, the control gate 40 and the semiconductor substrate 10, wherein the voltage applied to the drain terminal 30 and the floating gate 50 ranges from 2V to 3V, the voltage applied to the control gate 40 ranges from 0.7V to 1.0V, and the voltage applied to the semiconductor substrate 10 ranges from 1V to 1.5V. The control gate 40 is applied with a voltage equal to the threshold voltage of the flash memory device, and the floating gate 50 is applied with a voltage much greater than the threshold voltage of the flash memory device.
As shown in fig. 2, the programming principle of the flash memory device is: the voltage of the control gate 40 is equal to the threshold voltage of the flash memory device, a thinner channel electron layer is induced in the lower substrate region, the voltage of the floating gate 50 is higher than the threshold voltage, and a thicker channel electron layer is induced in the lower channel electron layer. By adjusting the applied voltage values of the drain terminal 30, the floating gate 50 and the control gate 40 and applying a voltage to the semiconductor substrate 10, electrons in a thinner channel electron layer in the substrate region under the control gate 40 are accelerated to generate hot electrons under the action of a high electric field of the semiconductor substrate 10, and the hot electrons penetrate through an oxide layer under the floating gate 50 to enter the floating gate 50 under the action of a high voltage of the floating gate 50, so that the programming operation is completed.
Example one
The semiconductor substrate 10 is a P-type substrate, the control gate 40 and the floating gate 50 are made of polysilicon, and the oxide layer is made of silicon dioxide, wherein the control gate 40 is 10nm in length and 90nm in height, the floating gate 50 is 70nm in height and 40nm in length, and the oxide layer is 2nm in thickness; in a programming operation, the threshold voltage Vth of the flash memory device is 0.7V, the voltage applied to the drain terminal 30 is 2V, the voltage applied to the floating gate 50 is 3V, the voltage applied to the control gate 40 is 0.7V, the voltage applied to the semiconductor substrate 10 is 1.5V, and the voltage applied to the source terminal 20 is 0V.
Example two
The semiconductor substrate 10 is a P-type substrate, the control gate 40 and the floating gate 50 are made of polysilicon, and the oxide layer is made of silicon dioxide, wherein the control gate 40 is 10nm in length and 90nm in height, the floating gate 50 is 70nm in height and 40nm in length, and the oxide layer is 3.5nm in thickness; in a programming operation, the threshold voltage Vth of the flash memory device is 0.7V, the voltage applied to the drain terminal 30 is 3V, the voltage applied to the floating gate 50 is 2V, the voltage applied to the control gate 40 is 1V, the voltage applied to the semiconductor substrate 10 is 1V, and the voltage applied to the source terminal 20 is 0V.
The manufacturing method of the flash memory device provided by the invention is the manufacturing method of the existing flash memory device, can be obtained by a conventional method by a person skilled in the art, can be compatible with a standard CMOS (complementary metal oxide semiconductor) process, and is not described herein again.
In summary, the method provided by the invention can avoid channel punch-through effect caused by applying high voltage to the drain terminal, effectively shorten the critical dimension of the split gate floating gate flash memory, increase the cell density of a NOR type or NAND type flash memory array using the split gate floating gate flash memory as a cell device, further increase the storage capacity and density of the flash memory, and improve the reliability of the device.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (8)
1. A programming method of a flash memory device, the flash memory comprising: the semiconductor substrate is provided with a source end and a drain end which are arranged at intervals, a control gate and a floating gate are arranged above a gap between the source end and the drain end, and the control gate and the floating gate are partially overlapped or arranged above the gap between the source end and the drain end at intervals; an oxide layer is arranged between the floating gate and the source end and the drain end; the programming method of the flash memory device is characterized by comprising the following steps:
when programming operation is carried out, voltages are respectively applied to the drain end, the floating gate, the control gate and the semiconductor substrate, wherein the voltage application ranges of the drain end and the floating gate are both 2V-3V, the voltage application range of the control gate is 0.7V-1.0V, the voltage application range of the semiconductor substrate is 1V-1.5V, the thickness of a channel electron layer induced under the floating gate is larger than that of a channel electron layer induced under the control gate in a substrate region, electrons of the channel electron layer in the substrate region under the control gate are accelerated to generate hot electrons under the action of a high electric field of the semiconductor substrate, and the hot electrons penetrate through an oxide layer under the floating gate to enter the floating gate under the action of high voltage of the floating gate, so that the programming operation is completed.
2. The programming method of a flash memory device according to claim 1, wherein the drain terminal is applied with a voltage of 2V, the floating gate is applied with a voltage of 3V, the control gate is applied with a voltage of 0.7V, and the semiconductor substrate is applied with a voltage of 1.5V.
3. The programming method of a flash memory device according to claim 1, wherein the source terminal applies a voltage of 0V.
4. The method of programming a flash memory device according to claim 1, wherein the control gate applied voltage is equal to a threshold voltage value of the flash memory device.
5. The programming method of a flash memory device according to claim 1, wherein the floating gate applied voltage is greater than a threshold voltage value of the flash memory device.
6. The method of programming a flash memory device according to claim 1, wherein the oxide layer has a thickness of 2nm to 3.5 nm.
7. The method of programming a flash memory device of claim 6, wherein the oxide layer is silicon dioxide.
8. The method of programming a flash memory device of claim 1, wherein the control gate and the floating gate are both polysilicon.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW536819B (en) * | 2002-05-17 | 2003-06-11 | Taiwan Semiconductor Mfg | Split-gate flash memory structure and its program method for extending cycling lifetime |
| CN1524297A (en) * | 2001-07-27 | 2004-08-25 | ��ʽ���������Ƽ� | Semiconductor device |
| CN1560870A (en) * | 1997-09-19 | 2005-01-05 | ӡ�����Ƽ��ɷ�����˾ | Flash memory array |
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| US6603679B2 (en) * | 2001-03-05 | 2003-08-05 | Sanyo Electric Co., Ltd. | Coupling coefficient measuring method and coupling coefficient measuring apparatus for semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560870A (en) * | 1997-09-19 | 2005-01-05 | ӡ�����Ƽ��ɷ�����˾ | Flash memory array |
| CN1524297A (en) * | 2001-07-27 | 2004-08-25 | ��ʽ���������Ƽ� | Semiconductor device |
| TW536819B (en) * | 2002-05-17 | 2003-06-11 | Taiwan Semiconductor Mfg | Split-gate flash memory structure and its program method for extending cycling lifetime |
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