TW536819B - Split-gate flash memory structure and its program method for extending cycling lifetime - Google Patents

Abstract

A split-gate flash memory structure and its program method for extending cycling lifetime are provided, wherein the flash memory cell consists of first and second flash memory cells whose floating gates are connected together. The second flash memory cell takes charge of programming function and the first flash memory cell takes charge of data reading function. When programming the second flash memory cell, the bit line of the first flash memory cell provides a positive bias close to the source bias to make the first flash memory cell unable to be programmed by using hot electrons to tunnel the coupling oxide layer to reach the floating gate but able to be programmed through the connected floating gate in programming the second flash memory. Therefore, the first flash memory cell does not encounter the damage due to hot electrons emitting into the coupling oxide. Accordingly, the cycling counts can be obviously increased.

Description

536819 V. Description of the invention (1) Field of the invention: The present invention relates to a split flash memory cell in a semiconductor integrated circuit, and particularly to a split flash memory cell structure capable of improving cycle life and a programming method thereof. . Background of the invention: Fast-moving system, recording (or external, it can be compared with other potentials after being used to protect it. Inactive power points 0 Flash memory system 1, high stability and other information can be eliminated), but unexpectedly Save to quick-stay data. General portable storage system flash memory that can retain storage is just a digital camera and other electronic products with low power consumption and safety data. In terms of bit flash memory, the data is at least black and tarnished. , The new type of "b 1 0cks" method for fast flashing, high access speed, and shock resistance and resistance to access conditions to record groups in order is slow. After that, there is no need for any power supply. Current technology even if the power supply is off for more than a decade. This advantage has made ’therefore competitive with other storage media. Tomorrow's star computer, handheld electronic notebook, and memory requirements are the most typical applications of flash memory for flash memory cards, such as CF (compact memory card) cards, MMC ( mu 11imedia memory card) card, MS (raem〇ry stick card) card or SMC (smart memory

Page 4 536819 V. Description of the Invention (2) card) card. To provide portable electronic consumer products. For example, it is used for flash drives, voice recorders, MP3s, smartphones or digital cameras, and so on. These memory cards are often overwritten to update data. In other words, flash memory cells can not only provide data readout after data is written, but often need to update data. The data storage method of the flash memory cell is based on an example of a flash memory cell. Please refer to the first figure, which includes a control gate 1, a floating gate 2, a source 3, and a pole. 4. An oxide layer 5 and an FN tunneling oxide layer 6. Memory cells are usually formatted before use. This is the data erasing operation. At this time, the control gate 1 is connected to a positive voltage, such as 13 volts, the source 3 is grounded, and the drain 4 is suspended. If the floating gate 2 has electron storage, it will pass through the FN tunneling oxide layer 6 to the control gate. Pole 1. The electrons of floating gate 2 are cleared. To change the state of the memory cell, it must be programmed. When programming, source 3 is connected to a positive voltage, such as 13 volts. The control gate is connected to a small voltage such as 1.8 volts. Drain 4 is grounded or very low voltage. Then the hot electrons will tunnel-couple the oxide layer 5 to the floating gate 2 and change the state of the floating gate. Because these memory cards are often overwritten to update data. In other words, flash memory cells not only provide data reading after data writing, but also often need to update data. Therefore, programming (storing data), erasing (files)

Page 5 536819 V. Description of the invention Remove or grid, especially wipe more frequently, use 100K times, the decline is apparent. Because it is still small. Obviously, extension, formula (3)) and other actions. It is very common for flash memory cells, and the data of some E2 PROM simulators are updated frequently. If one programming and one data erasing is called a cycle (c y c 1 e). The traditional flash memory cell has significant results after the number of cycles of 1 0, 0 0 0 (that is, the next 1 000 times are recorded as 1 K times). For example, if the data in the flash memory cell is logic 0 or 1, it becomes unclear. Even after the data is erased, the current read from the flash memory cell is not much different from before the erasure. If you want to make the state of the flash memory cell a long erasing time is inevitable, you can't even erase it. Before and after this change, the current being read out is almost the same. There are two main mechanisms affecting this. One is the tunneling oxide layer 6 between the floating gate 2 and the control gate 1. After erasing again and again, part of the electrons are tunneled from the floating gate 2 to the control through the tunneling oxide layer 6. The gate electrode 1 is trapped in the tunnel oxide layer 6. The second is between the source 3 and the floating gate 2. During programming, a small number of hot electrons are trapped in the coupling oxide layer 5, and each trapped electron accumulates more electrons. When more electrons are trapped in the consumable oxide layer 5, the transconductance of the channel will be reduced, and the threshold voltage will be increased. The memory cells cannot read the current. Therefore, in order to reduce the premature decay of the coupled oxide layer caused by the above-mentioned programming process, the traditional opening flash memory cell is programmed to shorten the programming time as much as possible. For example, Figure 2 compares traditional open flash memory cells with different lengths of time.

Page 6 536819 V. Description of the invention (4) The program pulse programs the memory cells, and then erases the data. After 30 cycles, the number of memory cells on the vertical axis reads the current read from the memory cells. Comparison chart of change relationship. When the memory cell is programmed with a program pulse of 40 / z S each time, it is shifted from curve 7 to curve 9 at the beginning. When shorter pulses are used, for example, each time they are programmed with a program pulse of 30 // S, the curve 7 is shifted from curve 7 to curve 8. From the result theory, the shorter pulse is used to program the curve 8 with a smaller displacement. In other words, short pulses are preferred. Even so, the effectiveness of the traditional open flash memory cells to extend the service life is still limited. In view of this, the present invention will provide a new flash memory architecture to extend the cycle life. Summary of the Invention: The main purpose of the present invention is to provide a flash memory cell structure that can be opened and closed to improve the cycle life. Another object of the present invention is to provide a method for stylizing the memory cell unit. The invention discloses a flash memory cell unit with extended data erasing and stylized cycle life. The flash memory cell unit includes a first flash memory cell and a second flash memory connected to a floating gate. Memory cells. The second flash memory cell is responsible for the main programming function, and the first flash memory cell is responsible for the main data reading function. When the second flash memory cell is programmed

Page 7 536819 V. Description of the invention (5) During the conversion, the first flash memory cell bit line provides a positive voltage close to the source, so that the first flash memory cell will not use hot electron tunneling coupling. The oxide layer is programmed to the floating gate via the connected floating gate when the second flash memory cell is used for programming. Therefore, according to the memory cell unit of the present invention, the first flash memory cell does not have the problem of (or extremely low) electrons falling into the coupling oxide layer, and reading data is performed by two open flash memory cells simultaneously. And this part of the damage to memory cells. Therefore, the flash memory cell of the present invention can significantly increase the number of cycles. It is usually increased from 1 OO K times to at least 7 OO K times. Detailed explanation: In view of the typical flash memory cell's data access problem after using it for a period of time, the main reason is that the data is from the floating gate to the control gate during data erasure. The middle is deeply trapped in the tunneling oxide layer. Another reason is that during the process of programming, the electrons are trapped in the coupling oxide layer through the coupling oxide layer to the floating gate. Electron trapping in the coupling oxide layer will increase the initial voltage of the channel, resulting in no current reading at the end. Memory cells are states where data has been erased. The latter damages the flash memory cells that are opened more than the former. The flash memory cell unit architecture of the present invention can solve the above problems. Please refer to Figure 3 for a flash memory card that can store one bit of metadata.

Page 8 536819 V. Description of Invention (6) Yuan. Each trip flash memory cell shown in the figure is the same as a conventional trip flash memory cell. The difference is that in the present invention, two flash memory cells 10 and 20 are combined into one memory cell unit. And the floating gates 15 of the two open flash memory cells 10 and 20 are connected. In addition, there is an additional first transistor 40 that is connected to the sensing signal SE by a gate. One source / drain of the first transistor 40 is connected to the drain of the first open flash memory cell 10, and the other source / drain is connected to the sense amplifier. The other transistor is a second transistor 50 whose gate is connected to the stylized signal PROG. One source / drain of the second transistor 50 is connected to the drain of the second flash memory cell 20, and the other source The / drain is connected to the write buffer. Therefore, according to the structure of the open flash memory cell unit of the present invention, the first open flash memory cell 10 is mainly used for data reading (henceforth abbreviated as R memory cell 10). The second opening flash memory cell 20 is mainly used for data writing (henceforth referred to as P memory cell 20). When programming, the source SL applies a larger positive voltage, such as 10 volts, and controls. The gate-connected word line WL applies a smaller voltage, such as 1.8 volts, and the bit line connection of the P memory cell. A voltage of about 0 to 0.5 volts. The bit line of the R memory cell is connected to a voltage of about 2.5 volts to prevent hot electrons from passing through the coupling oxide layer of the R memory cell to the floating gate electrode 15. Instead, the hot electron is subject to the source voltage and the control gate. The voltage attracts the floating gate 15 which first reaches the P memory cell 20, and then the R gate 10 which is in communication with the floating gate 15. When data is removed, R memory cell 10 and P memory cell 20 are performed simultaneously. Therefore, only the coupled oxide layer of P memory cell 20 has the problem of channel hot electron injection but is trapped. The coupling oxide layer of R memory cell 10

536819 V. Description of invention (7) is always clean. Figure 4 shows a layout diagram based on the above concepts. The layout shown is two memory cell units 10-20 and 10 '-2 0' sharing a source. The floating gates 15 of the memory cell units 10-20 are connected in series. In the manufacturing process, as long as the floating gate is defined, the polycrystalline silicon layer does not break. In addition to the above, the burden of stylization completely falls on P memory cell 20. The present invention further provides two stylized methods to reduce the burden of stylization completely on P memory cell 20 and make P memory cell 20 die early. The second programming method of the present invention is to connect the gate of transistor 10 and the gate of transistor 20 to the same PROG signal as shown in FIG. A better way is to make P memory cell 20 bear a larger stylized current and R memory cell bear a smaller stylized current. The stylization that makes P memory cell 20 account for a larger part is that the bit line of R memory cell 10 is connected to a first positive voltage, and the bit line of P memory cell 20 is connected to a second positive voltage. And make the first positive voltage greater than the second positive voltage, and both positive voltages can be programmed to the memory cell, so that a small part of the hot electron tunneling system passes through the coupling oxide layer of the R memory cell 10, most The hot electron tunneling system passes through the coupling oxide layer of the P memory cell 20 to the floating gate 15. In this way, the current carried by the P memory cell is lower than that of the conventional single memory cell, and it will not affect the data reading of the R memory cell. Except this

Page 10 536819 V. In addition to the description of the invention (8), another change of the program memory cell of the present invention is the two-stage programming. In the first stage, the P memory cell is first programmed, but the original programming time is shortened. For example, 100% of the original P memory cells are all stylized. Now, for example, it is changed to 80%-90%. Then, in the second stage, the R memory cell 20 is programmed. In the first stage, R memory cell 10 and P memory cell 2 Q source line SL are connected to a stylized positive voltage. Control gate connection for R memory cell 10 and P memory cell 20-word line WL positive electro-ink, word line WL positive voltage is less than stylized positive voltage; In addition, for P memory cell 20 bits Line to ground reference voltage or low voltage for programming, the R memory cell 10 bit line is connected to a positive voltage that cannot be programmed, so that the P memory cell 20 is programmed to the Degree of pre-programming, for example 80%. In the second stage, the voltages as described above are applied to the SL and WL lines, respectively. Subsequently, the bit line of the R memory cell 10 is connected to ground or a low voltage for programming, and the bit line of the P memory cell 20 is connected to a positive voltage that cannot be programmed to complete the programming. FIG. 6 is a diagram of the memory cell unit structure and programming method according to the present invention. After simulating 600 k times, P memory cells, R memory cells, and traditional single flash memory cells (where t is N memory cells) are erased from data. Then, the relationship between the current distribution read from the P memory cells, R memory cells, and N memory cells and the number of memory cells is shown. In the figure, curve 60 is the memory of three memory cells at the beginning (ie 0 K).

Page 11 536819 V. Description of the invention (9) Relation diagram between cell and current distribution. Curve 6 1 series N memory cells after 6 〇 〇 K, the current read has generally weakened from 4 5-6 0 // A to most in the range of 1 q — 2 0 # A, and the range is wide. The current read from the P memory cell decreases as shown in curve 6 2 to about 8 _ 1 3 // A ', but the memory cell has only a small displacement as shown in curve 6 4, which indicates that the data of the R memory cell is erased. The electrons can still be removed very cleanly. Figure 7 shows the comparison of the performance of the memory cell unit (2 T memory cell combining P memory cell and R memory cell) with the conventional single memory cell (1 T memory cell). Comparison. The curve 72 is the current value that can be read from the 2 T memory cell after the data is erased under different cycles (0 K to 7 OO K). The curve 71 is the current value read from the 1 T memory cell after the data is erased under different cycles of use (0 K to 700 K). Comparing the two, it can be found that the 2 T memory cell still has a large current even after the number of cycles of 7 〇 〇 K (more than 4 A ', and the 1 τ memory cell has a significant current reduction problem even under 50 k 'The current read after the number of cycles of 1 5 Ο Κ has been significantly lower than 1 A' is close to the memory cell just after programming (the electrons are stored in the floating gate). Curve 7 4 shows after programming (floating The relationship between the current read by the 2T memory cell in the gate electrode and the number of cycles. According to the structure of the flash memory cell unit of the present invention, the read data has always been bought and sold to the R memory cell. It can be found that the current can always be maintained below 1 Α. Therefore, the above experimental results prove that the open flash memory cell unit of the present invention can not only erase the data cleanly, but also the data can be stably maintained after programming.

536819 V. Description of the invention (ίο) As can be seen from the above, the switching memory cell of the present invention has the following advantages: The reliability is far beyond the traditional 1 T memory cell. Even after a fairly high (7 0 0 K) number of cycles, the memory cell can still clearly distinguish whether the logic 0 state or the logic 1 state is stored, which is far more than the traditional open flash memory cell unit (traditional approx. Only use it 100K times and so on). The above is a detailed description of the present invention using preferred embodiments, rather than limiting the scope of the present invention, and those skilled in the art will understand that appropriate changes and adjustments will still be made without departing from the spirit of the present invention. Without departing from the spirit and scope of the invention.

Page 13 536819 Schematic description Figure 1 shows the structure of a conventional flash memory cell. Figure 2 shows the traditional open flash memory cells programming the memory cells with program pulses of different time lengths, and then erasing the data. After 3 cycles of use, the number of memory cells on the vertical axis reads the memory cells. The comparison chart of the relationship between the current changes. FIG. 3 is a schematic diagram of a flash memory cell that is opened according to an embodiment of the present invention, and FIG. 4 is a schematic diagram according to the layout of FIG. 3; FIG. Stylized. Figure 6 shows the memory cell unit structure and programming method according to the present invention. After simulating 600 k times, P memory cells, R memory cells, and traditional single flash memory cells (denoted as N memory cells) are erased. Schematic diagram of the relationship between the current distribution read from the P memory cells, R memory cells, and N memory cells and the number of memory cells. Figure 7 shows the comparison of the performance of the memory cell unit (2 T memory cell combining P memory cell and R memory cell) of the present invention with a conventional single memory cell (1 T memory cell). Schematic representation of the data stored in the cell. Drawing number description: 1 floating gate 3 drain 5 FN tunneling oxide layer 2, 15 4 6 control gate source coupling oxide layer

Page 536819 The diagram briefly illustrates the curve 7: The relationship between the number of memory cells and the current read by the memory cell Curve 8: The relationship between the number of memory cells and the current read by the memory cell, each time with 30 // S Stylized curve of program pulse 9: The relationship between the number of memory cells and the current read by the memory cell, each time a program pulse of 40 / z S is used to program the R memory cell (first open flash memory cell) 1 0, 1 0 'P memory cell (second open flash memory cell) 2 0, 2 0' First transistor 40 First transistor 50 Curve 6 1 series of conventional memory cells after 6 0 K The relationship between the number of cells and the current distribution read. Line 60 is the relationship between the memory cells and the current distribution of the three memory cells at the beginning (ie, 0 K). Curve 62 is the relationship between the memory cell and the current distribution of the current read from the P memory cell. However, the R memory cell has only a small amount of displacement as shown. Curve 64 is the relationship between the current memory cell and the current distribution read from the R memory cell. Curve 7 4 shows the relationship between the read current and the number of cycles of the 2 T memory cell after programming (the electrons are stored in the floating gate). The curve 7 1 is from 1 T after the data is erased under different cycles. The current value curve 72 read by the memory cell is the current value that can be read from the 2 T memory cell after the data is erased under different cycles.

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Claims (1)

The flash of memory: Quick memory with two records containing the first flash. There is less of the quick tool to match with the cell of the first cell. The first flash of the flash and the flash of the flash. The and the recipient, · ,, are connected to the 1-cell cell phase, the single memory, the flash memory, the flash memory, the flash memory, the second flash, the quick flash, the second flash, and the second flash. The fast after the first state one by one cell state-reminiscence series 1 Logical logic 536819 6. Application for patent scope 2. The flash memory cell unit described in item 1 of the patent scope also includes a first transistor- The gate is connected to a read signal, and in addition, a source or terminal is connected to the drain of the first flash memory cell, and another source or drain of the first transistor is connected to the sense amplifier. The read signal can be used to determine whether to read the logic state of the first flash memory cell. 3. The flash memory cell unit according to item 1 of the scope of patent application, wherein the first flash memory cell is shared with the source line of the second flash memory cell, and the word line is also shared. 4. The flash memory cell unit described in item 1 of the scope of patent application, further comprising a second transistor, a gate connected to a stylized command signal, and a source or drain electrode and the second flash memory cell. The drain of the second transistor is connected, and the other source or drain of the second transistor is connected to the write buffer. Therefore, the stylized command signal can be used to determine whether to write data to the second flash memory cell. 5. —A stylized method of flash memory cell, the flash memory cell m page 16 536819 6. The scope of the patent application has a first flash memory cell and a second flash memory cell, and the first flash memory cell and the second flash memory cell are connected to a floating gate. The method includes at least the following Steps: The first flash memory cell and the second flash memory cell source are connected to a stylized positive voltage; the younger flash memory cell and the second flash memory cell control gate are connected to a word line ( w 〇rd 1 ine) positive voltage, the word line positive voltage is less than the stylized positive voltage; the bit line of the first flash memory cell is connected to a voltage equivalent to the stylized positive voltage to prevent hot electrons from tunneling the The coupling oxide layer of the first flash memory cell is connected to the floating gate, and the bit line of the second flash memory cell is connected to a ground or a low voltage to allow hot electrons to tunnel through the coupled oxidation of the second flash memory cell. Layer to the floating gate. 6. A programming method for a flash memory cell unit, the flash memory cell unit having a first flash memory cell and a second flash memory cell, and the first flash memory cell and the second flash memory cell The memory cell is connected to a floating gate, and the stylized method includes at least the following steps: the first flash memory cell and the second flash memory cell source are connected to a stylized positive voltage; the first flash memory cell and The second flash memory cell controls the gate to connect to a word line (w0rd 1 ine) positive voltage, the word line positive voltage is less than the stylized positive voltage; the first flash memory cell and the second flash memory Memory cell Page 17 536819 6. The scope of patent application is formalized, and the first flash memory cell occupies a smaller part of the stylization, and the second flash memory cell occupies a larger part of the stylization. 7. The stylization method of item 6 in the scope of patent application, wherein the first flash memory cell occupies a smaller part of the stylization, and the second flash memory cell occupies a larger part of the stylization. The bit line of the first flash memory cell is connected to a first positive voltage, and the bit line of the second flash memory cell is connected to a second positive voltage. The first positive voltage is greater than the second positive voltage, and may be The memory cell is programmed so that a small part of the hot electron tunneling system passes through the coupling oxide layer of the first flash memory cell, and most of the hot electron tunneling system passes through the coupling oxide layer of the second flash memory cell. And to the floating gate. Yuan Yi-style Single Cheng Bao Haihai Shi-Kou Shi 5 Note, the memory cell is connected to the flash memory, and the flash pole is recorded, and the fast-closing method is used to float the unit cell and the memory flash memory cell. Flashing a single flash, two flashes, one flashing, one flashing, and flashing flashes. The flashing method includes at least the following steps: The first stage is programmed through the coupling oxide layer of the second flash flash memory cell. It is reduced to about 80-90%; in the second stage, the remaining part is programmed through the coupling oxide layer of the first flash memory cell. 9. The stylization method according to item 8 of the scope of patent application, wherein the above-mentioned stylization of the first stage includes: connecting the source of the first flash memory cell and the source of the second flash memory cell for one pass Page 18