CN109346528B - Flash memory structure and corresponding programming, erasing and reading method - Google Patents

Flash memory structure and corresponding programming, erasing and reading method Download PDF

Info

Publication number
CN109346528B
CN109346528B CN201811132953.8A CN201811132953A CN109346528B CN 109346528 B CN109346528 B CN 109346528B CN 201811132953 A CN201811132953 A CN 201811132953A CN 109346528 B CN109346528 B CN 109346528B
Authority
CN
China
Prior art keywords
flash memory
substrate
region
charge storage
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811132953.8A
Other languages
Chinese (zh)
Other versions
CN109346528A (en
Inventor
顾经纶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201811132953.8A priority Critical patent/CN109346528B/en
Publication of CN109346528A publication Critical patent/CN109346528A/en
Application granted granted Critical
Publication of CN109346528B publication Critical patent/CN109346528B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to a flash memory structure, comprising: the substrate is internally provided with a source region, a drain region and a channel region positioned between the source region and the drain region, the substrate and the channel are doped by adopting P-type impurities with lower concentration, and the source region and the drain region are doped by adopting N-type impurities with high concentration; and a tunneling oxide layer, a charge storage layer, a blocking oxide layer and a control gate layer which are sequentially stacked on the substrate of the channel region. According to the invention, programming is carried out by using a mode of assisting band-to-band tunneling hot hole injection by back gate bias, hot holes can enter the charge storage layer under the condition of low voltage difference to realize programming, and the requirement on the capacitive coupling coefficient is low. The erasing is carried out by utilizing a channel electron injection mode, electrons in a channel can also enter the charge storage layer under the condition of low voltage difference, so that holes and electrons are combined in a one-to-one correspondence mode, the holes entering the charge storage layer are gradually erased during programming, and the problems of erasing saturation and process window reduction caused by a high-voltage FN erasing mechanism in the prior art are solved.

Description

Flash memory structure and corresponding programming, erasing and reading method
Technical Field
The present invention relates to the field of semiconductors, and more particularly to a flash memory structure and corresponding programming, erasing, and reading methods.
Background
In the prior art, a Flash memory is generally programmed by using a Back gate bias voltage assisted Band (valence Band) Band (conduction Band) Tunneling Hot Electron Injection (B4-Flash for short), and because a Back gate bias voltage is introduced to replace a part of source and drain voltages, the voltage difference between source and drain can be smaller than that of a traditional Flash memory, which is beneficial to reducing the size of the Flash memory. The B4-Flash memory structures are all p-type channels at present.
The inventor researches and discovers that electrons in a charge storage layer are generally erased by utilizing Fowler-Nordheim (FN) electron tunneling effect for a p-type channel Flash memory structure of B4-Flash currently used, and a very large voltage difference (generally required to be more than 15V) needs to be applied between a control gate and a substrate during erasing, but a capacitive coupling coefficient between the control gate and the charge storage layer of the B4-Flash memory is small, and a voltage obtained by the charge storage layer from the control gate through the capacitive coupling effect is also small, so that the electrons in the charge storage layer are not completely erased, and thus, threshold voltage differences between a programmed state (a state after programming) and an erased state (a state after erasing) of the B4-Flash memory are reduced, namely, a process window of a Flash memory device is small.
Disclosure of Invention
According to analysis of the background art, the B4-Flash of the p channel cannot solve the problem of small process window caused by erase saturation in the device structure and the process frame of the B4-Flash.
It is desirable that new Flash memory device structures retain the core advantages of the original p-channel B4-Flash, i.e., substrate bias needs to assist the programming mechanism to facilitate scaling. Because of the influence of small size of the device, the capacitive coupling coefficient of the B4-Flash control gate and the charge storage layer is inherently small, and in order to thoroughly solve the problem of small process window caused by erase saturation, an FN (Flash memory) erase mode requiring large voltage needs to be replaced by a new erase mode, wherein the new erase mode is that the voltage between the control gate and the substrate does not need to be large. The use of lower voltage band-to-band tunneling hot hole injection can be used as the electron erasure mechanism of a conventional Flash memory structure, but the substrate of the P-channel B4-Flash is N-type doped, which can only allow band-to-band tunneling to generate electrons (if band-to-band tunneling to generate holes, it is directly neutralized with the rest of the substrate electrons). Therefore, in the device structure frame of the original P-channel B4-Flash, a lower-voltage band-to-band tunneling hot hole injection can not be used to replace an FN electron erasing mechanism.
The invention provides a new Flash memory structure and a corresponding programming, erasing and reading method, aiming at the problems that the capacitive coupling coefficient between a control gate and a charge storage layer of the existing P-type channel B4-Flash memory structure is small, but the voltage required for erasing is large, and the charge storage layer can not obtain enough voltage for erasing, so that the process window is small, so that the required erasing voltage can be reduced, and the advantages of the original B4-Flash memory in the reduction of the size of a device are inherited.
In order to solve the problems existing in the prior art, the present invention provides a flash memory structure, comprising:
the transistor comprises a substrate, a source electrode region, a drain electrode region and a channel region positioned between the source electrode region and the drain electrode region, wherein the substrate and the channel are doped in a P type manner, and the source electrode region and the drain electrode region are doped in an N type manner; and
and the tunneling oxide layer, the charge storage layer, the blocking oxide layer and the control gate layer are sequentially stacked on the substrate of the channel region.
Optionally, in the flash memory structure, the base includes a silicon substrate, and the channel region is formed with an embedded sige structure.
Optionally, in the flash memory structure, the base includes a silicon substrate, and the source region and the drain region are formed with an embedded sige structure or a silicon structure.
Optionally, in the flash memory structure, a germanium concentration of the channel region is greater than a germanium concentration of the source region and/or the drain region.
Optionally, in the flash memory structure, the depth of the N-type doping is greater than 50 nm.
Optionally, in the flash memory structure, the charge storage layer includes polysilicon or silicon nitride.
The invention also provides a programming method adopting the flash memory structure, which utilizes a substrate bias-assisted band-to-band tunneling hot hole injection mode to inject holes into the charge storage layer.
Optionally, in the programming method, a first programming voltage applied to a control gate line connected to the control gate is-5V to-6V, a second programming voltage applied to a source line connected to the source region is 0V to 1V, a third programming voltage applied to a drain line connected to the drain region is 5V to 6V, and a fourth programming voltage applied to the substrate is-4V to-6V.
The invention also provides an erasing method adopting the flash memory structure, which utilizes a substrate bias voltage assisted channel hot electron injection mode to inject electrons into the charge storage layer.
Optionally, in the erasing method, a first erasing voltage applied to a control gate line connected to the control gate is 4V to 6V, a second erasing voltage applied to a source line connected to the source region is 0, a third erasing voltage applied to a drain line connected to the drain region is 4V to 5V, and a fourth erasing voltage applied to the substrate is 3V to 4V.
The invention also provides a reading method adopting the flash memory structure, a first reading voltage is applied to the control grid line connected with the control grid layer, a second reading voltage is applied to the source electrode line connected with the source electrode area, a third reading voltage is applied to the drain electrode line connected with the drain electrode area, reading current is obtained, when the reading current is larger than a preset value, the flash memory structure is judged to be in a programmed state, and when the reading current is smaller than the preset value, the flash memory structure is judged to be in an erased state.
Optionally, in the reading method, the first reading voltage is 2 to 3V, the second reading voltage is 0V, and the third reading voltage is 0.5 to 1.5V.
The flash memory structure provided by the invention comprises a substrate, and a tunneling oxide layer, a charge storage layer, a blocking oxide layer and a control gate layer which are sequentially stacked on the substrate, wherein a source region, a drain region and a channel positioned between the source region and the drain region are arranged in the substrate, the substrate is doped in a P type, and the source region and the drain region are doped in an N type. The flash memory structure provided by the embodiment of the invention is an N-type channel flash memory structure, programming can be carried out by using a back gate bias voltage to assist band-to-band tunneling hot hole injection mode, and hot holes can enter a charge storage layer to realize programming under the condition of controlling low voltage difference between a gate layer and a substrate. The Flash memory structure of the embodiment of the invention can be erased by utilizing a channel hot electron injection mode, and hot electrons in a channel region can enter the charge storage layer under the condition of controlling low voltage difference between the grid layer and the substrate, so that holes entering the charge storage layer and hot electrons can be neutralized in a one-to-one correspondence manner during programming, the holes entering the charge storage layer are gradually erased during programming, and the problems of erase saturation and process window reduction of a P-type channel B4-Flash structure in the prior art are solved.
The programming, erasing and reading method of the flash memory structure provided by the invention utilizes the flash memory structure, thereby having the same or similar advantages as the flash memory structure provided by the invention.
Drawings
Fig. 1 is a schematic diagram of a programming principle provided by an embodiment of the present invention.
Fig. 2 is a schematic energy band diagram of a band-to-band tunneling hot hole injection method assisted by a back gate bias in the programming method according to the embodiment of the present invention.
Fig. 3 is a schematic band diagram of a back gate bias assisted channel hot electron injection method in an erase method according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating an erasing principle according to an embodiment of the present invention.
Wherein, 100-flash memory structure; 10-a substrate; 11-PN junction depletion region; 12-a source region; 13-a drain region; 14-a channel region; 21-a cavity; 22-electron; 31-tunneling oxide layer; 32-a charge storage layer; 33-barrier oxide layer; 34-control gate layer.
Detailed Description
The invention will be described in more detail below with reference to schematic drawings and examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
An embodiment of the invention includes a flash memory structure, and fig. 1 is a schematic diagram of a programming band provided by an embodiment of the invention. As shown in fig. 1, a flash memory structure 100 according to an embodiment of the present invention includes: a substrate 10, wherein a source region 12, a drain region 13 and a channel region 14 located between the source region 12 and the drain region 13 are arranged in the substrate 10, the substrate 10 and the channel region 14 are doped with P-type, and the source region 12 and the drain region 13 are doped with N-type; and a tunnel oxide layer 31, a charge storage layer 32, a blocking oxide layer 33, and a control gate layer 34 sequentially stacked on the substrate 10 of the channel region 14.
In the flash memory structure 100, the charge storage layer 32 comprises polysilicon or silicon nitride. The base 10 may include a silicon substrate. The doping type of the source region 12 and the drain region 13 is N-type doping, and the depth of the N-type doping region is greater than 50nm, preferably 50 nm.
In the flash memory structure 100 of this embodiment, since the holes 21 in the substrate 10 generally have a large effective mass and a low mobility with respect to the electrons 22, in order to increase the mobility of the holes 21, the channel region 14, the source region 12, and the drain region 13 in the substrate 10 may be configured to include an embedded SiGe (eSiGe) structure, which is based on the principle that a recess is etched in a corresponding region of a silicon substrate, and a SiGe layer is selectively epitaxially grown in the recess, because the lattice constant of ge is larger than that of silicon, and after germanium is doped into silicon, the mobility of the holes 21 is greatly increased under the action of a compressive stress on the SiGe layer. In another embodiment, the embedded sige structure may be provided only in the channel region 14.
Further, in order to achieve the effect of improving the mobility of holes, the mol percentage concentration of germanium in silicon germanium is limited, and the mol percentage concentration of germanium in silicon germanium of the channel region 14 in the present embodiment may be set to be higher than the concentration of germanium in silicon germanium of the source region 12 and/or the drain region 13, for example, by setting the process conditions, the germanium concentration in the eSiGe structure of the channel region 14 may be 70% (mol concentration), and the germanium concentration in the eSiGe structure of the source region 12 and/or the drain region 13 may be 30% (mol concentration), so as to further improve the mobility of the holes 21 in the channel region 14, thereby making up the inherent shortage that the mobility of the holes is low as a programming means.
Embodiments of the present invention also include methods of performing programming, erasing, and reading using the flash memory structure 100 described above. Fig. 2 is a schematic energy band diagram of a band-to-band tunneling hot hole injection method assisted by a back gate bias in the programming method according to the embodiment of the present invention. Fig. 3 is a schematic band diagram of a back gate bias assisted channel hot electron injection method in an erase method according to an embodiment of the present invention. Fig. 4 is a schematic diagram illustrating an erasing principle according to an embodiment of the present invention. The method of programming, erasing and reading the flash memory structure 100 according to the embodiment of the present invention is described with reference to fig. 1 to 4.
The channel region 14 of the flash memory structure 100 of the embodiment of the present invention is P-type doped, and during programming, programming can be performed by using a back-gate bias-assisted Band-to-Band Hot Hole Injection (BTBHHI) mode.
Referring to fig. 1 and 2, the flash memory structure 100 according to the embodiment of the present invention, when programming by using a back-gate bias-assisted band-to-band tunneling hot hole injection method, may include the following processes:
first, under the action of the applied voltage difference (for example, the gate is a negative voltage, the drain is a positive voltage, and the voltage difference is greater than 10V) between the gate (the control gate layer 34 in this embodiment) and the drain (the drain region 13 in this embodiment), an electric field directed from the drain region 13 to the gate forms a strong band bending, so that holes in the drain-substrate PN junction depletion region in the gate-drain overlap region tunnel from the valence band to the conduction band (i.e., band-to-band tunneling) by the quantum tunneling effect, as shown in the process of fig. 1 and 2.
Then, under the acceleration action of the electric field between the substrate and the drain region 13, and between the source region 12 and the drain region 13, the holes 21 move a small distance towards the substrate and the source region, and hole electron pairs are obtained through impact ionization, and the holes obtained through impact ionization have enough energy to cross the barrier of the tunneling oxide layer to become hot holes, as shown in the processes of fig. 1 and 2; the substrate is applied with a large negative voltage, and the holes generated by band-band tunneling play a main acceleration role (compared with the acceleration role of the voltage between the source and the drain on the holes).
Then, under the action of the negative voltage applied to the gate, the hot holes are subjected to a strong vertical electric field toward the gate, and cross the tunnel oxide barrier to enter the charge storage layer 32, thereby completing programming. After the programming is completed, the threshold voltage of the corresponding flash memory device is lowered.
Illustratively, when the flash memory structure 100 according to the embodiment of the present invention performs programming, the first programming voltage Vg applied to the control gate line connected to the control gate layer 34 is-5V to-6V (e.g., -5V), the second programming voltage Vs applied to the source line connected to the source region 12 is 0V to 1V (e.g., 0V), the third programming voltage Vd applied to the drain line connected to the drain region 13 is 5V to 6V (e.g., 5V), and the fourth programming voltage Vb applied to the substrate 10 is-5V to-6V (e.g., -5V).
In this embodiment, the flash memory structure 100 is an N-channel flash memory structure, and can be erased by using a back gate bias to assist channel hot electron injection.
In general, FN erase operates on the principle that a voltage difference between a gate and a substrate causes electrons FN in a charge storage layer to tunnel to the substrate, where a large negative voltage (-8V) is applied to the control gate and a large positive voltage (+8V) is applied to the substrate.
The basic reason why the FN erase mode brings erase saturation is that the capacitive coupling coefficient between the control gate and the charge storage layer is small, which brings two effects:
1. if the charge storage layer is divided from the control gate by a small voltage ratio due to a small capacitive coupling coefficient, the voltage between the charge storage layer and the substrate is small, and it is difficult to erase the electrons in the charge storage layer.
2. The charge storage layer has smaller coupling voltage, which means that the voltage between the control gate and the charge storage layer is larger, and the larger voltage can cause electrons in the control gate to tunnel to the charge storage layer, so that after the erasing is carried out for a certain time, the electrons erased and entered in the charge storage layer are balanced, the number of the electrons is not reduced any more, and the electrons cannot be erased continuously, so that the erasing saturation is caused.
The main methods for increasing the capacitive coupling coefficient between the control gate and the charge storage layer are to reduce the thickness of the blocking oxide layer or to increase the thickness of the tunneling oxide layer. The thickness of the barrier oxide layer cannot be infinitely reduced and reliability problems are more likely to be encountered after reduction. The thickening of the tunnel oxide layer reduces the programming and erasing speed, so that the method is not feasible.
The B4-Flash memory has small device size and thinner tunneling oxide layer, so that the defect of small capacitive coupling coefficient between a control gate and a charge storage layer is caused naturally.
The common N-channel flash memory is erased by FN, a control gate is N-type doped, and a method of injecting P-type impurity ions into the control gate can be used for reducing the free electron concentration of the control gate. Therefore, electrons entering the charge storage layer from the control gate can be reduced during FN (flash memory) erasing, and the erasing saturation problem is reduced. However, this approach is also difficult to implement in P-channel flash memories because the gate itself is P-doped.
The problem of FN erase saturation of B4-Flash memories due to the small capacitive coupling coefficient between the control gate and the charge storage layer has not been alleviated or eradicated by technological methods.
Specifically, referring to fig. 4 and 3, the flash memory structure 100 according to the embodiment of the invention may include the following processes for injecting the electrons 22 in the channel region 14 into the charge storage layer 32 during erasing:
a channel inversion layer (electrons 22) is formed under the action of positive gate voltage (exceeding threshold voltage), a positive voltage is added to the drain region 13, the electrons 22 in the channel region 14 move to the drain region 13 under the action of a transverse electric field of the channel region 14, and different from ordinary channel hot electron injection, positive substrate bias voltage can replace the action of a part of drain terminal voltage, and transverse acceleration acting force is applied to channel electrons, so that the drain terminal voltage can be reduced by a little compared with the condition without substrate bias voltage, and the source-drain depletion region is prevented from being penetrated when the size of a device is reduced.
The electrons 22 are subjected to impact ionization after obtaining sufficient energy to generate hole-electron pairs, a part of the high-energy electrons become hot electrons, enter the charge storage layer 32 across the potential barrier of the tunnel oxide layer 31 under the action of a vertical electric field toward the charge storage layer 32, and neutralize the holes 21 entered during programming in the charge storage layer 32, thereby completing erasing, as shown in fig. 4 and 3.
Illustratively, when the flash memory structure 100 of the embodiment of the invention performs erasing, a first erasing voltage Vg applied to the control gate line connected to the control gate layer 34 is 4V to 6V (e.g., 5V, such that an inversion layer of electrons 22 is formed above the threshold voltage of the device), a second erasing voltage Vs applied to the source line connected to the source region 12 is 0V, a third erasing voltage Vs applied to the drain line connected to the drain region 13 is 4V to 5V (e.g., 5V), and a fourth erasing voltage applied to the substrate is 3V to 4V (e.g., 3V).
As can be seen from the above description, in the programming of the flash memory structure 100 according to the embodiment of the present invention, the flash memory structure 100 can be turned off by applying a negative bias voltage to the control gate line connected to the control gate layer 34, so that the programming current is reduced. Power consumption when programming with channel hot electron injection is greatly reduced relative to P-channel flash memory structure 100.
The flash memory structure 100 of the embodiment of the invention can perform reading to detect the programming and erasing results, i.e. the magnitude of the current in the read drain region can be used to determine whether the holes 21 exist in the charge storage layer 32.
Specifically, a first read voltage may be applied to a control gate line connected to the control gate layer 34, a second read voltage may be applied to a source line connected to the source region 12, a third read voltage may be applied to a drain line connected to the drain region 13, and a read current may be obtained from a bit line of the flash memory device to determine whether or not the holes 21 are present in the charge storage layer 32. If the programmed state is read and the charge storage layer 32 has holes 21, the threshold voltage of the flash memory device is reduced and the reading current is relatively large; if the erased state is read and the charge storage layer 32 has no holes 21, the threshold voltage of the flash memory device is increased and the read current is relatively small. Specifically, a preset value of the read current may be set, and when the read current is greater than the preset value, the flash memory structure 100 is determined to be in the programmed state, and when the read current is less than the preset value, the flash memory structure 100 is determined to be in the erased state. The preset value can be 1 e-6A/mum, and further, the preset value current value is a current value obtained by normalizing the width of the device channel.
For example, when the flash memory structure 100 of the present embodiment performs reading, the first reading voltage is 2V to 3V (e.g., 2.5V), and the second reading voltage and/or the third reading voltage is 0.5V to 1.5V (e.g., the second reading voltage is set to 0V and the third reading voltage is set to 1V).
In summary, the flash memory structure of the embodiment of the invention is an N-type channel flash memory structure, holes are used as programming particles, in order to improve mobility of the holes, an embedded SiGe structure is formed in the channel region, and preferably, Ge concentration of the channel region is higher than Ge concentration of the source region and/or the drain region, that is, a heterojunction is formed between the channel region and the source region (drain region) to further improve mobility of the holes, so that programming efficiency can be improved.
The flash memory structure of the embodiment of the invention can be programmed by using a back gate bias voltage to assist band-to-band tunneling hot hole injection mode, and because the hot holes can enter the charge storage layer under the condition of low voltage difference between the control gate layer and the substrate to realize low voltage when increasing erasing, the requirement on the capacitive coupling coefficient between the control gate and the charge storage layer is lower (for example, the requirement on the thinning of the blocking oxide layer between the control gate and the charge storage layer is lower than that of a P-type channel flash memory structure). The flash memory structure of the embodiment of the invention can be erased by utilizing a channel hot electron injection mode, and hot electrons in a channel region can enter the charge storage layer under the condition of low voltage difference between the control grid layer and the substrate, so that holes entering the charge storage layer can be correspondingly combined with hot electrons one by one during programming, the holes entering the charge storage layer are gradually erased during programming, and the problems of erase saturation and process window reduction caused by adopting FN (FN) erase in the P-type channel flash memory structure in the prior art are solved.
The flash memory structure of the embodiment of the invention can adopt a back gate bias voltage to assist band-to-band tunneling hot electron/hole injection mode to erase and program, wherein the back gate bias voltage replaces a part of source-drain voltage to play a role in accelerating carriers, so that the voltage difference between a source region and a drain region can be smaller than that of a traditional flash memory, namely the source region and the drain region are less prone to punch through when the size (especially the length of a channel) of a device is reduced, and the size reduction of the formed flash memory device is facilitated.
The foregoing embodiments are merely illustrative of the principles of the invention and its efficacy, and are not to be construed as limiting the invention. Those skilled in the art can make various changes, substitutions and alterations to the disclosed embodiments and technical contents without departing from the spirit and scope of the present invention.

Claims (2)

1. An erasing method of a flash memory structure is characterized in that the flash memory structure comprises a substrate, a source region, a drain region and a channel region positioned between the source region and the drain region are arranged in the substrate, the substrate and the channel adopt P-type doping, and the source region and the drain region adopt N-type doping; a tunneling oxide layer, a charge storage layer, a blocking oxide layer and a control gate layer are sequentially stacked on the substrate of the channel region;
the erasing method comprises the following steps: injecting electrons into the charge storage layer by using a substrate bias-assisted channel hot electron injection mode, namely applying a positive first erasing voltage on a control gate line connected with the control gate line, wherein the first erasing voltage is greater than the threshold voltage of the flash memory structure; applying a second erase voltage to a source line connected to the source region, wherein the second erase voltage is 0; applying a positive third erase voltage on a drain line connected to the drain region, applying a positive fourth erase voltage on the substrate, and the third erase voltage being greater than the fourth erase voltage; the charge storage layer is in a floating state.
2. The method of claim 1, wherein the first erase voltage is 4V to 6V, the third erase voltage is 4V to 5V, and the fourth erase voltage is 3V to 4V.
CN201811132953.8A 2018-09-27 2018-09-27 Flash memory structure and corresponding programming, erasing and reading method Active CN109346528B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811132953.8A CN109346528B (en) 2018-09-27 2018-09-27 Flash memory structure and corresponding programming, erasing and reading method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811132953.8A CN109346528B (en) 2018-09-27 2018-09-27 Flash memory structure and corresponding programming, erasing and reading method

Publications (2)

Publication Number Publication Date
CN109346528A CN109346528A (en) 2019-02-15
CN109346528B true CN109346528B (en) 2022-03-29

Family

ID=65307242

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811132953.8A Active CN109346528B (en) 2018-09-27 2018-09-27 Flash memory structure and corresponding programming, erasing and reading method

Country Status (1)

Country Link
CN (1) CN109346528B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416085A (en) * 2019-07-10 2019-11-05 复旦大学 A kind of half floating transistor of SiGe channel structure and preparation method thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6490205B1 (en) * 2000-02-16 2002-12-03 Advanced Micro Devices, Inc. Method of erasing a non-volatile memory cell using a substrate bias
US7133313B2 (en) * 2004-04-26 2006-11-07 Macronix International Co., Ltd. Operation scheme with charge balancing for charge trapping non-volatile memory
CN100442476C (en) * 2005-09-29 2008-12-10 中芯国际集成电路制造(上海)有限公司 Nano-device with enhanced strain inductive transferring rate for CMOS technology and its process
US7321145B2 (en) * 2005-10-13 2008-01-22 Macronix International Co., Ltd. Method and apparatus for operating nonvolatile memory cells with modified band structure
US7242622B2 (en) * 2005-12-06 2007-07-10 Macronix International Co., Ltd. Methods to resolve hard-to-erase condition in charge trapping non-volatile memory
US20080285350A1 (en) * 2007-05-18 2008-11-20 Chih Chieh Yeh Circuit and method for a three dimensional non-volatile memory
CN100570898C (en) * 2007-07-10 2009-12-16 清华大学 Be used for non-volatile memory device of multidigit storage and preparation method thereof
US8462556B1 (en) * 2011-12-15 2013-06-11 Nanjing University Method for operating a high density multi-level cell non-volatile flash memory device
US8674422B2 (en) * 2012-01-30 2014-03-18 Synopsys, Inc. Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
KR102159845B1 (en) * 2012-07-01 2020-09-25 롱지튜드 플래쉬 메모리 솔루션즈 리미티드 Sonos ono stack scaling
CN104241334A (en) * 2014-07-31 2014-12-24 上海华力微电子有限公司 Junctionless transistor
CN104157655B (en) * 2014-08-27 2020-02-21 上海华力微电子有限公司 SONOS flash memory device and compiling method thereof
CN104332469B (en) * 2014-08-27 2021-01-29 上海华力微电子有限公司 n-channel nonvolatile memory element and compiling method thereof
CN105226065B (en) * 2015-08-20 2018-05-01 上海华力微电子有限公司 A kind of dibit SONOS memories and its compiling, erasing and read method
CN105097821B (en) * 2015-08-20 2018-08-10 上海华力微电子有限公司 A kind of N-channel non-volatile flash memory device and its compiling, erasing and read method

Also Published As

Publication number Publication date
CN109346528A (en) 2019-02-15

Similar Documents

Publication Publication Date Title
JP4601316B2 (en) Nonvolatile semiconductor memory device
US9082490B2 (en) Ultra-low power programming method for N-channel semiconductor non-volatile memory
US20100315884A1 (en) Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof
CN104241396B (en) N-channel SONOS device and compiling method thereof
US6207978B1 (en) Flash memory cells having a modulation doped heterojunction structure
US8320192B2 (en) Memory cell, a memory array and a method of programming a memory cell
TWI742299B (en) Electrically erasable programmable nonvolatile memory cell and method of operating memory cell
US7598560B2 (en) Hetero-bimos injection process for non-volatile flash memory
CN109346528B (en) Flash memory structure and corresponding programming, erasing and reading method
US20070087503A1 (en) Improving NROM device characteristics using adjusted gate work function
CN105097821B (en) A kind of N-channel non-volatile flash memory device and its compiling, erasing and read method
CN104157655B (en) SONOS flash memory device and compiling method thereof
KR101042521B1 (en) Capacitorless dram, method of write and read thereof
TWI419166B (en) Low - pressure rapid erasure of nonvolatile memory
KR100640973B1 (en) Method for Programming/Erasing in Flash Memory Device
CN106206748B (en) SONOS device and manufacturing method thereof
US8125020B2 (en) Non-volatile memory devices with charge storage regions
CN104332469B (en) n-channel nonvolatile memory element and compiling method thereof
JP2004087770A (en) Nonvolatile semiconductor memory device and charge injection method thereof
Lo et al. Study of the walk-out effect of junction breakdown instability of the high-voltage depletion-mode N-channel MOSFET for NAND flash peripheral device and an efficient layout solution
US9337352B1 (en) Floating gate flash memory device and compilation method thereof
KR100606929B1 (en) Method for Programming/Erasing Flash Memory Device
US8077512B2 (en) Flash memory cell and method for operating the same
KR100853964B1 (en) The driving method of non-volatile memory device
CN103021462B (en) The method for writing data of SONOS non-volatile memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant