CN102290444A - SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory - Google Patents
SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title abstract description 10
- -1 Silicon Oxide Nitride Chemical class 0.000 title abstract 7
- 229910052814 silicon oxide Inorganic materials 0.000 title abstract 7
- 239000000758 substrate Substances 0.000 claims abstract description 140
- 230000005641 tunneling Effects 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 35
- 230000008569 process Effects 0.000 description 20
- 230000005684 electric field Effects 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010849 ion bombardment Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229920006395 saturated elastomer Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention relates to a SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and a SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory; the SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure comprises a substrate, a tunneling dielectric layer, a trapped charge layer, a top dielectric layer, a conductive layer, a source electrode and a drain electrode, wherein the substrate comprises a first substrate and a second substrate; the first substrate is positioned on the second substrate; the region of ONO (Oxide-Nitride-Oxide) is defined by the first substrate; the surface of the first substrate is a convex surface; the tunneling dielectric layer, the trapped charge layer, the top dielectric layer and the conductive layer are sequentially arranged on the first substrate; the upper surfaces and the lower surfaces of the tunneling dielectric layer, the trapped charge layer, the top dielectric layer and the conductive layer are convex surfaces; and the source electrode and the drain electrode are positioned in the second substrate and are respectively positioned at both sides of the first substrate. The SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure can solve the problem of the erasing saturation of the SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory of the prior art.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to SONOS structure, SONOS memory.
Background technology
Usually, the semiconductor memory that is used to store data is divided into volatile memory and nonvolatile memory, and volatile memory is lost its data easily when power interruptions, even and nonvolatile memory still can be preserved its data when power interruptions.Compare with other nonvolatile storage technologies (for example, disc driver), nonvolatile semiconductor memory is less relatively.Therefore, nonvolatile memory has been widely used in mobile communication system, storage card etc.
Non-volatile memory cells can be realized by one of floating gate structure or SONOS (Silicon-Oxide-Nitride-Oxide-Silicon is called for short SONOS) structure two big major techniques.Floating gate type memory thicker tunnel oxide (70-120 dust) relatively provides good charge holding performance, the technological process ratio is easier to control, in case but there is defective in the tunnel oxide, stored charge is lost from the polysilicon accumulation layer along defective easily.The thinner thickness of the tunnel oxide of SONOS memory utilizes the silicon nitride medium layer of insulation to capture and stored charge, and the trap that silicon nitride is used for catching electric charge is independently, can not cause losing in a large number of electric charge because of a defective.SONOS have also that anti-erasable ability is good, operating voltage is low and power is low, technical process is simple and with advantage such as standard CMOS process compatibility.
Fig. 1 is the schematic diagram of the SONOS structure of prior art, and with reference to figure 1, the SONOS structure of prior art comprises substrate 10; Be positioned at tunneling medium layer 11 on the described substrate 10, catch charge layer 12 and top medium layer 13, wherein, the material of tunneling medium layer 11 is a silica, the material of catching charge layer 12 is a silicon nitride, the material of top medium layer 13 is a silica, tunneling medium layer 11, catches the laminated construction that charge layer 12 and top medium layer 13 have constituted ONO (oxide-nitride-oxide); Be positioned at the grid 14 on the described top medium layer 13; Be positioned at the source electrode 15 of described substrate 10, described laminated construction both sides and drain 16.
The operation principle of SONOS memory is: when writing process, between grid 14 and substrate 10, apply positive voltage (be generally+10V), apply identical low-voltage (be generally 0V) with drain electrode on 16 at source electrode 15, electronics generation tunnelling in the raceway groove is passed tunneling medium layer 11, be stored in and catch in the charge layer 12, finish electron tunneling programming operation process.When erase process, between grid 14 and substrate 10, apply negative voltage (be generally-10V), apply identical low-voltage (be generally 0V) with drain electrode on 15 at source electrode 14, can finish and catch the electron tunneling of catching in the charge layer 12 and pass the erase operation process that tunneling medium layer 11 enters substrate 10.The SONOS memory of above-described prior art exists wipes saturated problem, promptly catch in the charge layer electronics fully tunnelling go out to catch charge layer.Many patent and patent applications about the SONOS memory are arranged, for example disclosed SONOS and forming method thereof in the Chinese patent application that on June 15th, 2011, disclosed publication number was CN102097491A in the prior art.
Summary of the invention
The problem that the present invention solves is that the SONOS memory of prior art exists the saturated problem of wiping.
For addressing the above problem, the invention provides a kind of SONOS structure, comprising:
Substrate, described substrate comprise first substrate and second substrate, and described first substrate is positioned on described second substrate, and described first substrate defines the zone of ONO structure, and the surface of described first substrate is a convex surface;
Be positioned at tunneling medium layer on described first substrate successively, catch charge layer, top medium layer and conductive layer, described tunneling medium layer, the upper surface of catching charge layer, top medium layer and conductive layer, lower surface are convex surface;
Source electrode and drain electrode are positioned at described second substrate, and lay respectively at the both sides of described first substrate.
Optionally, described convex surface is a cambered surface.
Optionally, the material of described tunneling medium layer is a silica.
Optionally, the material of described top medium layer is a silica.
Optionally, described material of catching charge layer is a silicon nitride.
Optionally, the material of described conductive layer is a polysilicon.
Optionally, the material of described substrate is monocrystalline silicon, monocrystalline germanium or silicon-on-insulator.
The present invention also provides a kind of SONOS memory, comprises described SONOS structure, and described a plurality of SONOS structures are arranged in array.
Compared with prior art, the specific embodiment of the invention has the following advantages:
In the technical program, the SONOS structure is a convex configuration, it is tunneling medium layer, catch charge layer and top medium layer, the upper surface of conductive layer, lower surface is convex surface, the upper surface of first substrate that contacts with tunneling medium layer also is convex surface, in this structure, substrate and grid are that the power line between the conductive layer no longer is parallel distribution, but (comprise the top medium layer perpendicular to dielectric layer from grid, catch charge layer and tunneling medium layer) focus on substrate, this makes power line density is that electric field strength constantly increases from the grid to the substrate, even do not have under the situation of electronics (wiping fully) catching charge layer, this structure guarantees that also electric field in the tunneling medium layer is much larger than the electric field of top medium layer, with respect to traditional SONOS structure, this structure is in whole erase process, from catching electron amount that charge layer is tunneling to substrate through tunneling medium layer, efficiently solve traditional SONOS structure with this and wipe saturated problem greater than being tunneling to the electron amount of catching charge layer through the top medium layer from grid.
Description of drawings
Fig. 1 is the schematic diagram of the SONOS structure of prior art;
Fig. 2 is the cross-sectional view of the SONOS structure of the specific embodiment of the invention;
Fig. 3 is the schematic flow sheet of formation method of the SONOS structure of the specific embodiment of the invention
Fig. 4 to Fig. 8 is the cross-sectional view of formation method of the SONOS structure of the specific embodiment of the invention.
Embodiment
Operation principle based on above-described SONOS memory, the SONOS memory adopts FN tunneling effect (Fowler-Nordheim Tunneling) to wipe: the feasible electron tunneling of catching in the charge layer of the high field between grid and substrate is crossed tunneling medium layer and is entered substrate, under the situation that tunneling medium layer thickness is determined, tunnelling process mainly is to be determined by the electric field in the tunneling medium layer, electric field strength is big more, easy more generation tunnelling, the easy more tunnelling of electronics of promptly catching in the charge layer enters substrate.Have two tunnelling processes in the SONOS structure: tunnelling one, electronics are tunneling to through the top medium layer from grid and catch charge layer, tunnelling two: electronics is tunneling to substrate from catching charge layer through tunneling medium layer.In traditional dull and stereotyped SONOS structure, the time to catch in the charge layer quantity of electronics many wiping beginning, and the electric field of tunneling medium layer is much larger than the electric field of top medium layer; Along with the carrying out of wiping, catch that electronics reduces gradually in the charge layer, so the electric field in the tunneling medium layer constantly reduce and in the top medium layer electric field constantly increase; Both electric fields equate when wiping fully.Can infer, in erase process, tunnelling one constantly strengthens owing to the enhancing of top medium layer electric field, tunnelling two is owing to the tunneling medium layer electric field weakens, when tunnelling one and tunnelling two sizableness, promptly be tunneling to the electron amount of catching charge layer through the top medium layer and be tunneling to the electron amount of substrate when suitable through tunneling medium layer from catching charge layer from grid, get very little from the net outflow electrorheological of catching charge layer, just the net outflow electron amount is considerably less, wipes to become very difficult so that can't wipe fully within reasonable time.In the present invention, the SONOS structure is a convex configuration, it is tunneling medium layer, catch charge layer and top medium layer, the upper surface of conductive layer, lower surface is convex surface, the surface of first substrate that contacts with tunneling medium layer also is convex surface, in this structure, substrate and grid are that the power line between the conductive layer no longer is parallel distribution, but (comprise the top medium layer perpendicular to dielectric layer from grid, catch charge layer and tunneling medium layer) focus on substrate, this makes power line density is that electric field strength constantly increases from the grid to the substrate, even do not have under the situation of electronics (wiping fully) catching charge layer, this structure guarantees that also electric field in the tunneling medium layer is much larger than the electric field of top medium layer, with respect to traditional SONOS structure, this structure tunnelling one process is weakened, tunnelling two processes are enhanced, in whole erase process, tunnelling two keeps much larger than tunnelling one always, just, efficiently solve traditional SONOS structure with this and wipe saturated problem from catching electron amount that charge layer is tunneling to substrate through tunneling medium layer much larger than being tunneling to the electron amount of catching charge layer through the top medium layer from grid.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
Fig. 2 is the cross-sectional view of the SONOS structure of the specific embodiment of the invention, with reference to figure 2, the SONOS structure of the specific embodiment of the invention, comprise: substrate 20, described substrate 20 comprises the first substrate 20a and the second substrate 20b, the described first substrate 20a is positioned on the described second substrate 20b, and the described first substrate 20a defines the zone of ONO structure, and the surface of the described first substrate 20a is a convex surface; Be positioned at tunneling medium layer 21 on the described first substrate 20a successively, catch charge layer 22, top medium layer 23 and conductive layer 24, be that described tunneling medium layer 21 is positioned on the described first substrate 20a, the described charge layer 22 of catching is positioned on the described tunneling medium layer 21, described top medium layer 23 is positioned at described catching on the charge layer 22, described conductive layer 24 is positioned on the described top medium layer 23, described tunneling medium layer 21, catch charge layer 22, top medium layer 23 and form the ONO structures, described conductive layer 24 is as grid; Source electrode 25 and drain electrode 26 are positioned at the described second substrate 20b, and lay respectively at the both sides of the first substrate 20a; The upper surface of the lower surface of tunneling medium layer 21 and the first substrate 20a is fitted, catching the lower surface of charge layer 22 and the upper surface of tunneling medium layer 21 fits, the lower surface of top medium layer 23 is fitted with the upper surface of catching charge layer 22, the upper surface of the lower surface of conductive layer 24 and top medium layer 23 is fitted, and therefore described tunneling medium layer 21, upper surface, the lower surface of catching charge layer 22, top medium layer 23 and conductive layer 24 are convex surface.Tunneling medium layer 21, catch charge layer 22, top medium layer 23 and conductive layer 24 and all have side and upper surface, lower surface, two wherein relative with substrate 20 surfaces are respectively upper surface and lower surface, near substrate 20 is lower surface, away from substrate 20 be upper surface, other surfaces between upper surface and lower surface are the side.
In specific embodiments of the invention shown in Figure 2, described convex surface is a cambered surface, but among the present invention, the surface of the first substrate 20a, tunneling medium layer 21, upper surface, the lower surface of catching charge layer 22, top medium layer 23 and conductive layer 24 are not limited to cambered surface, also can be the convex surface of other shapes, as long as guarantee that power line focuses on substrate from grid perpendicular to dielectric layer (comprise the top medium layer, catch charge layer and tunneling medium layer), electric field strength is constantly increased from the grid to the substrate get final product.
In the specific embodiment of the invention, substrate 20 is that the material of the first substrate 20a and the second substrate 20b is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide or silicon-on-insulator (SOI) structure.Be formed with well region and isolation structure (not shown) in substrate 20, in this embodiment, well region is a N type well region, and isolation structure is formed in the substrate 20, between the adjacent SONOS structure.Source electrode 25 and drain electrode 26 are the P type and mix.In other embodiments, well region also can be P type well region, and corresponding source electrode 25 and drain electrode 26 are the N type and mix.Around stacked structure, be formed with the side wall (not shown).
In the specific embodiment of the invention, the material of described tunneling medium layer 21 is a silica, and its thickness is
(dust), and tunneling medium layer 21 thickness everywhere is basic identical.But among the present invention, the material of tunneling medium layer 21 is not limited to silica, also can be for well known to a person skilled in the art other materials.
The material of described top medium layer 23 is a silica, and its thickness is
And top medium layer 23 thickness everywhere is basic identical.But among the present invention, the material of top medium layer 23 is not limited to silica, also can be for well known to a person skilled in the art other materials.
The material of catching charge layer 22 is a silicon nitride, and its thickness is
And it is basic identical to catch charge layer 22 thickness everywhere.But among the present invention, the material of catching charge layer 22 is not limited to silicon nitride, also can be for well known to a person skilled in the art other materials.
Based on above-described SONOS structure, the present invention also provides a kind of SONOS memory, comprises a plurality of above-described SONOS structures, and described a plurality of SONOS structures are arranged in array.About other aspects of this SONOS memory, the arrangement mode of word line, bit line for example, the connected mode of a plurality of SONOS structures, arrangement mode are those skilled in the art's known technology, do not do at this and give unnecessary details.
Based on above-described SONOS structure, the present invention also provides a kind of formation method of SONOS structure, Fig. 3 is the schematic flow sheet of formation method of the SONOS structure of the specific embodiment of the invention, and with reference to figure 3, the formation method of the SONOS structure of the specific embodiment of the invention comprises:
Step S31 provides substrate;
Step S32 forms patterned photoresist layer on described substrate, define the zone of ONO structure on the substrate;
Step S33 is a mask with described patterned photoresist layer, is top less than the described substrate of 90 degree direction dry etchings with the surface of described substrate, and the substrate after being etched is divided into first substrate and second substrate, and the surface of first substrate is a convex surface;
Step S34 removes described patterned photoresist layer;
Step S35 forms tunneling medium layer successively, catches charge layer, top medium layer and conductive layer on described first substrate;
Step S36 carries out ion doping to described second substrate, in described second substrate, the both sides of first substrate form source electrode and drain electrode.
Fig. 4 to Fig. 8 is the cross-sectional view of formation method of the SONOS structure of the specific embodiment of the invention, below in conjunction with the formation method that the SONOS structure of the specific embodiment of the invention is described in detail in detail with reference to figure 3 and Fig. 4 to Fig. 8.
In conjunction with reference to figure 3 and Fig. 4, execution in step S31 provides substrate 20, and in the specific embodiment of the invention, the material of substrate 20 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide or silicon-on-insulator (SOI) structure.Be formed with well region and isolation structure (not shown) in substrate 20, in this embodiment, well region is a N type well region, and isolation structure is formed in the substrate, between the adjacent SONOS structure.Accordingly, source electrode that forms afterwards and drain electrode are the doping of P type.In other embodiments, well region also can be P type well region, and corresponding source electrode that forms afterwards and drain electrode are the N type and mix.Around stacked structure, be formed with the side wall (not shown).
In conjunction with reference to figure 3 and Fig. 5, execution in step S32 forms patterned photoresist layer 30 on described substrate 20, define the zone of ONO structure on the substrate 20; Execution in step S33, with described patterned photoresist layer 30 is mask, be top less than the described substrate 20 of 90 degree direction dry etchings with the surface of described substrate, the substrate 20 after being etched is divided into the first substrate 20a and the second substrate 20b, and the surface of the first substrate 20a is a convex surface.In the specific embodiment of the invention, described convex surface comprises: contact with described photoresist layer 30 and with surperficial equal first 211 of the described second substrate 20b, be positioned at described first 211 side and with described first 211 second 212 of joining, described second 212 is the inclined-plane, with first 211 not at grade; Also comprise the 3rd 213, described the 3rd 213 between the described second substrate 20b and described second 212, described the 3rd 213 between the described second substrate 20b and described second 212, and described the 3rd 213 Surface Vertical with the described second substrate 20b.
In the specific embodiment of the invention, adjust direction and the bombardment power that the ion side direction is bombarded substrate 20 by direction and the power of adjusting bias voltage in the dry etching.Bias voltage can be adjusted the offset direction of the ion in the dry etching, thereby can adjust the direction of ion bombardment substrate 20, usually the power of ion bombardment substrate 20 is divided into the power on vertical substrates 20 surfaces and the power of bombarding substrate 20 from the side, therefore in this dry etching, the substrate that do not hidden by photoresist 20 is removed by ion bombardment, the side of the substrate 20 that is hidden by photoresist is also by a bombardment part, and, the closer to the top, it is big more to be subjected to ion bombardment power, therefore can form the surface and be the first substrate 20a of convex surface.
Afterwards, in conjunction with reference to figure 3 and Fig. 6, execution in step S34 removes described patterned photoresist layer.In the specific embodiment of the invention, remove patterned photoresist layer after, also comprise: the substrate after the described etching is annealed, and making the first substrate 20a convex surface is cambered surface.The condition of annealing is: at H
2During atmosphere was enclosed, temperature was to anneal in 800～900 ℃ of scopes, and under this annealing process, the first substrate 20a can deform, and convex surface becomes the cambered surface of protrusion.Need to prove that the not strict one section cambered surface that refers in the sphere of the cambered surface among the present invention is so long as smooth curved surface promptly satisfies the cambered surface requirement among the present invention.
On the first substrate 20a, form afterwards by tunneling medium layer, when catching the ONO structure that charge layer and top medium layer form and being positioned at conductive layer on the top medium layer, tunneling medium layer, catch charge layer and top medium layer, the shape of conductive layer is all coincide with the shape of the first substrate 20a, it is tunneling medium layer, catch charge layer and top medium layer, the upper surface of conductive layer, lower surface is convex surface, in this embodiment, because the surface of first substrate is cambered surface, then tunneling medium layer, catch charge layer and top medium layer, the upper surface of conductive layer, lower surface also is cambered surface.
With reference to figure 7, after substrate is annealed, also comprise: utilize thermal oxidation process to form oxide layer 31, cover the first substrate 20a and the second substrate 20b, remove described oxide layer 31 afterwards.In the specific embodiment of the invention, the material of oxide layer 31 is a silica, but is not limited to silica.The purpose of utilizing thermal oxidation process to form oxide layer 31 is to repair carries out in the annealing process substrate, and the defective that forms in substrate guarantees that with this performance of device is not subjected to the influence of annealing process.After forming oxide layer 31, utilize wet etching to remove oxide layer 31 again.In other embodiments of the invention, if can in substrate 20, not form defective in the annealing process, then do not need to carry out the growth of oxide layer 31.
In conjunction with reference to figure 3 and Fig. 8, execution in step S35 forms tunneling medium layer 21 successively, catches charge layer 22, top medium layer 23 and conductive layer 24 on the described first substrate 20a.In the specific embodiment of the invention, after removing oxide layer 31, on the substrate of the described first substrate 20a, form tunneling medium layer 21 successively, catch charge layer 22, top medium layer 23 and conductive layer 24.Concrete grammar is: form tunneling medium layer 21 on the first substrate 20a and the second substrate 20b, form on tunneling medium layer 21 and catch charge layer 22, catching formation top medium layer 23 on the charge layer 22, form conductive layer 24 on top medium layer 23.Then, utilize photoetching, the graphical tunneling medium layer 21 of etching technics, catch tunneling medium layer 21 on charge layer 22, top medium layer 23 and the conductive layer 24 residues first substrate 20a substrate, catch charge layer 22, top medium layer 23 and conductive layer 24.
In the specific embodiment of the invention, the material of described tunneling medium layer 21 is a silica, and its thickness is
The formation method is chemical vapour deposition (CVD).But among the present invention, the material of tunneling medium layer 21 is not limited to silica, also can be for well known to a person skilled in the art other materials.The material of top medium layer 23 is a silica, and its thickness is
The formation method is chemical vapour deposition (CVD), but among the present invention, the material of top medium layer 23 is not limited to silica, also can be for well known to a person skilled in the art other materials.The material of catching charge layer 22 is a silicon nitride, and its thickness is
The formation method is chemical vapour deposition (CVD), but among the present invention, the material of catching charge layer 22 is not limited to silicon nitride, and the formation method is chemical vapour deposition (CVD), also can be for well known to a person skilled in the art other materials.Conductive layer 24 is as grid, and its material is a polysilicon, and thickness is
The formation method is vapour deposition, but among the present invention, the material of conductive layer 24 is not limited to polysilicon, also can be for well known to a person skilled in the art other materials.
Continuation is with reference to figure 8, and execution in step S36 carries out ion doping to the described second substrate 20b, in the described second substrate 20b, the both sides of the first substrate 20a form source electrode 25 and drain 26.Wherein, before forming source electrode 25 and drain electrode 26, forming side wall around the stacked structure that also be included in tunneling medium layer 21, catch charge layer 22, top medium layer 23 and conductive layer 24 forms, is that mask carries out ion doping to form source electrode 25 and to drain 26 to the second substrate 20b with stacked structure, side wall afterwards.The ionic type that mixes is determined according to the type of the SONOS structure that forms.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (8)
1. a SONOS structure is characterized in that, comprising:
Substrate, described substrate comprise first substrate and second substrate, and described first substrate is positioned on described second substrate, and described first substrate defines the zone of ONO structure, and the surface of described first substrate is a convex surface;
Be positioned at tunneling medium layer on described first substrate successively, catch charge layer, top medium layer and conductive layer, described tunneling medium layer, the upper surface of catching charge layer, top medium layer and conductive layer, lower surface are convex surface;
Source electrode and drain electrode are positioned at described second substrate, and lay respectively at the both sides of described first substrate.
2. SONOS structure as claimed in claim 1 is characterized in that, described convex surface is a cambered surface.
3. SONOS structure as claimed in claim 1 or 2 is characterized in that, the material of described tunneling medium layer is a silica.
4. SONOS structure as claimed in claim 1 or 2 is characterized in that, the material of described top medium layer is a silica.
5. SONOS structure as claimed in claim 1 or 2 is characterized in that, described material of catching charge layer is a silicon nitride.
6. SONOS structure as claimed in claim 1 or 2 is characterized in that, the material of described conductive layer is a polysilicon.
7. SONOS structure as claimed in claim 1 or 2 is characterized in that, the material of described substrate is monocrystalline silicon, monocrystalline germanium or silicon-on-insulator.
8. a SONOS memory is characterized in that, comprises each described SONOS structure of a plurality of claims 1～7, and described a plurality of SONOS structures are arranged in array.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709292A (en) * | 2012-05-22 | 2012-10-03 | 上海宏力半导体制造有限公司 | SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof |
| CN104253160A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102709292A (en) * | 2012-05-22 | 2012-10-03 | 上海宏力半导体制造有限公司 | SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof |
| CN104253160A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
| CN104253131A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
| CN104253161A (en) * | 2014-07-31 | 2014-12-31 | 上海华力微电子有限公司 | B4-Flash with convexity grid electrode structure |
| CN104253160B (en) * | 2014-07-31 | 2017-07-07 | 上海华力微电子有限公司 | A kind of B4 Flash with convex surface grid structure |
| CN104253161B (en) * | 2014-07-31 | 2017-07-07 | 上海华力微电子有限公司 | A kind of B4 Flash with convex surface grid structure |
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