CN105097814A - Semiconductor memory, semiconductor memory array and operating method thereof - Google Patents
Semiconductor memory, semiconductor memory array and operating method thereof Download PDFInfo
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- CN105097814A CN105097814A CN201410218841.XA CN201410218841A CN105097814A CN 105097814 A CN105097814 A CN 105097814A CN 201410218841 A CN201410218841 A CN 201410218841A CN 105097814 A CN105097814 A CN 105097814A
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Abstract
The invention provides a semiconductor memory. The semiconductor array at least comprises a semiconductor substrate. The semiconductor substrate comprises at least one storage bit structure. The storage bit structure comprises the components of a source doped region and a drain doped region which are formed in the semiconductor substrate; a memory gate stack structure which is formed on the semiconductor substrate between the source doped region and the drain doped region; sidewalls which are formed at two sides of the memory gate stacking structure and comprises a source sidewall at the side of the source doped region and a drain sidewall at the side of the drain doped region; and metal contact structures which are formed outside the sidewalls and comprise a source metal contact structure on the source doped region and a drain metal contact structure on the drain doped region; wherein the thickness of the drain sidewall is smaller than 120 angstroms. The semiconductor memory provided by the technical solution can prevent a problem of memory service life reduction caused by activation of all storage bit structures in erasing in prior art.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, particularly relate to a kind of semiconductor memory, semiconductor memory array and method of operation thereof.
Background technology
At traditional ETOXNORflash memory as shown in Figure 1, comprise formation bank bit structure over the semiconductor substrate 10, wherein each bank bit structure comprises formation source doping region S in the semiconductor substrate and drain doping region D, be formed in the storage grid stack architecture 30 in the Semiconductor substrate between source doping region and drain doping region, and be formed in the side wall 20 of described storage grid stack architecture 30 both sides.Described storage grid stack architecture 30 comprises: the tunnel oxide 14 being positioned at described semiconductor substrate surface; Be positioned at the floating gate layer FG on described tunnel oxide 14; Be positioned at the ONO layer (sign) on described floating gate layer FG; Be positioned at the control grid layer CG on described ONO layer.Described floating gate layer and control grid layer are polysilicon layer.Wherein, the side wall 20 of described storage grid stack architecture 30 both sides is that the technique utilizing tradition to form side wall is formed, and the appearance of the side wall 20 of both sides is roughly the same, is the class ramp structure of upper-thin-lower-thick.Described side wall 20 can be sandwich construction, as comprised first side wall layer (not shown) of storage grid stack architecture 30 as described in next-door neighbour and the second side wall layer (not shown) of being positioned at outside the first side wall, material can be the composition of silicon nitride, silicon oxynitride, silica or three.
Shown in composition graphs 2, the semiconductor memory array that Fig. 2 is formed for the bank bit textural association shown in Fig. 1.Described semiconductor memory array comprises bank bit structure described at least two row two row Fig. 1.Drain metal contacts structure 40 with the described bank bit structure of a line is electrically connected to mutually bit line W, the source metal contact structures 60 of the described bank bit structure of same row are electrically connected to wordline B mutually, and the storage grid stack architecture 30 with the described bank bit structure of a line is electrically connected to mutually control grid line C by control gate metal contact structure 50.
In conventional art, carrying out write operation for the bank bit structure shown in Fig. 1 and Fig. 2 and semiconductor memory array is:
Choose the bank bit in described semiconductor memory array, voltage 4.2V is provided to the bit line that selected bank bit connects, voltage 0V is provided to the wordline that selected bank bit connects, there is provided voltage 9.5V to the control grid line that selected bank bit connects, provide voltage 0V to described Semiconductor substrate;
Carrying out erase operation for the bank bit structure shown in Fig. 1 and Fig. 2 and semiconductor memory array is: choose the bank bit in described semiconductor memory array, there is provided voltage 7V to wordline, bit line and described Semiconductor substrate that selected bank bit connects, provide voltage-8V to the control grid line that selected bank bit connects.
In above-mentioned erase operation, in selected bank bit structure, electronics enters Semiconductor substrate from floating gate layer FG by the tunnel oxide 14 between floating gate layer FG and Semiconductor substrate 10, thus realizes the erase operation to bank bit structure.
But the wordline of described selected bank bit structure, bit line and Semiconductor substrate together provide identical voltage, the all bank bit structures being arranged in same semicondctor storage array are all activated, and only have selected bank bit structure to need to carry out erase operation, and, often carry out an erase operation, all bank bit structures will be made to be activated, this brings very large loss to bank bit structure, shortens the life-span of the semiconductor memory applying described bank bit structure greatly.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of semiconductor memory, semiconductor memory array and method of operation thereof, for solving in prior art when carrying out erase operation, the problem that all bank bit structures all will be activated.
For achieving the above object and other relevant objects, the invention provides a kind of semiconductor memory, described semiconductor memory at least comprises Semiconductor substrate, described Semiconductor substrate at least comprises a bank bit structure, and described bank bit structure comprises:
Form source doping region in the semiconductor substrate and drain doping region;
Be formed in the storage grid stack architecture in the Semiconductor substrate between source doping region and drain doping region;
Be formed in the side wall of storage grid stacked structure both sides, comprise the source electrode side wall being positioned at source doping region side and the drain electrode side wall being positioned at drain doping region side;
Be formed in the metal contact structure outside side wall, comprise the source metal contact structures be positioned in source doping region and the drain metal contacts structure be positioned in drain doping region;
Wherein, the thickness of described source electrode side wall is less than
Preferably, described drain metal contacts structure is lower than described storage grid stack architecture.
Preferably, described storage grid stack architecture comprises: the tunnel oxide being positioned at described semiconductor substrate surface; Be positioned at the floating gate layer on described tunnel oxide; Be positioned at the ONO layer on described floating gate layer; Be positioned at the control grid layer on described ONO layer.Preferably, described floating gate layer and control grid layer are polysilicon layer.
Preferably, described source electrode side wall is the strip of upper and lower consistency of thickness.
Accordingly, technical scheme of the present invention additionally provides a kind of semiconductor memory array, described semiconductor memory array comprises at least two row two and arranges bank bit structure described above, drain metal contacts structure with the described bank bit structure of a line is electrically connected to bit line mutually, the source metal contact structures of the described bank bit structure of same row are electrically connected to wordline mutually, and the storage grid stack architecture with the described bank bit structure of a line is electrically connected to mutually control grid line.
Preferably, described semiconductor memory array at least comprises a memory cell, described memory cell comprises two the first bank bit structure be oppositely arranged and the second bank bit structures, shares source metal contact structures between the source electrode side wall of described first bank bit structure and the source electrode side wall of the second bank bit structure.
Preferably, described semiconductor memory array at least comprises the first memory cell and the second memory cell that are oppositely arranged, shares a drain metal contacts structure between the drain electrode side wall that described first memory cell is adjacent with the second memory cell.
Accordingly, technical scheme of the present invention additionally provides a kind of method of operation of semiconductor memory array, and the method for operation of described semiconductor memory array at least comprises:
Semiconductor memory array as above is provided;
Carry out write operation: choose the bank bit structure in described semiconductor memory array, voltage 3.5V ~ 5.5V is provided to the bit line that selected bank bit structure connects, voltage 0V is provided to the wordline that selected bank bit connects, there is provided voltage 8V ~ 10V to the control grid line that selected bank bit structure connects, provide voltage 0V to described Semiconductor substrate;
Carry out erase operation: choose the bank bit structure in described semiconductor memory array, voltage 6V is provided to the bit line that selected bank bit structure connects, there is provided voltage-11V to the wordline that selected bank bit structure connects, the control grid line connect selected bank bit structure and described Semiconductor substrate provide identical voltage.
As mentioned above, semiconductor memory of the present invention, semiconductor memory array and method of operation thereof, have following beneficial effect:
Because the thickness of the drain electrode side wall of bank bit structure each in semiconductor memory is less than
electronics when erase operation can enter drain electrode through drain electrode side wall thus complete erase operation from floating gate layer.Because described control grid line and Semiconductor substrate are provided identical voltage, make the bank bit structure except being chosen by wordline and bit line, other bank bit structure in described Semiconductor substrate is not activated, avoid the damage brought not needing to be activated when wiping, thus extend the useful life of semiconductor memory.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of the semiconductor storage bit architecture in conventional art.
Fig. 2 is shown as the schematic diagram of the semiconductor memory array in conventional art.
Fig. 3 is shown as the schematic diagram of the semiconductor storage bit architecture provided in embodiments of the invention.
Fig. 4 is shown as the schematic diagram of the semiconductor memory array provided in embodiments of the invention.
Element numbers explanation
10 Semiconductor substrate
S source doping region
D drain doping region
30 storage grid stack architectures
20 side walls
14 tunnel oxides
FG floating gate layer
CG control grid layer
40 drain metal contacts structures
50 control gate metal contact structures
60 source metal contact structures
100 Semiconductor substrate
300 storage grid stack architectures
200 side walls
140 tunnel oxides
400 drain metal contacts structures
500 control gate metal contact structures
600 source metal contact structures
210 source electrode side walls
220 drain electrode side walls
W bit line
B wordline
C controls grid line
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 3 to Fig. 4.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Figure 3, provide a kind of semiconductor memory in the present embodiment, described semiconductor memory at least comprises Semiconductor substrate 100, described Semiconductor substrate 100 at least comprises a bank bit structure, and described bank bit structure comprises:
Form source doping region S in the semiconductor substrate and drain doping region D; General, described source doping region S and drain doping region D can adopt photoetching process and plasma doping process to be formed, and source doping region S between adjacent two bank bit structures and drain doping region D shares.
Described bank bit structure also comprises: be formed in the storage grid stack architecture 300 in the Semiconductor substrate 100 between source doping region S and drain doping region D; Preferably, described storage grid stack architecture 300 comprises: the tunnel oxide 140 being positioned at described Semiconductor substrate 100 surface; Be positioned at the floating gate layer FG on described tunnel oxide 140; Be positioned at the ONO layer on described floating gate layer FG; Be positioned at the control grid layer CG on described ONO layer.
Described storage grid stack architecture can repeatedly adopt semiconductor film-forming process to form layers of material layer, then utilize the structure in Semiconductor substrate 100 between photoetching and selective etch technique reservation source doping region S and drain doping region D, thus form described storage grid stack architecture.
Concrete, wherein a kind of execution mode can be:
Described tunnel oxide 140 adopts thermal oxidation technology or chemical vapor deposition method to be formed, and thickness is
Described ONO layer (oxide layer-nitride layer-oxide layer) can adopt repeatedly carries out chemical vapor deposition method and forms each layer, is made up of bottom oxide layer, nitration case and top layer oxide layer.Preferably, adopt thinner bottom oxide layer and thicker top layer oxide layer, higher critical electric field strength can be ensured, thinner equivalent oxide thickness can be obtained again, improve coupling efficiency, reduce program voltage.
Described floating gate layer FG and control grid layer CG is doped polysilicon layer, described doped polysilicon layer generally can adopt chemical vapor deposition method, and carry out in-situ doped formation simultaneously, or adopt chemical vapor deposition method to form polysilicon layer, then adopt ion implantation to carry out adulterating that polysilicon layer is formed doped polysilicon layer.
Described bank bit structure also comprises: the side wall being formed in storage grid stacked structure 300 both sides, and described side wall comprises the source electrode side wall 210 being positioned at source doping region S side and the drain electrode side wall 220 being positioned at drain doping region D side; Wherein, the thickness of described drain electrode side wall 220 is less than
preferably, the material of described drain electrode side wall 220 is silica, and pattern is the strip of upper and lower consistency of thickness.
Concrete, described source electrode side wall 210 and drain electrode side wall 220 can be formed respectively in different process.Wherein a kind of execution mode can be, traditional side wall technique is adopted to form the side wall of both sides, then adopt photoetching and etching technics by the side wall removing above drain doping region D, the opening stayed after adopting the depositing operation side wall formed above silica-filled drain doping region D to be removed again, and then utilize photoetching and etching technics, etch the figure of source metal contact structures 400 in silica in said opening.
Described bank bit structure also comprises: be formed in the metal contact structure outside side wall 210,220, described metal contact structure comprises: be positioned at the source metal contact structures 400 on source doping region S, be positioned at the drain metal contacts structure 600 on drain doping region D and connect the control gate metal contact structure 500 of bank bit structure control grid CG; Preferably, described drain metal contacts structure 600 is formed directly in the groove between adjacent two drain electrode side walls 220, and its height is lower than described storage grid stack architecture 300.Concrete, described metal contact structure can adopt Damascus technics to be formed.
Accordingly, as shown in Figure 4, a kind of semiconductor memory array is additionally provided in the present embodiment, described semiconductor memory array comprises at least two row two and arranges bank bit structure as shown in Figure 3, drain metal contacts structure 400 with the described bank bit structure of a line is electrically connected to mutually bit line W, the source metal contact structures 600 of the described bank bit structure of same row are electrically connected to wordline B mutually, and the memory control gate metal contact structure 500 with the described bank bit structure of a line is electrically connected to mutually and controls grid line G.
Wherein, continue with reference to shown in figure 3, described semiconductor memory array at least comprises a memory cell, described memory cell comprises two the first bank bit structure N1 be oppositely arranged and the second bank bit structure N2, share a drain doping region D between the drain electrode side wall 220 of described first bank bit structure N1 and the drain electrode side wall 220 of the second bank bit structure N2, and share a drain metal contacts structure 400.
In addition, described semiconductor memory array at least comprises the first memory cell and the second memory cell that are oppositely arranged, shares source metal contact structures 600 between the source electrode side wall 210 that described first memory cell is adjacent with the second memory cell.
Accordingly, additionally provide a kind of method of operation of semiconductor memory array in the present embodiment, the method for operation of described semiconductor memory array at least comprises:
Semiconductor memory array as above is provided;
Carry out write operation: choose the bank bit structure in described semiconductor memory array, voltage 4.2V is provided to the bit line that selected bank bit structure connects, voltage 0V is provided to the wordline that selected bank bit structure connects, there is provided voltage 9.5V to the control grid line that selected bank bit structure connects, provide voltage 0V to described Semiconductor substrate;
Carry out erase operation: choose the bank bit in described semiconductor memory array, voltage 6V is provided to the bit line that selected bank bit structure connects, there is provided voltage-11V to the wordline that selected bank bit structure connects, the control grid line C connect selected bank bit structure and described Semiconductor substrate 100 provide identical voltage.
In above-mentioned erase operation, because the thickness of the side wall 220 that drains is less than
electronics when erase operation can enter drain D through drain electrode side wall 220 thus complete erase operation from floating gate layer FG.Because described control grid line CG and Semiconductor substrate 100 are provided identical voltage, except the bank bit structure chosen by wordline and bit line, other bank bit structure in described Semiconductor substrate 100 is not activated, avoid the damage brought not needing to be activated when wiping, thus extend the useful life of semiconductor memory.
In sum, the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (9)
1. a semiconductor memory, is characterized in that, described semiconductor memory at least comprises Semiconductor substrate, described Semiconductor substrate at least comprises a bank bit structure, and described bank bit structure comprises:
Form source doping region in the semiconductor substrate and drain doping region;
Be formed in the storage grid stack architecture in the Semiconductor substrate between source doping region and drain doping region;
Be formed in the side wall of storage grid stacked structure both sides, comprise the source electrode side wall being positioned at source doping region side and the drain electrode side wall being positioned at drain doping region side;
Be formed in the metal contact structure outside side wall, comprise the source metal contact structures be positioned in source doping region and the drain metal contacts structure be positioned in drain doping region;
Wherein, the thickness of described drain electrode side wall is less than
2. semiconductor memory according to claim 1, is characterized in that: described drain metal contacts structure is lower than described storage grid stack architecture.
3. semiconductor memory according to claim 1, is characterized in that: described storage grid stack architecture comprises: the tunnel oxide being positioned at described semiconductor substrate surface; Be positioned at the floating gate layer on described tunnel oxide; Be positioned at the ONO layer on described floating gate layer; Be positioned at the control grid layer on described ONO layer.
4. semiconductor memory according to claim 3, is characterized in that: described floating gate layer and control grid layer are polysilicon layer.
5. semiconductor memory according to claim 1, is characterized in that: described drain electrode side wall is the strip of upper and lower consistency of thickness.
6. a semiconductor memory array, it is characterized in that: described semiconductor memory array comprises at least two row two and arranges bank bit structure as claimed in claim 1, drain metal contacts structure with the described bank bit structure of a line is electrically connected to bit line mutually, the source metal contact structures of the described bank bit structure of same row are electrically connected to wordline mutually, and the storage grid stack architecture with the described bank bit structure of a line is electrically connected to mutually control grid line.
7. semiconductor memory array according to claim 6, it is characterized in that: described semiconductor memory array at least comprises a memory cell, described memory cell comprises two the first bank bit structure be oppositely arranged and the second bank bit structures, shares a drain metal contacts structure between the drain electrode side wall of described first bank bit structure and the drain electrode side wall of the second bank bit structure.
8. semiconductor memory array according to claim 7, it is characterized in that: described semiconductor memory array at least comprises the first memory cell and the second memory cell that are oppositely arranged, between the source electrode side wall that described first memory cell is adjacent with the second memory cell, share source metal contact structures.
9. a method of operation for semiconductor memory array, is characterized in that: the method for operation of described semiconductor memory array at least comprises:
Semiconductor memory array as claimed in claim 6 is provided;
Carry out write operation: choose the bank bit structure in described semiconductor memory array, voltage 3.5V ~ 5.5V is provided to the bit line that selected bank bit structure connects, voltage 0V is provided to the wordline that selected bank bit connects, there is provided voltage 8V ~ 10V to the control grid line that selected bank bit structure connects, provide voltage 0V to described Semiconductor substrate;
Carry out erase operation: choose the bank bit structure in described semiconductor memory array, voltage 6V is provided to the bit line that selected bank bit structure connects, there is provided voltage-11V to the wordline that selected bank bit structure connects, the control grid line connect selected bank bit structure and described Semiconductor substrate provide identical voltage.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134457A (en) * | 2016-02-29 | 2017-09-05 | 东芝存储器株式会社 | Semiconductor storage and its manufacture method |
| CN108493190A (en) * | 2018-03-06 | 2018-09-04 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
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| CN1674257A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | Fast-flash memory structure and producing method thereof |
| CN1917209A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Programmable and eraseable digital switch component, manufacturing method, and operation method |
| TW201001717A (en) * | 2008-04-17 | 2010-01-01 | Sandisk Corp | Non-volatile memory with sidewall channels and raised source/drain regions |
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- 2014-05-22 CN CN201410218841.XA patent/CN105097814B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1674257A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | Fast-flash memory structure and producing method thereof |
| CN1917209A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Programmable and eraseable digital switch component, manufacturing method, and operation method |
| TW201001717A (en) * | 2008-04-17 | 2010-01-01 | Sandisk Corp | Non-volatile memory with sidewall channels and raised source/drain regions |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107134457A (en) * | 2016-02-29 | 2017-09-05 | 东芝存储器株式会社 | Semiconductor storage and its manufacture method |
| CN107134457B (en) * | 2016-02-29 | 2020-12-08 | 东芝存储器株式会社 | Semiconductor memory device and method of manufacturing the same |
| CN108493190A (en) * | 2018-03-06 | 2018-09-04 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN108493190B (en) * | 2018-03-06 | 2021-03-23 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
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| CN105097814B (en) | 2019-05-17 |
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