CN108493190A - Memory and forming method thereof - Google Patents
Memory and forming method thereof Download PDFInfo
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- CN108493190A CN108493190A CN201810183297.8A CN201810183297A CN108493190A CN 108493190 A CN108493190 A CN 108493190A CN 201810183297 A CN201810183297 A CN 201810183297A CN 108493190 A CN108493190 A CN 108493190A
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- floating gate
- side wall
- gate structure
- erasing
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
A kind of memory and forming method thereof, including：Form erasing gate structure, floating gate structure and the side wall in floating gate structure, floating gate structure and side wall are corresponding with backwards to the first side wall and second sidewall for wiping gate structure respectively in channel direction, the first side wall is in planar, the first side wall is recessed towards erasing gate structure relative to second sidewall, and the first side wall and second sidewall are discontinuous；Isolation film is formed in erasing gate structure, floating gate structure and side face of wall and semiconductor substrate surface, isolation film covers the first side wall and second sidewall；Barrier film is formed on the surface of isolation film；Barrier film is etched back to the isolation film for exposing semiconductor substrate surface, forms the barrier layer of covering the first side wall and second sidewall；It is that mask etching isolation film covers the separation layer of the first side wall and second sidewall to semiconductor substrate surface, formation is exposed using barrier layer；Barrier layer is removed later.The method improves the performance of memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of memory and forming method thereof.
Background technology
Flash memory is a kind of important device in IC products.Flash memory is mainly characterized by being not added with
The information of storage can be kept in the case of voltage for a long time.Flash memory has integrated level height, faster access speed and is easy to
The advantages that erasing, thus be widely used.
Flash memory is divided into two types：Gatestack (stack gate) flash memory and divide grid (split gate) fast
Flash memory.Gatestack flash memory has floating boom and the control gate positioned at the top of floating boom.Gatestack flash memory existed
The problem of erasing.Unlike gatestack flash memory, Split-gate flash memory is formed in the side of floating boom as erasing grid
The wordline of pole.Split-gate flash memory can effectively avoid erasure effect.
However, the performance of existing Split-gate flash memory is poor.
Invention content
Problems solved by the invention is to provide a kind of memory and forming method thereof, to improve the performance of memory.
To solve the above problems, the present invention provides a kind of forming method of memory, including：Semiconductor substrate, institute are provided
It includes scratching area and floating gate region to state semiconductor substrate, and the floating gate region is adjacent with scratching area and is located at scratching area both sides；Form position
In on the scratching area erasing gate structure, the floating gate structure that is located on floating gate region and be located at floating gate structure
On side wall, the floating gate structure channel direction have backwards to wipe gate structure the first side wall, the side wall is in ditch
Road direction has backwards to the second sidewall for wiping gate structure, and the first side wall is in planar, and the first side wall is relative to second sidewall
Recessed towards erasing gate structure, the first side wall and second sidewall are discontinuous；The erasing gate structure, floating gate structure and
The surface of side face of wall and semiconductor substrate forms isolation film, and isolation film covering the first side wall and the second side
Wall；Barrier film is formed on the surface of the isolation film；The barrier film is etched back to until exposing positioned at semiconductor substrate surface
Isolation film, form the barrier layer of covering the first side wall and second sidewall, and between the barrier layer and side wall and barrier layer
There is isolation film between floating gate structure；It is mask etching isolation film until expose semiconductor substrate table using the barrier layer
Face makes the isolation film form the separation layer of covering the first side wall and second sidewall；After forming the separation layer, the resistance is removed
Barrier.
Optionally, the scratching area and the floating gate region constitute erasing floating gate area；The semiconductor substrate further includes several
Wordline bitline regions, the erasing floating gate area abut between adjacent wordline bitline regions and with wordline bitline regions, are wiped from floating boom
Except the direction being oriented parallel to from scratching area to floating gate region in area to wordline bitline regions；Form the erasing gate structure, floating boom
Pole structure and the method for side wall include：Floating gate structure is formed in the part erasing floating gate area of scratching area and semiconductor substrate
Film, and the floating gate structural membrane in erasing floating gate area also extends on the wordline bitline regions of semiconductor substrate；In floating gate
Several discrete dielectric layers are formed in structural membrane and semiconductor substrate, there is the first opening, first opens between adjacent dielectric layer
Mouth is located on floating gate region and does not extend on scratching area and wordline bitline regions；Side wall is formed in the first opening；After forming side wall,
The floating gate structural membrane on the dielectric layer and scratching area on scratching area is removed, second is formed in the dielectric layer and is open, described second
Opening also extends in floating gate structural membrane, and the bottom-exposed of the second opening goes out semiconductor substrate；It is formed and is wiped in the second opening
Except gate structure；After forming erasing gate structure, the floating gate of the dielectric layer and wordline bitline regions of etching removal wordline bitline regions
Structural membrane and the part floating gate structural membrane of side wall bottom form the floating gate structure in the bottom of side wall.
Optionally, further include：Before forming the erasing gate structure, served as a contrast in the semiconductor of second open bottom
Source region is formed in bottom；After forming the erasing gate structure, the source region is located at the semiconductor of the erasing gate structure bottom
In substrate.
Optionally, the floating gate structural membrane and side wall of the dielectric layer and wordline bitline regions of etching removal wordline bitline regions
The technique of the part floating gate structural membrane of bottom includes dry carving technology, and the parameter of the dry carving technology includes：The gas packet of use
Include HBr, He, O2And Cl2, the flow of HBr is 80sccm~150sccm, He and O2Total flow be 3sccm~8sccm, O2
He and O2Total flow in molar percentage be 28%~32%, Cl2Flow be 5sccm~15sccm, source radio-frequency power is
200 watts~300 watts, bias voltage is 200 volts~300 volts, and chamber pressure is 5mtorr~20mtorr.
Optionally, further include：It is formed before side wall in the first opening, etches the floating gate structure of the first open bottom
Film keeps the surface for the floating gate structural membrane that the first opening exposes recessed；After forming the floating gate structure, the floating boom
The surface of pole structure towards side wall is recessed, and the floating gate structure also has the third side wall towards erasing gate structure,
The height of the first side wall is less than the height of third side wall；The first side wall is perpendicular to the surface of the semiconductor substrate.
Optionally, the thickness of the floating gate structure is 200 angstroms~800 angstroms.
Optionally, on channel direction, grid are wiped in the top of the first side wall relative to the bottom end direction of second sidewall
Structure recessed size in pole is 200 angstroms~400 angstroms.
Optionally, the material of the isolation film includes silica；The material of the barrier film includes silicon nitride；Described in formation
The technique of isolation film includes high temperature oxide deposition technique；The technique for forming the barrier film includes chemical vapor deposition method.
Optionally, the thickness of the separation layer is 100 angstroms~300 angstroms.
The present invention also provides a kind of memories formed using above-mentioned any one method, including：Semiconductor substrate is partly led
Body substrate includes scratching area and floating gate region, and the floating gate region is adjacent with scratching area and is located at scratching area both sides；It is served as a contrast positioned at semiconductor
Erasing gate structure on the scratching area at bottom；The floating gate structure being located on the floating gate region of semiconductor substrate, the floating boom
Pole structure has in channel direction backwards to the first side wall for wiping gate structure, and the first side wall is in planar；Positioned at floating gate knot
Side wall on structure, the side wall have in channel direction backwards to the second sidewall for wiping gate structure, and the first side wall is relative to the
Two side walls are recessed towards erasing gate structure, and the first side wall and second sidewall are discontinuous；Cover second sidewall and all the first side
The separation layer of wall.
Compared with prior art, technical scheme of the present invention has the following advantages：
Technical solution of the present invention provide memory forming method in, the separation layer for be isolated floating gate structure and
Word line structure makes floating gate structure have electronics holding capacity.Etching isolation film is until expose semiconductor substrate surface with shape
During at separation layer, the barrier layer can protect the isolation film on the first side wall surface of floating gate structure, avoid etching
The technique of isolation film reduces the thickness of the isolation film on the first side wall surface, in this way the thickness control to the isolation film on the first side wall surface
System is more accurate, meets the requirement of technological design.The first side wall of the floating gate structure includes in planar benefit：In order to
Isolation film more uniform can be attached to the surface of the first side wall.Since the first side wall is relative to second sidewall direction erasing grid
Structure is recessed, and the first side wall and second sidewall are discontinuous, therefore even if the side wall inclination angle of floating gate structure is irregular, can also
Ensure isolation film to erasing gate structure recessed, covering first of the isolation film relative to covering second sidewall of covering the first side wall
The barrier film of side wall is recessed to erasing gate structure relative to the barrier film of covering second sidewall.So that being etched back to stop
During film, the removal that is etched of the barrier film of covering the first side wall bottom is avoided to avoid barrier layer in this way behind formation barrier layer
Expose the isolation film on the first side wall surface.Therefore using barrier layer as mask etching isolation film until exposing semiconductor substrate table
During face, the isolation film on the first side wall surface will not be removed, and avoid the surface for exposing the first side wall, i.e. separation layer energy
Enough whole the first side walls of covering.To sum up, it is conducive to the progress of memory program process, improves the performance of memory.
Further, the floating gate structure is removed the floating gate of the dielectric layer and wordline bitline regions of wordline bitline regions by etching
Structural membrane and the part floating gate structural membrane of side wall bottom and formed, therefore etch floating gate structural membrane need time increase
Add, correspondingly, the fluctuation of etch period reduces.Therefore etching floating gate structural membrane end is being monitored using control etch period
In the case of point, it can more be accurately controlled size of the floating gate structure along channel direction.
Further, it is formed before side wall in the first opening, etches the floating gate structural membrane of the first open bottom, make first
The surface for the floating gate structural membrane exposed that is open is recessed；After forming floating gate structure, floating gate structure is towards side wall
Surface is recessed, so that and the top of third side wall is in wedge angle, when wiping gate structure progress erasing operation, third side
The wedge angle on wall top can reduce the channel voltage of tunneling effect so that electronics is easier from floating gate structure tunnelling to erasing grid
Pole structure improves efficiency of erasing.Secondly as needing the portion of etching removal side wall bottom during forming floating gate structure
Point floating gate structural membrane, therefore the height of the first side wall is made to be less than the height of third side wall, so make the first side wall be easier with
Semiconductor substrate keeps vertical.The first side wall is vertical with semiconductor substrate, on the one hand, makes side wall perpendicular to semiconductor substrate table
It is easier floating gate structure being completely covered by the direction in face, on the other hand, avoids the tip angle on the first side wall top too small,
The electronics when word line structure is read in floating gate structure is avoided to enter word by the wedge angle on the first side wall top
Cable architecture avoids causing electronics holding capacity in floating gate structure from declining.
Description of the drawings
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of memory forming process；
Fig. 4 to Figure 22 is the structural schematic diagram of memory forming process in one embodiment of the invention.
Specific implementation mode
As described in background, the performance for the memory that the prior art is formed is poor.
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of memory forming process.
With reference to figure 1, semiconductor substrate 100 is provided, the semiconductor substrate 100 includes scratching area X1 and floating gate region X2, institute
Floating gate region X2 is stated with scratching area X1 adjoinings and positioned at the both sides scratching area X1；Form the erasing gate structure being located on scratching area X1
130, the floating gate structure 110 on the X2 of floating gate region and the side wall in floating gate structure 110 120, floating gate are located at
Structure 110 has in channel direction backwards to the first side wall 1111 for wiping gate structure 130, and side wall 120 has in channel direction
Backwards to the second sidewall 1201 of erasing gate structure 130；In erasing gate structure 130, floating gate structure 110 and side wall 120
Outer surface and the surface of semiconductor substrate 200 form isolation film 140；Barrier film 150 is formed on 140 surface of isolation film.
With reference to figure 2, barrier film 150 is etched back to until exposing the isolation film 150 positioned at 100 surface of semiconductor substrate, shape
At the barrier layer 151 of covering the first side wall 1111 and second sidewall 1201, and between barrier layer 151 and side wall 120 and stop
There is isolation film 140 between layer 151 and floating gate structure 110.
Be mask etching isolation film 140 to 100 surface of semiconductor substrate is exposed with barrier layer 151 with reference to figure 3, make every
From the separation layer 141 that film 140 forms covering the first side wall 1111 and second sidewall 1201.
After forming the separation layer 141, the barrier layer 151 is removed.
Etching isolation film 140 is to during exposing 100 surface of semiconductor substrate to form separation layer 141, the resistance
Barrier 151 can protect the isolation film 140 on 1111 surface of the first side wall of floating gate structure 110, avoid etching isolation film 140
Technique reduces the thickness of the isolation film 140 on 1111 surface of the first side wall, in this way to the isolation film 140 on 1111 surface of the first side wall
Thickness control is more accurate.
The floating gate structure 110 is formed by etching FGS floating gate structure film, before forming floating gate structure 110, floating boom
Structural membrane is located at 100 surface of part semiconductor substrate of 120 side of bottom and side wall of side wall 120.Specifically, with side wall
120 be mask, using anisotropy dry carving technology etching FGS floating gate structure film until 100 surface of semiconductor substrate is exposed, in side
Floating gate structure 110 is formed on the bottom of wall 120.Why using anisotropy dry carving technology etch FGS floating gate structure film, be in order to
Make the first side wall 1111 at planar, the first side wall 1111 includes in planar benefit：Keep isolation film 140 more uniform
It is attached to the surface of the first side wall 1111.Above-mentioned the first side wall 1111 and second sidewall 1201 are continuous.
However, the performance for the memory that the above method is formed is poor, it has been investigated that, reason is：
With the continuous reduction of characteristic size, the thickness of floating gate structure 110 constantly reduces, correspondingly, FGS floating gate structure film
Thickness it is smaller, therefore cause the side wall inclination angle of floating gate structure 110 be easy to present it is irregular.Specifically, due to FGS floating gate structure
The thickness of film is smaller, and the time for etching FGS floating gate structure film is shorter, therefore during etching FGS floating gate structure film, it is difficult to pass through quarter
The end-point detection method for losing parameter, is removed the type of corrosion product such as the variation of etch rate, in etching or gas is put
Variation of active reaction agent etc. monitors etching terminal in electricity, usually monitors etching terminal by controlling etch period.And it needs
The time for etching FGS floating gate structure film is less, has larger fluctuation to the time of FGS floating gate structure film etching in this way.In order to facilitate saying
Bright, the etch period of technological design is the object time.In one case, mesh is less than to the real time of FGS floating gate structure film etching
The time is marked, the first side wall 1111 of floating gate structure 110 is caused to be inclined outwardly.Etch the other parameters in FGS floating gate structure membrane process
Fluctuation be also possible to cause the first side wall 1111 of floating gate structure 110 to be inclined outwardly.And the first side wall 1111 and the second side
Wall 1201 is continuous, therefore side wall 120 cannot all hide floating gate structure 110 on the direction perpendicular to semiconductor substrate surface
Lid.After forming isolation film 140, the projection of the isolation film 140 on 1111 surface of the first side wall on 100 surface of semiconductor substrate cannot be by
Projection of the side wall 120 on 100 surface of semiconductor substrate all covers.Barrier film 150 is etched back to until exposing positioned at semiconductor
The isolation film 150 on 100 surface of substrate can also expose the part isolation film 150 of the first side wall 1111.It is to cover with barrier layer 151
Film etches isolation film 140 to during exposing 100 surface of semiconductor substrate, and also the part of the first side wall 1111 can be isolated
Film 150 also removes.Cause the part surface of the first side wall 1111 that cannot be isolated the covering of film 150 and expose in this way.Subsequently
After forming word line structure, word line structure and the first side wall 1111 are directly linked together, and floating gate structure 110 is caused to lose storage
The ability of electronics.
On this basis, the present invention provides a kind of forming method of memory, forms erasing gate structure, floating gate structure
And the side wall in floating gate structure, floating gate structure and side wall are corresponding with backwards to erasing grid respectively in channel direction
The first side wall and second sidewall of structure, the first side wall are in planar, and the first side wall is relative to second sidewall direction erasing grid
Structure is recessed, and the first side wall and second sidewall are discontinuous；Erasing gate structure, floating gate structure and side face of wall and
The surface of semiconductor substrate forms isolation film, and isolation film covers the first side wall and second sidewall；Resistance is formed on the surface of isolation film
Keep off film；Barrier film is etched back to the isolation film exposed positioned at semiconductor substrate surface, forms covering the first side wall and the second side
The barrier layer of wall；Using barrier layer as mask etching isolation film until exposing semiconductor substrate surface, covering the first side wall is formed
With the separation layer of second sidewall；Barrier layer is removed later.The method improves the performance of memory.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 17 is the structural schematic diagram of memory forming process in one embodiment of the invention.
With reference to figure 4, semiconductor substrate 200 is provided, semiconductor substrate 200 includes scratching area A1 and floating gate region A2, described floating
Grid region A2 and scratching area A1 is adjacent and is located at the both sides scratching area A1.
In the present embodiment, the memory is flash memory.
The semiconductor substrate 200 provides technique platform to form memory.
The semiconductor substrate 200 includes erasing floating gate area A and several wordline bitline regions B, and erasing floating gate area A includes erasing
Area A1 and floating gate region A2, the erasing floating gate area A are abutted between adjacent wordline bitline regions B and with wordline bitline regions B, from
The direction of erasing floating gate area A to wordline bitline regions B being oriented parallel to from scratching area A1 to floating gate region A2.
The material of the semiconductor substrate 200 can be silicon, germanium or SiGe.The semiconductor substrate 200 can be with
It is silicon-on-insulator (SOI), germanium on insulator (GeOI) or germanium on insulator SiClx (SiGeOI).It is described in the present embodiment
The material of semiconductor substrate 200 is monocrystalline silicon.
Then, formed be located on the scratching area A1 erasing gate structure, the floating gate that is located on the A2 of floating gate region
Structure and the side wall in floating gate structure, the floating gate structure have in channel direction backwards to erasing gate structure
The first side wall, the side wall has in channel direction backwards to the second sidewall for wiping gate structure, the first side wall in planar,
The first side wall is recessed towards erasing gate structure relative to second sidewall, and the first side wall and second sidewall are discontinuous.
Introduced below with reference to Fig. 5 to Figure 18 to be formed erasing gate structure, floating gate structure and side wall method.
In conjunction with being schematic diagram on the basis of Fig. 4 with reference to figure 5, Fig. 6 and Fig. 7, Fig. 5, Fig. 6 is along cutting line M-N in Fig. 5
Sectional view, Fig. 7 be along Fig. 5 cutting line M1-N1 schematic diagram, in the part floating boom of scratching area A1 and semiconductor substrate 200
Floating gate structural membrane 210 is formed on scratching area A, and the floating gate structural membrane 210 on erasing floating gate area A is also extended to and partly led
On the wordline bitline regions B of body substrate 200.
Region where floating gate structural membrane 210 corresponds to the position of active area.
In the present embodiment, further include：It is also formed during forming floating gate structural membrane 210 and is located at part semiconductor lining
Substrate separation layer 220 in bottom 200.The material of the substrate separation layer 220 is silica.
Specifically, forming initial floating boom knot on the erasing floating gate area A and several wordline bitline regions B of semiconductor substrate 200
Structure film (not shown)；The first mask layer (not shown) is formed on initial FGS floating gate structure film；Graphical first mask
Material layer, initial FGS floating gate structure film and part semiconductor substrate 200 form floating gate structure in the semiconductor substrate 200
Film 210 and the first mask layer in floating gate structural membrane 210, are formed simultaneously groove, and the groove is located at floating gate structure
Between film 210, between the first mask layer and in part semiconductor substrate 200；Substrate separation layer is formed in the trench
220；After forming substrate separation layer 220, first mask layer is removed.The initial FGS floating gate structure film corresponds to floating gate structural membrane
210, the first mask layer corresponds to the first mask layer.
The floating gate structural membrane 210 includes floating gate oxide film and the floating boom film in floating gate oxide film.The floating boom
Oxidation film be located on scratching area A1 and the part erasing floating gate area A of semiconductor substrate 200 on, and on the erasing floating gate area A
Floating gate oxide film also extends on the wordline bitline regions B of semiconductor substrate 200.
In conjunction with reference to figure 8 and Fig. 9, Fig. 8 is schematic diagram on the basis of Fig. 5, and Fig. 9 is the schematic diagram on Fig. 6, and Fig. 9
For the sectional view of the cutting line M-N along Fig. 8, several discrete Jie are formed in floating gate structural membrane 210 and semiconductor substrate 200
There is between adjacent dielectric layer 230 matter layer 230 first opening 231, the first opening 231 to be located on the A2 of floating gate region and not extend
To scratching area A1 and wordline bitline regions B.
Specifically, forming several discrete dielectric layers in part floating gate structural membrane 210 and section substrate separation layer 220
230.The bottom-exposed of first opening 231 goes out the substrate separation layer 220 of floating gate region A2 and the floating gate structural membrane of floating gate region A2
210。
The material of the dielectric layer 230 includes silicon nitride or silicon oxynitride.
The method for forming the dielectric layer 230 includes：It is formed and is situated between in floating gate structural membrane 210 and substrate separation layer 220
Plasma membrane (not shown)；Patterned second mask layer is formed on deielectric-coating, the second mask layer covers the medium of wordline bitline regions B
The deielectric-coating of film and scratching area A1 and the deielectric-coating for exposing floating gate region A2；Using the second mask layer as mask etching deielectric-coating, make
Deielectric-coating forms dielectric layer 230；The second mask layer is removed later.
In conjunction with being schematic diagram on the basis of Fig. 8 with reference to figure 10 and Figure 11, Figure 10, Figure 11 is signal on the basis of Fig. 9
Figure forms side wall 240 in first 231 (in conjunction with reference to figure 8 and Fig. 9) of opening.
The material of the side wall 240 is silica or silicon oxynitride.The material of the material and dielectric layer 230 of the side wall 240
Material is different.
Formed side wall 240 method include：Side wall film (not shown) is formed in an opening 231 and on dielectric layer 230；
The side wall film is planarized until exposing the surface of dielectric layer 230, forms side wall 240.
In the present embodiment, further include：Before side wall 240 being formed in the first opening 231,231 bottoms of the first opening of etching
Floating gate structural membrane 210, keep the surface for the floating gate structural membrane 210 that the first opening 231 exposes recessed.In other realities
It applies in example, is formed before side wall in the first opening, the floating gate structural membrane of the first open bottom is not etched, correspondingly, first
The surface for the floating gate structural membrane exposed that is open is in plane.
In conjunction with being schematic diagram on the basis of Figure 10 with reference to figure 12 and Figure 13, Figure 12, Figure 13 is showing on the basis of Figure 11
It is intended to, after forming side wall 240, removes the floating gate structural membrane 210 on the dielectric layer 230 and scratching area A1 on scratching area A1,
The second opening 232 is formed in dielectric layer 230, second opening 232 also extends in floating gate structural membrane 210, the second opening
232 bottom-exposed goes out semiconductor substrate 200.
The technique for removing the floating gate structural membrane 210 on the dielectric layer 230 and scratching area A1 on scratching area A1 is etching work
Skill, such as dry carving technology or wet-etching technique.
The bottom-exposed of second opening 232 goes out the surface of 200 scratching area A1 of semiconductor substrate.
In conjunction with being schematic diagram on the basis of Figure 12 with reference to figure 14 and Figure 15, Figure 14, Figure 15 is showing on the basis of Figure 13
It is intended to, source region 262 is formed in the semiconductor substrate 200 of the second 232 bottoms of opening.
The technique for forming source region 262 is ion implantation technology.
In conjunction with being schematic diagram on the basis of Figure 14 with reference to figure 16 and Figure 17, Figure 16, Figure 17 is showing on the basis of Figure 15
It is intended to, forms erasing gate structure 250 in the second opening 232.
The source region 262 is located in the semiconductor substrate 200 of 250 bottom of erasing gate structure.
The erasing gate structure 250 includes erasing gate dielectric layer 251 and the erasing grid on erasing gate dielectric layer 251
Pole 252.Wherein, erasing gate dielectric layer 251 is located at side wall and the bottom of the second opening 232.Erasing gate dielectric layer 251 material be
The material of silica, erasing grid 252 is polysilicon.
With reference to figure 18, Figure 18 is schematic diagram on the basis of Figure 17, after forming erasing gate structure 250, etching removal word
The part floating boom of the dielectric layer 230 of line bitline regions B and 240 bottom of floating gate structural membrane 210 and side wall of wordline bitline regions B
Pole structural membrane 210 forms floating gate structure 211 in the bottom of side wall 240.
The floating gate structure 211 has in channel direction backwards to the first side wall 2111 for wiping gate structure 250, described
Side wall 240 has in channel direction backwards to the second sidewall 2401 for wiping gate structure 250, the first side wall 2111 in planar,
The first side wall 2111 is recessed relative to second sidewall 2401 towards erasing gate structure 250, the first side wall 2111 and second sidewall
2401 is discontinuous.
The floating gate structure 211 is located on the part floating gate region A2 of the semiconductor substrate 200.
The floating gate structure 211 includes floating gate dielectric layer and the floating boom on floating gate dielectric layer.The floating gate dielectric
Layer is formed by the floating gate oxide layers, and the floating boom is formed by the floating boom film.
The first side wall 2111 is in planar, enables follow-up isolation film is more uniform to be attached to the first side wall 2111.Make
The first side wall 2111 is in planar, needs that anisotropy dry carving technology is used to etch floating gate structural membrane 210 to form floating gate
Structure 211.
The floating gate structure 211 also has the third side wall towards erasing gate structure 250.
The thickness of the floating gate structure 211 is 200 angstroms~800 angstroms.If the thickness of floating gate structure 211 is excessive, meeting
Cause erasable voltage excessive, and reduces erasable efficiency.
The floating gate structure 211 is removed the floating boom of the dielectric layer 230 and wordline bitline regions B of wordline bitline regions B by etching
The part floating gate structural membrane 210 of 240 bottom of pole structural membrane 210 and side wall and formed, therefore etch floating gate structural membrane 210
The time needed increases, correspondingly, the fluctuation of etch period reduces.Therefore it is being floated using control etch period to monitor etching
In the case of the terminal of gate structure film 210, it can more be accurately controlled size of the floating gate structure 211 along channel direction.
In the present embodiment, since the surface of floating gate structural membrane 210 that the first opening 231 exposes is recessed,
After forming floating gate structure 211, the surface of floating gate structure 211 towards side wall 240 is recessed, the floating gate structure 211
Fringe region thickness be more than floating gate structure 211 intermediate region thickness, so that the top of third side wall in point
Angle, when wiping the progress erasing operation of gate structure 250, the wedge angle on third side wall top can reduce the channel electricity of tunneling effect
Pressure so that electronics is easier, from 211 tunnelling of floating gate structure to erasing gate structure 250, to improve efficiency of erasing.
In other embodiments, the top surface of floating gate structure 211 and sidewall surfaces are vertical, the top of third side wall without
Wedge angle.
Secondly as needing the part floating boom of 240 bottom of etching removal side wall during forming floating gate structure 211
Pole structural membrane 210, therefore the height of the first side wall 2111 is made to be less than the height of third side wall, and then the first side wall 2111 is made more to hold
Easily keep vertical with semiconductor substrate 200.The first side wall 2111 is vertical with semiconductor substrate 200, on the one hand, side wall 240 is made to exist
It is easier floating gate structure 211 being completely covered by the direction on 200 surface of semiconductor substrate, on the other hand, avoids the
The tip angle on 2111 top of one side wall is too small, avoids the electricity in floating gate structure 211 when word line structure is read
Son enters word line structure by the wedge angle on the first side wall top, avoids causing in floating gate structure 211 under electronics holding capacity
Drop.
On channel direction, grid knot is wiped in the top of the first side wall 2111 relative to the bottom end direction of second sidewall 2401
The recessed size of structure 250 is 200 angstroms~400 angstroms.If on channel direction, the top of the first side wall 2111 is relative to second sidewall
2401 bottom end is more than 400 angstroms towards the recessed size of erasing gate structure 250, causes floating gate structure 211 in channel direction
On it is undersized, lead to be unfavorable for the progress of programming；If on channel direction, the top of the first side wall 2111 is relative to second
The bottom end of side wall 2401 is less than 200 angstroms towards the recessed size of erasing gate structure 250, if the first side wall 1111 is inclined outwardly,
Side wall 240 is higher in the risk for exposing 211 part of floating gate structure in 200 surface direction of semiconductor substrate.
In the present embodiment, the floating gate structural membrane of the dielectric layer 230 and wordline bitline regions B of etching removal wordline bitline regions B
210 and 240 bottom of side wall part floating gate structural membrane 210 technique be anisotropy dry carving technology, the anisotropy
The parameter of dry carving technology includes：The gas of use includes HBr, He, O2And Cl2, the flow of HBr is 80sccm~150sccm, He
And O2Total flow be 3sccm~8sccm, O2In He and O2Total flow in molar percentage be 28%~32%, Cl2's
Flow is 5sccm~15sccm, and source radio-frequency power is 200 watts~300 watts, and bias voltage is 200 volts~300 volts, chamber pressure
For 5mtorr~20mtorr.
In the prior art, in order to keep the first side wall and second sidewall continuous, each to different of the technique of FGS floating gate structure film is etched
Property is stronger, and the first side wall and the continuous purpose of second sidewall are desirable to directly define floating boom along the width of channel direction using side wall
The width of pole structure.
It is each in forming anisotropy dry carving technology that floating gate structure 211 uses compared with prior art in the present embodiment
The anisotropic degree of anisotropy dry carving technology is weaker, specifically, increasing a small amount of Cl2So that isotropic etching effect increases
By force so that the first side wall 2111 is recessed towards erasing gate structure 250 relative to second sidewall 2401, and can ensure the first side
Wall 2111 is in planar.
In above-mentioned parameter, changes other parameters and be not easy to make the first side while making the first side wall 2111 be in planar
Wall 2111 is recessed towards erasing gate structure 250 relative to second sidewall 2401.And Cl2Content be also required to stringent control,
Cl2Content only can just have said effect in above-mentioned range of flow.
In the present embodiment, even if can be more accurately controlled if the first side wall 2111 and discontinuous second sidewall 2401 floating
Size of the gate structure 211 along channel direction.
With reference to figure 19, in the erasing gate structure 250, outer surface, the Yi Jiban of floating gate structure 211 and side wall 240
The surface of conductor substrate 200 forms isolation film 270, and the isolation film 270 covers the first side wall 2111 and second sidewall 2401.
The material of the isolation film 270 includes silica.
The technique for forming the isolation film 270 is depositing operation, such as high temperature oxide deposition technique (HTO).
In the present embodiment, the technique for forming the isolation film 270 is high temperature oxide deposition technique, and benefit includes：It is this
Technique has good step coverage, even if the first side wall 2111 is inwardly recessed relative to second sidewall 2401, isolation film 270
Still it can be very good to be covered in 2111 surface of the first side wall.
The isolation film 270 is used to form separation layer.
9 are continued to refer to figure 1, barrier film 280 is formed on the surface of the isolation film 270.
In the present embodiment, barrier film 280 is formed in the whole surface of isolation film 270.
The material of the barrier film 280 includes silicon nitride.The barrier film 280 is used to form barrier layer.
The technique for forming the barrier film 280 is depositing operation, such as chemical vapor deposition method.
In the present embodiment, due to second sidewall 2401 of the first side wall 2111 relative to side wall 240 of floating gate structure 211
It is recessed towards erasing gate structure 250, and the first side wall 2111 and second sidewall 2401 are discontinuous, therefore even if floating gate structure
211 side wall inclination angle is irregular, it is also ensured that the isolation film of covering the first side wall 2111 is relative to covering second sidewall 2401
Isolation film 270 it is recessed to erasing gate structure 250, cover the barrier film 280 of the first side wall 2111 relative to covering the second side
The barrier film 280 of wall 2401 is recessed to erasing gate structure 250.
With reference to figure 20, the barrier film 280 (with reference to figure 19) is etched back to until exposing positioned at 200 surface of semiconductor substrate
Isolation film 270, form the barrier layer 281 of covering the first side wall 2111 and second sidewall 2401, and the barrier layer 281 and side
There is isolation film 270 between wall 2111 and between barrier layer 281 and floating gate structure 211.
The technique for being etched back to the barrier film 280 includes anisotropy dry carving technology.
Due to the first side wall 2111 barrier film 280 relative to second sidewall 2401 barrier film 280 to erasing grid knot
Structure 250 is recessed, so that during being etched back to barrier film 280, avoids the barrier film of 2111 bottom of covering the first side wall
280 are etched removal, after forming barrier layer 281 in this way, barrier layer 281 are avoided to expose the isolation film on 2111 surface of the first side wall
280。
With reference to figure 21, with the barrier layer 281 for mask etching isolation film 270 until exposing 200 table of semiconductor substrate
Face makes the isolation film 270 form the separation layer 271 of covering the first side wall 2111 and second sidewall 2401.
The effect of the separation layer 271 includes：Floating gate structure 211 and word line structure is isolated, floating gate structure 211 is made to have
There is electronics holding capacity.
During etching isolation film 270 to form separation layer 271, the barrier layer 281 can protect the first side wall
The isolation film 270 on 2111 surfaces avoids the technique of etching isolation film 270 from reducing the isolation film 270 on the surface of the first side wall 2111
Thickness, it is more accurate to the thickness control of the isolation film 270 on 2111 surface of the first side wall in this way.Specifically, when deposition is formed
Isolation film 270 thickness be first thickness when, also can guarantee separation layer 271 thickness be first thickness.
During etching isolation film 270 to form separation layer 271, the isolation film 270 on 2111 surface of the first side wall is not
It can be removed, avoid the surface for exposing the first side wall 2111, i.e. separation layer 271 that from capable of covering whole the first side walls 2111.It is comprehensive
On, it is conducive to the progress of memory program process, improves the performance of memory.
Due to thickness being affected to the performance of memory device of separation layer 271, the thickness of separation layer 271 it is excessive or
It is too small that the performance of memory is had adverse effect on, therefore the thickness for being accurately controlled separation layer 271 is stored for improving
The performance of device has great importance.
In the present embodiment, the thickness of the separation layer 271 is 100 angstroms~300 angstroms.The thickness of the separation layer 271 selects
The meaning of this range is：If the thickness of separation layer 271 is excessive, cause under the raceway groove and word line structure under floating gate structure 211
Raceway groove connection resistance it is excessive, influence device reading performance；And when programming, floating gate structure 211 is served as a contrast with semiconductor herein
Electric field between bottom causes programming efficiency to reduce as separation layer thickness is excessive and reduces；If the thickness mistake of separation layer 271
It is small, lead to the reduction of electronics holding capacity.
With reference to figure 22, after forming the separation layer 271, remove the barrier layer 281 (with reference to figure 21).
Etching removal barrier layer 281.In the present embodiment, barrier layer 281 or isotropism are removed using wet-etching technology
Dry carving technology removes barrier layer 281.
In the present embodiment, further include：Word line structure, and 211, floating gate structure are formed in the side wall of the separation layer 271
Between word line structure and erasing gate structure 250.
In the present embodiment, the programming process of memory is injected using the thermoelectron of source to carry out.The erase process of memory
Utilize tunneling effect.In erase process, electronics is tunneled through erasing gate dielectric layer 251 from floating gate structure 211 and enters erasing
In grid.
Correspondingly, the present embodiment also provides a kind of memory formed using the above method, 2 are please referred to Fig.2, including：Half
Conductor substrate 200, semiconductor substrate 200 include scratching area A1 and floating gate region A2, the floating gate region A2 and scratching area A1 it is adjacent and
Positioned at the both sides scratching area A1；Erasing gate structure 250 on the scratching area A1 of semiconductor substrate 200；It is located at and partly leads
Floating gate structure 211 on the floating gate region A2 of body substrate 200, the floating gate structure 211 have in channel direction backwards to erasing
The first side wall 2111 of gate structure 250, the first side wall 2111 is in planar；Side wall 240 in floating gate structure 211,
The side wall 240 channel direction have backwards to wipe gate structure 250 second sidewall 2401, the first side wall 2111 relative to
Second sidewall 2401 is recessed towards erasing gate structure 250, and the first side wall 2111 and second sidewall 2401 are discontinuous；Covering second
The separation layer 271 of side wall 2401 and whole the first side walls 2111.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of memory, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes scratching area and floating gate region, the floating gate region it is adjacent with scratching area and
Positioned at scratching area both sides；
It forms the erasing gate structure being located on the scratching area, the floating gate structure being located on floating gate region and is located at
Side wall in floating gate structure, the floating gate structure have in channel direction backwards to the first side wall for wiping gate structure, institute
Stating side wall has in channel direction backwards to the second sidewall for wiping gate structure, and the first side wall is in planar, and the first side wall is opposite
Recessed towards erasing gate structure in second sidewall, the first side wall and second sidewall are discontinuous；
It is formed and is isolated on the erasing gate structure, floating gate structure and the surface of side face of wall and semiconductor substrate
Film, and isolation film covering the first side wall and second sidewall；
Barrier film is formed on the surface of the isolation film；
The barrier film is etched back to until exposing isolation film positioned at semiconductor substrate surface, forms covering the first side wall and the
The barrier layer of two side walls, and there is isolation film between the barrier layer and side wall and between barrier layer and floating gate structure；
Using the barrier layer as mask etching isolation film until exposing semiconductor substrate surface, the isolation film is made to form covering
The separation layer of the first side wall and second sidewall；
After forming the separation layer, the barrier layer is removed.
2. the forming method of memory according to claim 1, which is characterized in that the scratching area and the floating gate region structure
At erasing floating gate area；The semiconductor substrate further includes several wordline bitline regions, and the erasing floating gate area is located at adjacent wordline
It is abutted between bitline regions and with wordline bitline regions, from being oriented parallel to from scratching area to floating for erasing floating gate area to wordline bitline regions
The direction in grid region；
Forming the method for wiping gate structure, floating gate structure and side wall includes：In the portion of scratching area and semiconductor substrate
Divide and form floating gate structural membrane in erasing floating gate area, and the floating gate structural membrane in erasing floating gate area also extends to semiconductor
On the wordline bitline regions of substrate；Several discrete dielectric layers, adjacent Jie are formed in floating gate structural membrane and semiconductor substrate
There is the first opening, the first opening to be located on floating gate region and not extend on scratching area and wordline bitline regions between matter layer；
Side wall is formed in one opening；After forming side wall, the floating gate structural membrane on the dielectric layer and scratching area on scratching area is removed, is being situated between
The second opening is formed in matter layer, second opening also extends in floating gate structural membrane, and the bottom-exposed of the second opening goes out half
Conductor substrate；Erasing gate structure is formed in the second opening；After forming erasing gate structure, etching removal wordline bitline regions
The part floating gate structural membrane of the floating gate structural membrane and side wall bottom of dielectric layer and wordline bitline regions, in the bottom of side wall
Form the floating gate structure.
3. the forming method of memory according to claim 2, which is characterized in that further include：Forming the erasing grid
Before the structure of pole, source region is formed in the semiconductor substrate of second open bottom；After forming the erasing gate structure, institute
Source region is stated to be located in the semiconductor substrate of the erasing gate structure bottom.
4. the forming method of memory according to claim 2, which is characterized in that the medium of etching removal wordline bitline regions
The technique of the part floating gate structural membrane of the floating gate structural membrane and side wall bottom of layer and wordline bitline regions includes anisotropy
The parameter of dry carving technology, the anisotropy dry carving technology includes：The gas of use includes HBr, He, O2And Cl2, the flow of HBr
For 80sccm~150sccm, He and O2Total flow be 3sccm~8sccm, O2In He and O2Total flow in Mole percent
Than for 28%~32%, Cl2Flow be 5sccm~15sccm, source radio-frequency power is 200 watts~300 watts, and bias voltage is
200 volts~300 volts, chamber pressure is 5mtorr~20mtorr.
5. the forming method of memory according to claim 2, which is characterized in that further include：It is formed in the first opening
Before side wall, the floating gate structural membrane of the first open bottom is etched, makes the surface for the floating gate structural membrane that the first opening exposes
It is recessed；After forming the floating gate structure, the surface of floating gate structure towards the side wall is recessed, the floating gate
Also there is structure the third side wall towards erasing gate structure, the height of the first side wall to be less than the height of third side wall；Institute
The first side wall is stated perpendicular to the surface of the semiconductor substrate.
6. the forming method of memory according to claim 1, which is characterized in that the thickness of the floating gate structure is
200 angstroms~800 angstroms.
7. the forming method of memory according to claim 1, which is characterized in that on channel direction, first side
The top of wall is 200 angstroms~400 angstroms relative to the size that the bottom end of second sidewall is recessed towards erasing gate structure.
8. the forming method of memory according to claim 1, which is characterized in that the material of the isolation film includes oxidation
Silicon；The material of the barrier film includes silicon nitride；
The technique for forming the isolation film includes high temperature oxide deposition technique；The technique for forming the barrier film includes chemical gas
Phase depositing operation.
9. the forming method of memory according to claim 1, which is characterized in that the thickness of the separation layer is 100 angstroms
~300 angstroms.
10. a kind of memory formed according to claim 1 to 9 any one method, which is characterized in that including：
Semiconductor substrate, semiconductor substrate include scratching area and floating gate region, and the floating gate region is adjacent with scratching area and positioned at erasing
Area both sides；
Erasing gate structure on the scratching area of semiconductor substrate；
The floating gate structure being located on the floating gate region of semiconductor substrate, the floating gate structure have backwards in channel direction
The first side wall of gate structure is wiped, the first side wall is in planar；
Side wall in floating gate structure, the side wall have in channel direction backwards to the second sidewall for wiping gate structure,
The first side wall is recessed towards erasing gate structure relative to second sidewall, and the first side wall and second sidewall are discontinuous；
Cover the separation layer of second sidewall and whole the first side walls.
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