CN102760737A - Floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device. A memory cell of the EEPROM device comprises a memory transistor and a selection transistor, wherein the memory transistor comprises a floating gate positioned at the lower part and a control gate positioned at the upper part; and a dielectric layer is arranged between the floating gate and the control gate, and is in a curved surface shape. The invention further discloses a manufacturing method of the device, which mainly comprises the step that the floating gate is subjected to shallow trench etching, so that the dielectric layer is in the concave curved surface shape. Compared with the traditional flat dielectric layer, the capacitance area is increased; and the increased capacitance is proportional to the depth of a shallow trench, so that the voltage coupling efficiency and the coupled voltage are increased, and the area of the existing device can be kept or even reduced.

Description

Floating gate type EEPROM device and manufacturing approach thereof

Technical field

The present invention relates to a kind of NVM (non volatile memory; Nonvolatile memory) device; Particularly relate to a kind of EEPROM (Electrically Erasable Programmable Read OnlyMemory, Electrically Erasable Read Only Memory) device.

Background technology

For obtaining more high-performance and more large storage capacity, embedded NVM hopes that the area of memory cell is more little good more.Embedded NVM technical development mainly contains floating boom (floating gate), dividing potential drop grid (split gate) and three kinds of technology of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon oxide nitride oxide silicon) so far.Floating gate type NVM has the more advantage of high data retention ability with respect to other technologies, but faces difficulty in size aspect reducing.This be since the size of floating boom own reduce to cause reducing of media area between floating boom and the control gate, just coupling capacitance reduces, thus this can make the voltage coupling efficiency reduce device performance.

See also Fig. 1, this is the memory cell of floating gate type EEPROM, comprises a memory transistor 1a and a selection transistor 1b.These two transistors are manufactured all on substrate 10 and the gate oxide 11, and a shared heavy-doped source drain region 10a.Said memory transistor 1a is a floating boom tunnel oxidation layer transistor (FLOTOX; FLOating gate Tunnel OXide; Sometimes abbreviate the floating boom transistor as); Comprise the multi-crystal silicon floating bar 12 that is positioned at the below and 14 two grids of polysilicon control grid that are positioned at the top, these two grids 12, have dielectric layer 13 isolated between 14.Said dielectric layer 13 is rendered as flat shape.Said gate oxide 11 has a fraction of thickness thinner in the zone of memory transistor 1a, is called tunnel oxide 11a.

In the floating gate type EEPROM device, tunnelling current and electric field strength exponent function relation.Owing to consider the cavity (pin-hole fromplasma damage) that data holding ability (data retention) and plasma wound form, the thickness basic controlling of floating gate type EEPROM tunnel oxide is difficult at reduce again.So obtain high electric field, just need the voltage of tunnel oxide to want high.And the voltage that is applied on the tunnel oxide is the effective voltage of floating boom coupling, and coupling coefficient comprises to be wiped COEFFICIENT K e and write COEFFICIENT K w.

$\mathrm{Ke}=\frac{\mathrm{Cpp}}{\mathrm{Cox}+\mathrm{Ctun}+\mathrm{Cpp}}$

$\mathrm{Kw}=1-\frac{\mathrm{Ctun}}{\mathrm{Cpp}+\mathrm{Cgox}+\mathrm{Ctun}}$

Wherein Cpp is an electric capacity between two-layer polysilicon, and Cox is a gate oxide electric capacity, and Ctun is the tunnel oxide layer capacitance.No matter wipe or write, increase Cpp and can both increase coupling coefficient, so it is extremely important for improving tunnelling voltage and then improving electric field strength to increase Cpp, one of mode that increases Cpp is exactly the media area that increases between floating boom and the control gate.This just makes existing floating gate type EEPROM be faced with to reduce size and the contradiction situation that improves performance.

Summary of the invention

Technical problem to be solved by this invention provides a kind ofly can reduce size, can improve the floating gate type EEPROM device of performance again.For this reason, the present invention also will provide the manufacturing approach of said floating gate type EEPROM.

For solving the problems of the technologies described above; The memory cell of floating gate type EEPROM device of the present invention comprises a memory transistor and a selection transistor; Memory transistor wherein comprises floating boom that is positioned at the below and the control gate that is positioned at the top; One deck medium is arranged between said floating boom and control gate, and said dielectric layer is rendered as curve form.

Further, said dielectric layer is rendered as recessed groove shape.

The manufacturing approach of said floating gate type EEPROM device comprises the steps:

In the 1st step, the ion that silicon substrate is carried out p type impurity injects, and forms the p trap;

In the 2nd step, adopt ion implantation technology in the p trap, to form n type heavily doped region, as memory transistor and the transistorized source and drain of selection;

The 3rd step; At p trap superficial growth one deck silica as gate oxide; On gate oxide, form tunneling window with photoetching and etching technics, regrowth one deck tunnel oxide on the p trap in this tunneling window then, the thickness of tunnel oxide is thinner than gate oxide;

The 4th step deposited first polysilicon layer as floating boom with chemical vapor deposition method on gate oxide and tunnel oxide, when deposition or after the deposition, first polysilicon layer is carried out the doping of n type impurity;

The 5th step, first polysilicon layer is carried out the shallow trench etching technics, form a groove;

In the 6th step, deposit one deck medium at silicon chip surface with chemical vapor deposition method;

In the 7th step, on dielectric layer, deposit second polysilicon layer as control gate with chemical vapor deposition method again;

In the 8th step, with photoetching and etching technics second polysilicon layer, dielectric layer and first polysilicon layer are carried out etching, thereby form memory transistor respectively and select transistor.

Floating gate type EEPROM device of the present invention and manufacturing approach thereof are mainly utilized floating boom are carried out the shallow trench etching; Make dielectric layer present recessed curve form; The dielectric layer increase capacity area of traditional flat shape of comparing; The electric capacity that increases is directly proportional with the degree of depth of shallow trench, thereby increases voltage coupling efficiency (coupling ratio) and coupled voltages, and can keep existing device area even reduction of device area.

Description of drawings

Fig. 1 is the memory cell structure sketch map of existing floating gate type EEPROM;

Fig. 2 is the memory cell structure sketch map of floating gate type EEPROM of the present invention.

Description of reference numerals among the figure:

1a is a memory transistor; 1b is for selecting transistor; 10 is silicon substrate; The 10a doped source drain region of attaching most importance to; 11 is gate oxide; 11a is a tunnel oxide; 12 is multi-crystal silicon floating bar; 13 is dielectric layer; 14 is polysilicon control grid.

Embodiment

See also Fig. 2, this is a specific embodiment of floating gate type EEPROM device of the present invention.Wherein, each memory cell all comprises a memory transistor 1a and a selection transistor 1b, and these two transistors are manufactured all on substrate 10 and the gate oxide 11, and a shared heavy-doped source drain region 10a.Said memory transistor 1a is a floating boom transistor, comprises the multi-crystal silicon floating bar 12 that is positioned at the below and 14 two grids of polysilicon control grid that are positioned at the top, these two grids 12, has dielectric layer 13 isolated between 14.Said gate oxide 11 has a fraction of thickness thinner in the zone of memory transistor 1a, is called tunnel oxide 11a.

As shown in Figure 1, in the existing floating gate type EEPROM device, the upper and lower surfaces of dielectric layer 13 is smooth flat shape.Floating boom 12 contacts with the lower surface of dielectric layer 13, and this contact-making surface also is smooth plane; Control gate 14 contacts with the upper surface of dielectric layer 13, and this contact-making surface also is smooth plane.

As shown in Figure 2, in the floating gate type EEPROM device of the present invention, dielectric layer 13 integral body demonstrate curve form, particularly are recessed groove structures, and its upper and lower surface is recessed polyhedron.Floating boom 12 contacts with the lower surface of dielectric layer 13, and this contact-making surface also is recessed polyhedron; Control gate 14 contacts with the upper surface of dielectric layer 13, and this contact-making surface also is recessed polyhedron.

The present invention passes through the shape of the dielectric layer 13 of this ingenious design just; Make in the coupling capacitance that can improve under the prerequisite that does not change floating boom 12 sizes between floating boom 12 and the control gate 14; More can be in the coupling capacitance that still improves under the prerequisite of dwindling floating boom 12 sizes between floating boom 12 and the control gate 14, this has just thoroughly solved floating gate type EEPROM device to small size and high performance requirement simultaneously.

Introduce the manufacturing approach of floating gate type EEPROM according to the invention below with a concrete embodiment, comprise the steps:

In the 1st step, the ion that silicon substrate 10 is carried out p type impurity injects, and forms p trap 10.

In the 2nd step, adopt ion implantation technology in p trap 10, to form n type heavily doped region 10a, as memory transistor 1a and the source and drain of selecting transistor 1b.

The 3rd step; At p trap 10 Film by Thermal Oxidation one deck silica as gate oxide 11; On gate oxide 11, form tunneling window (bottom is a p trap 10) with photoetching and etching technics; Regrowth one deck tunnel oxide 11a on the p trap 10 in this tunneling window then; The thickness of tunnel oxide is thinner than gate oxide, and the thickness of tunnel oxide 11a for example is

The 4th step; With chemical vapor deposition (CVD) technology deposition first polysilicon layer on gate oxide 11 and tunnel oxide 11a; Be used as floating boom 12, deposit thickness for example carries out the doping of n type impurity to first polysilicon layer for when deposition or after the deposition.

The 5th step; First polysilicon layer is carried out shallow trench etching (STI) technology; Form a groove, the degree of depth of this groove for example is

The 6th step; Deposit one deck spacer medium 13 with chemical vapor deposition method at silicon chip surface; Spacer medium 13 for example is ONO (silica-silicon-nitride and silicon oxide) layer, and thickness for example is about

.Specifically, is sequentially deposited silicon oxide

silicon nitride

silica

The 7th step; On dielectric layer 13, deposit second polysilicon layer with chemical vapor deposition method again; Be used as control gate 14, deposit thickness for example is

In the 8th step, with photoetching and etching technics second polysilicon layer, dielectric layer 13 and first polysilicon layer are carried out etching, thereby form memory transistor 1a respectively and select transistor 1b.

Above embodiment is the exemplary illustration to technical scheme according to the invention, should not be construed as the concrete restriction to technical scheme according to the invention.The technological means that persons skilled in the art are known be equal to replacement, concrete parameter adjustment etc., all should be regarded as within protection scope of the present invention.

Claims (8)

1. floating gate type EEPROM device; Its memory cell comprises a memory transistor and a selection transistor; Memory transistor wherein comprises floating boom that is positioned at the below and the control gate that is positioned at the top; One deck medium is arranged between said floating boom and control gate, it is characterized in that, said dielectric layer is rendered as curve form.

2. floating gate type EEPROM device according to claim 1 is characterized in that said dielectric layer is rendered as recessed groove shape.

3. the manufacturing approach of floating gate type EEPROM device as claimed in claim 1 is characterized in that, comprises the steps:

In the 1st step, the ion that silicon substrate is carried out p type impurity injects, and forms the p trap;

In the 2nd step, adopt ion implantation technology in the p trap, to form n type heavily doped region, as memory transistor and the transistorized source and drain of selection;

The 3rd step; At p trap superficial growth one deck silica as gate oxide; On gate oxide, form tunneling window with photoetching and etching technics, regrowth one deck tunnel oxide on the p trap in this tunneling window then, the thickness of tunnel oxide is thinner than gate oxide;

The 4th step deposited first polysilicon layer as floating boom with chemical vapor deposition method on gate oxide and tunnel oxide, when deposition or after the deposition, first polysilicon layer is carried out the doping of n type impurity;

The 5th step, first polysilicon layer is carried out the shallow trench etching technics, form a groove;

In the 6th step, deposit one deck medium at silicon chip surface with chemical vapor deposition method;

In the 7th step, on dielectric layer, deposit second polysilicon layer as control gate with chemical vapor deposition method again;

In the 8th step, with photoetching and etching technics second polysilicon layer, dielectric layer and first polysilicon layer are carried out etching, thereby form memory transistor respectively and select transistor.

4. the manufacturing approach of floating gate type EEPROM device according to claim 3; It is characterized in that; Said method is in the 3rd step, and the thickness of tunnel oxide is

5. the manufacturing approach of floating gate type EEPROM device according to claim 3; It is characterized in that; Said method is in the 4th step, and the deposit thickness of first polysilicon layer is

6. the manufacturing approach of floating gate type EEPROM device according to claim 3; It is characterized in that; Said method is in the 5th step, and the degree of depth of groove is

7. the manufacturing approach of floating gate type EEPROM device according to claim 3; It is characterized in that; Said method is in the 6th step; Spacer medium is ONO (silica-silicon-nitride and silicon oxide) layer, and thickness is

8. the manufacturing approach of floating gate type EEPROM device according to claim 3; It is characterized in that; Said method is in the 7th step, and the deposit thickness of second polysilicon layer is

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