CN106783865A - A kind of preparation method of memory cell - Google Patents
A kind of preparation method of memory cell Download PDFInfo
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- CN106783865A CN106783865A CN201611065246.2A CN201611065246A CN106783865A CN 106783865 A CN106783865 A CN 106783865A CN 201611065246 A CN201611065246 A CN 201611065246A CN 106783865 A CN106783865 A CN 106783865A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 60
- 238000007667 floating Methods 0.000 claims abstract description 82
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 29
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 230000005641 tunneling Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 18
- 210000004027 cell Anatomy 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 210000002421 cell wall Anatomy 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract description 11
- 238000010168 coupling process Methods 0.000 abstract description 11
- 238000005859 coupling reaction Methods 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 241000790917 Dioxys <bee> Species 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of preparation method of memory cell, belongs to technical field of manufacturing semiconductors, including：There is provided a definition has the Semiconductor substrate of the prefabricated preparation area of grid and the prefabricated preparation area of source and drain and sequentially forms a floating gate tunneling oxide layer, a floating gate polysilicon layer and a floating boom silicon dioxide layer in semiconductor substrate surface；Floating boom silicon dioxide layer above the prefabricated preparation area of grid forms one first groove；Removal floating boom silicon dioxide layer, and floating gate polysilicon layer one second groove of formation above the prefabricated preparation area of grid；In the ONO layer of floating gate polysilicon layer disposed thereon one；A control grid layer is formed in ONO layer surface；Control grid layer, ONO layer and floating gate polysilicon layer above the prefabricated preparation area of removal source and drain；Made annealing treatment to form source-drain electrode after ion implantation technology is implemented in the prefabricated preparation area of source and drain.Beneficial effects of the present invention：The contact area of floating boom and control gate is improved, the coupling efficiency of floating boom and control gate is improved, so as to improve write-in and the efficiency of erasing of memory cell.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of preparation method of memory cell.
Background technology
The control gate (Control Gate, CG) of the memory cell of flash memory and the coupling of floating boom (Floating Gate, FG)
Rate (coupling ratio) directly affects write-in and the efficiency of erasing of floating gate type flash memory, improves the coupling of CG to FG
Ratio is most important for the operating efficiency of floating gate type flash memory.
With the improvement of manufacturing technology, the size of FG has been reduced to sub-micron rank, by tunneling oxide potential barrier, electronics
(or hole) is injected into FG, stores the threshold voltage that the electric charge in FG changes device, and mode, stores data successively,
CG utilizes the current potential of Capacity control FG.Coupling efficiency between FG and CG is relevant with the overlapping area between FG and CG, faying surface
Product is bigger, and coupling efficiency is bigger, but the ability of reduction unit size can be limited when increasing overlapping area, close so as to hinder device
The raising of degree.
By taking the storage element preparation method of existing flash memory as an example, existing way is the deposition SiO2/ after FG is finished
SIN/SiO2 is ono dielectric layer, and then the redeposition CG on ONO, forms electric capacity, specifically, profit ONO by the use of ONO as medium
Dielectric layer realizes the isolation of CG to FG, and increasing CG to FG's FG is wrapped up with CG perpendicular to the direction of FG raceway grooves
Coupling ratio, the control stronger to FG so as to realize CG.
Based on current technological process, to increase the coupling ratio of CG to FG, thinning ONO thickness certainly will be wanted, subtract
The storage time of electric charge can be reduced while thin ONO.
The content of the invention
For problems of the prior art, the invention provides a kind of by improving the coupling between floating boom and control gate
Conjunction rate is so as to the write-in for improving memory cell and the memory cell preparation method for clashing efficiency.
The present invention is adopted the following technical scheme that：
A kind of preparation method of memory cell, methods described includes：
Step S1, the definition of offer one have the Semiconductor substrate of the prefabricated preparation area of default grid and the prefabricated preparation area of source and drain, and in institute
State semiconductor substrate surface and sequentially form a floating gate tunneling oxide layer, a floating gate polysilicon layer and a floating boom silicon dioxide layer；
Step S2, the floating boom silicon dioxide layer above the prefabricated preparation area of the grid form one first groove；
Step S3, the removal floating boom silicon dioxide layer, and form one second groove in the floating gate polysilicon layer；
Step S4, in the ONO layer of floating gate polysilicon layer disposed thereon one, the ONO layer is covered the floating boom polycrystalline
The cell wall and bottom land of silicon layer and second groove；
Step S5, a control grid layer is formed in the ONO layer surface, and make control grid layer filling described second recessed
Groove；
The control grid layer, the ONO layer and the floating boom above step S6, the removal prefabricated preparation area of source and drain is more
Crystal silicon layer；
Step S7, after ion implantation technology is implemented in the prefabricated preparation area of the source and drain made annealing treatment to form source-drain electrode.
Preferably, a p-well region is defined by shallow grooved-isolation technique on the semiconductor substrate, and in the p-well region
Definition forms the prefabricated preparation area of the grid, and defines to form the prefabricated preparation area of the source and drain in the prefabricated preparation area both sides of the grid.
Preferably, by an etching technics in the step S2, first groove is formed.
Preferably, by an etching technics in the step S3, using first groove, in the removal floating boom dioxy
While SiClx layer, the floating gate polysilicon layer above the prefabricated preparation area of the grid forms one second groove.
Preferably, the step S6 removes the floating gate polysilicon layer, the ONO layer and institute by an etching technics
State control grid layer.
Preferably, the step S2 includes：
Step S21, in the floating boom silicon dioxide layer coating photoresist layer；
Step S22, the patterning photoresist layer；
Step S23, with pattern the photoresist layer be mask, etching positioned at the grid prepare area above it is described
Floating boom silicon dioxide layer is forming first groove；
Step S24, the removal photoresist layer.
Preferably, in the step S23, the floating boom silicon dioxide layer, described are etched by the way of wet etching
One groove is inverted trapezoidal structure.
Preferably, in the step S3, the floating gate polysilicon layer is etched by the way of dry etching, described second is recessed
Groove is inverted trapezoidal structure.
Preferably, the wet etching in the step S2 is identical with the etching rate of the dry etching in the step S3.
Preferably, in the step S5, the floating gate polysilicon layer, the ONO layer are etched by the way of dry etching
And the control grid layer.
The beneficial effects of the invention are as follows：By forming the second groove on the floating gate polysilicon layer, realize floating boom with control
Bigger contact area between grid processed, without thinning ONO layer thickness, is not influenceing unit size, without reducing cell density
In the case of, the coupling efficiency between floating boom and control gate is improved, so as to improve write-in and the efficiency of erasing of memory cell.
Brief description of the drawings
Fig. 1 be a preferred embodiment of the present invention in, the schematic diagram of step S1；
Fig. 2 be a preferred embodiment of the present invention in, the schematic diagram of step S2；
Fig. 3 be a preferred embodiment of the present invention in, the schematic diagram of step S2；
Fig. 4 be a preferred embodiment of the present invention in, the schematic diagram of step S3；
Fig. 5 be a preferred embodiment of the present invention in, the schematic diagram of step S4 and step S5；
Fig. 6 be a preferred embodiment of the present invention in, the schematic diagram of step S6；
Fig. 7 be a preferred embodiment of the present invention in, the schematic diagram of step S7；
Fig. 8 be a preferred embodiment of the present invention in, the flow chart of the preparation method of memory cell；
Fig. 9 be a preferred embodiment of the present invention in, the flow chart of step S2.
Specific embodiment
It should be noted that in the case where not conflicting, following technical proposals can be mutually combined between technical characteristic.
Specific embodiment of the invention is further described below in conjunction with the accompanying drawings：
As shown in figures 1-8, a kind of preparation method of memory cell, the above method includes：
Step S1, the definition of offer one have the Semiconductor substrate 1 of the prefabricated preparation area of grid and the prefabricated preparation area of source and drain, and in above-mentioned half
The surface of conductor substrate 1 sequentially forms a floating gate tunneling oxide layer 2, a floating gate polysilicon layer 3 and a floating boom silicon dioxide layer 4；
Step S2, the above-mentioned floating boom silicon dioxide layer 4 above the prefabricated preparation area of above-mentioned grid form one first groove 5；
Step S3, the above-mentioned floating boom silicon dioxide layer 4 of removal, and the above-mentioned floating boom polycrystalline above the prefabricated preparation area of above-mentioned grid
Silicon layer 3 forms one second groove 6；
Step S4, in the ONO layer 7 of 3 disposed thereon of above-mentioned floating gate polysilicon layer one, above-mentioned ONO layer 7 is covered above-mentioned floating boom many
The surface of crystal silicon layer 3 and the cell wall and bottom land of above-mentioned second groove 6；
Step S5, a control grid layer 8 is formed in the surface of above-mentioned ONO layer 7, and above-mentioned control grid layer 8 is filled above-mentioned second
Groove 6；
Above-mentioned control grid layer 8, above-mentioned ONO layer 7 and above-mentioned floating boom above step S6, the above-mentioned prefabricated preparation area of source and drain of removal
Polysilicon layer 3；
Step S7, after ion implantation technology is implemented in the prefabricated preparation area of above-mentioned source and drain made annealing treatment to form source-drain electrode.
In the present embodiment, in forming tunnel oxide 2 (in Fig. 1 successively in Semiconductor substrate 1 (the P Sub in Fig. 1)
Tunnel oxide), floating gate polysilicon layer 3 (FG in Fig. 1), floating boom silicon dioxide layer 4 (oxide in Fig. 1), Fig. 1 dotted lines
It is the prefabricated preparation area of grid at frame G, is source-drain electrode and preparation area at dotted line frame S and dotted line frame D.
Floating boom silicon dioxide layer 4 is performed etching to form the first groove 5, while etching floating boom silicon dioxide layer 4 and floating
Gate polysilicon layer 3, the second groove 6 is formed with while floating boom silicon dioxide layer 4 are removed in etching floating gate polysilicon layer 3.
ONO layer 7 and control grid layer 8 (CG in Fig. 5) are deposited on floating gate polysilicon layer 3.Remove the above-mentioned of the prefabricated preparation area both sides of grid
Floating gate polysilicon layer 3, above-mentioned ONO layer 7 and above-mentioned control grid layer 8, to form the basic structure of device.It is prefabricated in above-mentioned grid
The prefabricated preparation area of source-drain electrode of preparation area both sides is made annealing treatment to form source-drain electrode after implementing ion implantation technology, to form device
Electrode be N+ (source) and N+ (Drain) in Fig. 7, i.e. source electrode 9 and drain electrode 10 in Fig. 7.
By forming the second groove 6 on above-mentioned floating gate polysilicon layer 3, realize floating gate polysilicon layer 3 and control grid layer 8 it
Between bigger contact area, without the thickness of thinning ONO layer 7, do not influenceing unit size, the situation without reducing cell density
Under, the coupling efficiency between floating boom and control gate is improved, so as to improve write-in and the efficiency of erasing of memory cell.
In preferred embodiments of the present invention, a p-well region is defined by shallow grooved-isolation technique in above-mentioned Semiconductor substrate, and
The prefabricated preparation area of above-mentioned grid is formed defined in above-mentioned p-well region, and defines to form above-mentioned in the prefabricated preparation area both sides of above-mentioned grid
The prefabricated preparation area of source and drain.
In preferred embodiments of the present invention, by an etching technics in above-mentioned steps S2, above-mentioned first groove 5 is formed.
In preferred embodiments of the present invention, by an etching technics in above-mentioned steps S3, using above-mentioned first groove 5, in
While removing above-mentioned floating boom silicon dioxide layer 4, the above-mentioned floating gate polysilicon layer 3 above the prefabricated preparation area of above-mentioned grid forms one
Second groove 6.
In preferred embodiments of the present invention, above-mentioned steps S2 includes：
Step S21, in above-mentioned floating boom silicon dioxide layer 4 coating photoresist layer 11 (PR in Fig. 2)；
Step S22, the above-mentioned photoresist layer 11 of patterning；
Step S23, with pattern above-mentioned photoresist layer 11 be mask, etching positioned at above-mentioned grid prepare area above it is upper
Floating boom silicon dioxide layer 4 is stated to form above-mentioned first groove 5；
Step S24, the above-mentioned photoresist layer 11 of removal.
In the present embodiment, can also perform etching to form the first above-mentioned first groove 5 by the mask of other forms.
In preferred embodiments of the present invention, in above-mentioned steps S23, above-mentioned floating boom dioxy is etched by the way of wet etching
SiClx layer 4, above-mentioned first groove 5 is inverted trapezoidal structure.
In the present embodiment, concrete methods of realizing is not limited to the mode of above-mentioned wet etching.The cell wall 6 of the first groove 5
Gradually magnify in bottom land to cell wall direction along the second groove.
In preferred embodiments of the present invention, in above-mentioned steps S3, above-mentioned floating boom polycrystalline is etched by the way of dry etching
Silicon layer 3, above-mentioned second groove 6 is inverted trapezoidal structure.In the present embodiment, concrete methods of realizing is not limited to above-mentioned dry etching
Mode.The cell wall 6 of the second groove 6 gradually magnifies along bottom land to the cell wall direction of the second groove.
In preferred embodiments of the present invention, the dry etching in wet etching and above-mentioned steps S3 in above-mentioned steps S23
Etching rate it is identical.
In the present embodiment, while floating boom silicon dioxide layer 4 are removed, the floating boom polycrystalline above the prefabricated preparation area of grid
Silicon layer 3 forms one second groove 5.
In preferred embodiments of the present invention, in above-mentioned steps S5, above-mentioned floating boom polycrystalline is etched by the way of dry etching
Silicon layer 3, above-mentioned ONO layer 7 and above-mentioned control grid layer 8.
For a person skilled in the art, after reading described above, various changes and modifications undoubtedly will be evident that.
Therefore, appending claims should regard the whole variations and modifications for covering true intention of the invention and scope as.In power
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (10)
1. a kind of preparation method of memory cell, it is characterised in that methods described includes：
Step S1, the definition of offer one have the Semiconductor substrate of the prefabricated preparation area of grid and the prefabricated preparation area of source and drain, and in the semiconductor
Substrate surface sequentially forms a floating gate tunneling oxide layer, a floating gate polysilicon layer and a floating boom silicon dioxide layer；
Step S2, the floating boom silicon dioxide layer above the prefabricated preparation area of the grid form one first groove；
Step S3, the removal floating boom silicon dioxide layer, and the floating gate polysilicon layer above the prefabricated preparation area of the grid
Form one second groove；
Step S4, in the ONO layer of floating gate polysilicon layer disposed thereon one, the ONO layer is covered the floating gate polysilicon layer
Surface and the cell wall and bottom land of second groove；
Step S5, a control grid layer is formed in the ONO layer surface, and the control grid layer is filled second groove；
The control grid layer, the ONO layer and the floating gate polysilicon above step S6, the removal prefabricated preparation area of source and drain
Layer；
Step S7, after ion implantation technology is implemented in the prefabricated preparation area of the source and drain made annealing treatment to form source-drain electrode.
2. preparation method according to claim 1, it is characterised in that on the semiconductor substrate by shallow-trench isolation work
Skill defines a p-well region, and the prefabricated preparation area of the grid is formed defined in the p-well region, and in the prefabricated preparation area of the grid
Both sides define to form the prefabricated preparation area of the source and drain.
3. preparation method according to claim 1, it is characterised in that by an etching technics in the step S2, forms
First groove.
4. preparation method according to claim 1, it is characterised in that by an etching technics in the step S3, utilizes
First groove, while the floating boom silicon dioxide layer is removed, the floating boom above the prefabricated preparation area of the grid
Polysilicon layer forms one second groove.
5. preparation method according to claim 1, it is characterised in that the step S6 removes institute by an etching technics
State floating gate polysilicon layer, the ONO layer and the control grid layer.
6. preparation method according to claim 1, it is characterised in that the step S2 includes：
Step S21, in the floating boom silicon dioxide layer coating photoresist layer；
Step S22, the patterning photoresist layer；
Step S23, with pattern the photoresist layer be mask, etching positioned at the grid prepare area above the floating boom
Silicon dioxide layer is forming first groove；
Step S24, the removal photoresist layer.
7. preparation method according to claim 3, it is characterised in that in the step S23, by the way of wet etching
The floating boom silicon dioxide layer is etched, first groove is inverted trapezoidal structure.
8. preparation method according to claim 7, it is characterised in that in the step S3, by the way of dry etching
The floating gate polysilicon layer is etched, second groove is inverted trapezoidal structure.
9. the preparation method according to claim 8, it is characterised in that wet etching and the step in the step S2
The etching rate of the dry etching in rapid S3 is identical.
10. preparation method according to claim 1, it is characterised in that in the step S5, by the way of dry etching
Etch the floating gate polysilicon layer, the ONO layer and the control grid layer.
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| CN201611065246.2A CN106783865B (en) | 2016-11-28 | 2016-11-28 | A kind of production method of storage unit |
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| CN201611065246.2A CN106783865B (en) | 2016-11-28 | 2016-11-28 | A kind of production method of storage unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863298A (en) * | 2017-12-06 | 2018-03-30 | 武汉新芯集成电路制造有限公司 | The preparation method and floating gate type flash memory of floating gate type flash memory |
| CN108133937A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | Flush memory device and its manufacturing method |
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| CN105576016A (en) * | 2014-10-09 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Gate structure and making method thereof, and flash memory device |
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| JPH0590610A (en) * | 1991-09-30 | 1993-04-09 | Rohm Co Ltd | Nonvolatile semiconductor memory and manufacture thereof |
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| CN108133937A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | Flush memory device and its manufacturing method |
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| CN106783865B (en) | 2019-02-15 |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |