CN105097814B - Semiconductor memory, semiconductor memory array and its operating method - Google Patents
Semiconductor memory, semiconductor memory array and its operating method Download PDFInfo
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- CN105097814B CN105097814B CN201410218841.XA CN201410218841A CN105097814B CN 105097814 B CN105097814 B CN 105097814B CN 201410218841 A CN201410218841 A CN 201410218841A CN 105097814 B CN105097814 B CN 105097814B
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Abstract
The present invention provides a kind of semiconductor memory, the semiconductor memory includes at least semiconductor substrate, a storage bit architecture is included at least in the semiconductor substrate, the storage bit architecture includes: the source doping region and drain doping region to be formed in the semiconductor substrate；The storage grid stack architecture being formed in the semiconductor substrate between source doping region and drain doping region；It is formed in the side wall of storage grid stacked structure two sides, including being located at the source electrode side wall of source doping region side and positioned at the drain electrode side wall of drain doping region side；The metal contact structure being formed on the outside of side wall, the source metal contact structures including being located on source doping region and the drain metal contacts structure on drain doping region；Wherein, the thickness of the drain electrode side wall is less thanTechnical solution of the present invention can be to avoid when carrying out erasing operation, all storage bit architectures will be activated in the prior art, the problem of reduction so as to cause storage life.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, more particularly to a kind of semiconductor memory, semiconductor storage battle array
Column and its operating method.
Background technique
In traditional ETOX NOR flash memory as shown in Figure 1, including the storage formed over the semiconductor substrate 10
Bit architecture, wherein each storage bit architecture includes the source doping region S and drain doping region D to be formed in the semiconductor substrate, shape
At the storage grid stack architecture 30 in the semiconductor substrate between source doping region and drain doping region, and it is formed in institute
State the side wall 20 of 30 two sides of storage grid stack architecture.The storage grid stack architecture 30 includes: partly to lead positioned at described
The tunnel oxide 14 on body substrate surface；Floating gate layer FG on the tunnel oxide 14；On the floating gate layer FG
ONO layer (not indicating)；Control grid layer CG on the ONO layer.The floating gate layer and control grid layer are polysilicon layer.Its
In, the side wall 20 of 30 two sides of storage grid stack architecture is to be formed using the technique for being conventionally formed side wall, the side of two sides
The appearance of wall 20 is roughly the same, is the class bevel structure of upper-thin-lower-thick.The side wall 20 can be multilayered structure, such as include tight
The first side wall layer (not shown) and the second side wall layer on the outside of the first side wall of the adjacent storage grid stack architecture 30
(not shown), material can be silicon nitride, silicon oxynitride, silica or the composition of three.
As shown in connection with fig. 2, Fig. 2 is that storage bit architecture shown in Fig. 1 combines the semiconductor memory array to be formed.Described half
Conductor storage array includes storing bit architecture described in two column Fig. 1 of at least two row.With the drain electrode of the storage bit architecture of a line
Metal contact structure 40 is electrically connected to mutually bit line W, the source metal contact structures 60 of the storage bit architecture of same row
It is electrically connected to wordline B mutually, the storage grid stack architecture 30 with the storage bit architecture of a line passes through control gate gold
Belong to contact structures 50 and is electrically connected to control grid line C mutually.
In traditional technology, write-in behaviour is carried out for Fig. 1 and storage bit architecture shown in Fig. 2 and semiconductor memory array
As:
The storage position in the semiconductor memory array is chosen, the bit line connected to selected storage position provides voltage
4.2V, the wordline connected to selected storage position provide voltage 0V, the control grid line connected to selected storage position
Voltage 9.5V is provided, provides voltage 0V to the semiconductor substrate；
Erasing operation is carried out for Fig. 1 and storage bit architecture shown in Fig. 2 and semiconductor memory array are as follows: choose institute
The storage position in semiconductor memory array is stated, wordline, bit line and the semiconductor substrate connected to selected storage position
Voltage 7V is provided, the control grid line connected to selected storage position provides voltage -8V.
In above-mentioned erasing operation, in selected storage bit architecture, electronics from floating gate layer FG by floating gate layer FG and
Tunnel oxide 14 between semiconductor substrate 10 enters semiconductor substrate, to realize the erasing operation to storage bit architecture.
However wordline, bit line and the semiconductor substrate of the selected storage bit architecture provide identical voltage together,
So that all storage bit architectures being located in same semicondctor storage array are all activated, and only selected storage position knot
Structure needs to carry out erasing operation, also, erasing operation of every progress is it is necessary to make all storage bit architectures be activated, this
Very big loss is brought to storage bit architecture, greatly shortens the longevity of the semiconductor memory using the storage bit architecture
Life.
Summary of the invention
In view of the foregoing deficiencies of prior art, it is led the purpose of the present invention is to provide a kind of semiconductor memory, partly
Body storage array and its operating method, for solving in the prior art when carrying out erasing operation, all storage bit architectures
The problem of will being activated.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor memory, and the semiconductor is deposited
Reservoir includes at least semiconductor substrate, and a storage bit architecture, the storage bit architecture packet are included at least in the semiconductor substrate
It includes:
Form source doping region and drain doping region in the semiconductor substrate；
The storage grid stack architecture being formed in the semiconductor substrate between source doping region and drain doping region；
Be formed in the side wall of storage grid stacked structure two sides, including be located at source doping region side source electrode side wall and
Drain electrode side wall positioned at drain doping region side；
The metal contact structure being formed on the outside of side wall, including be located at source doping region on source metal contact structures and
Drain metal contacts structure on drain doping region；
Wherein, the thickness of the source electrode side wall is less than
Preferably, the drain metal contacts structure is lower than the storage grid stack architecture.
Preferably, the storage grid stack architecture includes: the tunnel oxide positioned at the semiconductor substrate surface；
Floating gate layer on the tunnel oxide；ONO layer on the floating gate layer；Control gate on the ONO layer
Layer.Preferably, the floating gate layer and control grid layer are polysilicon layer.
Preferably, the source electrode side wall is the strip of upper and lower consistency of thickness.
Correspondingly, technical solution of the present invention additionally provides a kind of semiconductor memory array, the semiconductor memory array
It is mutual that storage bit architecture, the drain metal contacts structure with the storage bit architecture of a line as described above are arranged including at least two rows two
It is mutually electrically connected to bit line, the source metal contact structures of the storage bit architecture of same row are electrically connected to mutually wordline,
Storage grid stack architecture with the storage bit architecture of a line is electrically connected to mutually control grid line.
Preferably, the semiconductor memory array includes at least a storage unit, and the storage unit is set relatively including two
The the first storage bit architecture and the second storage bit architecture set, the source electrode side wall of the first storage bit architecture and the second storage position knot
Source metal contact structures are shared between the source electrode side wall of structure.
Preferably, the semiconductor memory array includes at least the first storage unit being oppositely arranged and the second storage is single
Member shares a drain metal contacts structure between first storage unit and the adjacent drain electrode side wall of the second storage unit.
Correspondingly, technical solution of the present invention additionally provides a kind of operating method of semiconductor memory array, it is described partly to lead
The operating method of body storage array includes at least:
Semiconductor memory array as described above is provided；
It carries out write operation: choosing the storage bit architecture in the semiconductor memory array, selected storage position is tied
The bit line that structure is connected provides voltage 3.5V~5.5V, and the wordline connected to selected storage position provides voltage 0V, to quilt
The control grid line that the storage bit architecture chosen is connected provides voltage 8V~10V, provides voltage 0V to the semiconductor substrate；
It carries out erasing operation: choosing the storage bit architecture in the semiconductor memory array, selected storage position is tied
The bit line that structure is connected provides voltage 6V, and the wordline connected to selected storage bit architecture provides voltage -11V, to selected
In the control grid line that is connected of storage bit architecture and the semiconductor substrate identical voltage is provided.
As described above, semiconductor memory of the invention, semiconductor memory array and its operating method, have beneficial below
Effect:
Since the thickness of the drain electrode side wall of storage bit architecture each in semiconductor memory is less thanIn erasing operation
When electronics can enter drain electrode from floating gate layer by drain electrode side wall to completing erasing operation.Due to the control grid line and
Semiconductor substrate is provided identical voltage, so that in addition to the storage bit architecture chosen by wordline and bit line, the semiconductor lining
Other storage bit architectures on bottom are not activated, and avoid and are activated when not needing erasing and bring is damaged, thus
Extend the service life of semiconductor memory.
Detailed description of the invention
Fig. 1 is shown as the schematic diagram of the semiconductor storage bit architecture in traditional technology.
Fig. 2 is shown as the schematic diagram of the semiconductor memory array in traditional technology.
Fig. 3 is shown as the schematic diagram of the semiconductor storage bit architecture provided in the embodiment of the present invention.
Fig. 4 is shown as the schematic diagram of the semiconductor memory array provided in the embodiment of the present invention.
Component label instructions
10 semiconductor substrates
The source doping region S
The drain doping region D
30 storage grid stack architectures
20 side walls
14 tunnel oxides
FG floating gate layer
CG control grid layer
40 drain metal contacts structures
50 control gate metal contact structures
60 source metal contact structures
100 semiconductor substrates
300 storage grid stack architectures
200 side walls
140 tunnel oxides
400 drain metal contacts structures
500 control gate metal contact structures
600 source metal contact structures
210 source electrode side walls
220 drain electrode side walls
W bit line
B wordline
C controls grid line
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 3 is please referred to Fig. 4.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
As shown in figure 3, providing a kind of semiconductor memory in the present embodiment, the semiconductor memory includes at least half
Conductor substrate 100, a storage bit architecture is included at least in the semiconductor substrate 100, and the storage bit architecture includes:
Form source doping region S and drain doping region D in the semiconductor substrate；In general, the source doping region S and
Drain doping region D can be formed using photoetching process and plasma doping process, and the source between adjacent two storages bit architecture
Pole doped region S and drain doping region D are shared.
The storage bit architecture further include: the semiconductor substrate being formed between source doping region S and drain doping region D
Storage grid stack architecture 300 on 100；Preferably, the storage grid stack architecture 300 includes: positioned at described half
The tunnel oxide 140 on 100 surface of conductor substrate；Floating gate layer FG on the tunnel oxide 140；Positioned at the floating gate
ONO layer on layer FG；Control grid layer CG on the ONO layer.
The storage grid stack architecture can be employed many times semiconductor film-forming process and form layers of material layer, then sharp
Retain the structure between source doping region S and drain doping region D in semiconductor substrate 100 with photoetching and selective etch technique,
To form the storage grid stack architecture.
Specifically, one of embodiment can be with are as follows:
The tunnel oxide 140 is formed using thermal oxidation technology or chemical vapor deposition process, with a thickness of
The ONO layer (oxide layer-nitride layer-oxide layer) can be formed respectively using chemical vapor deposition process is repeatedly carried out
Layer, is made of bottom oxide layer, nitration case and top layer oxide layer.Preferably, using relatively thin bottom oxide layer and thicker
Top layer oxide layer not only can guarantee higher critical electric field strength, but also can obtain relatively thin equivalent oxide thickness, improve coupling
Rate reduces program voltage.
The floating gate layer FG and control grid layer CG is doped polysilicon layer, and the doped polysilicon layer generally can be using change
Gas-phase deposition is learned, and carries out doping in situ simultaneously and forms polysilicon layer to be formed, or using chemical vapor deposition process,
Ion implanting is used to be doped so that polysilicon layer is formed doped polysilicon layer again.
The storage bit architecture further include: be formed in the side wall of 300 two sides of storage grid stacked structure, the side wall packet
Include the drain electrode side wall 220 positioned at the source electrode side wall 210 of the side source doping region S and positioned at the drain doping region side D；Wherein, institute
The thickness for stating drain electrode side wall 220 is less thanPreferably, the material of the drain electrode side wall 220 is silica, and pattern is upper and lower
The strip of consistency of thickness.
Specifically, the source electrode side wall 210 and drain electrode side wall 220 can be formed in different process respectively.It is one of
Embodiment can be that the side wall of two sides has been formed using traditional side wall technique, then will be leaked using lithography and etching technique
Side wall above the doped region D of pole removes, then is gone using the side wall that depositing operation is formed above silica-filled drain doping region D
Then the opening left after removing recycles lithography and etching technique, etches source metal in silica in said opening
The figure of contact structures 400.
The storage bit architecture further include: be formed in the metal contact structure in 210,220 outside of side wall, the metal contact
Structure includes: that the source metal contact structures 400 on the S of source doping region, the drain metal on the D of drain doping region connect
Touch the control gate metal contact structure 500 of structure 600 and connection storage bit architecture control gate CG；Preferably, the drain electrode gold
Belong in the groove that contact structures 600 are formed directly between adjacent two drain electrodes side wall 220, height is lower than the storage grid
Stack architecture 300.Specifically, the metal contact structure can be formed using Damascus technics.
Correspondingly, as shown in figure 4, additionally provide a kind of semiconductor memory array in the present embodiment, the semiconductor storage
Array includes that at least two rows two arrange storage bit architecture as shown in Figure 3, and the drain metal with the storage bit architecture of a line connects
Touching structure 400 is electrically connected to mutually bit line W, and the source metal contact structures 600 of the storage bit architecture of same row are mutual
It is electrically connected to wordline B, the memory control gate metal contact structure 500 with the storage bit architecture of a line electrically connects mutually
It is connected to control grid line G.
Wherein, with continued reference to shown in Fig. 3, the semiconductor memory array includes at least a storage unit, and the storage is single
Member includes two the first storage bit architecture N1 being oppositely arranged and the second storage bit architecture N2, the leakage of the first storage bit architecture N1
A drain doping region D is shared between pole side wall 220 and the drain electrode side wall 220 of the second storage bit architecture N2, and shares a drain electrode
Metal contact structure 400.
In addition, the semiconductor memory array includes at least the first storage unit and the second storage unit being oppositely arranged,
Source metal contact structures 600 are shared between first storage unit and the adjacent source electrode side wall 210 of the second storage unit.
Correspondingly, a kind of operating method of semiconductor memory array is additionally provided in the present embodiment, the semiconductor storage
The operating method of array includes at least:
Semiconductor memory array as described above is provided；
It carries out write operation: choosing the storage bit architecture in the semiconductor memory array, selected storage position is tied
The bit line that structure is connected provides voltage 4.2V, and the wordline connected to selected storage bit architecture provides voltage 0V, to selected
In the control grid line that is connected of storage bit architecture voltage 9.5V is provided, provide voltage 0V to the semiconductor substrate；
It carries out erasing operation: the storage position in the semiconductor memory array is chosen, to selected storage bit architecture institute
The bit line of connection provides voltage 6V, and the wordline connected to selected storage bit architecture provides voltage -11V, to selected
The control grid line C and the semiconductor substrate 100 that storage bit architecture is connected provide identical voltage.
In above-mentioned erasing operation, since the thickness of drain electrode side wall 220 is less thanElectronics in erasing operation
Drain D can be entered from floating gate layer FG by drain electrode side wall 220 to complete erasing operation.Due to the control grid line CG and half
Conductor substrate 100 is provided identical voltage, in addition to the storage bit architecture chosen by wordline and bit line, the semiconductor substrate
Other storage bit architectures on 100 are not activated, and avoid and are activated when not needing erasing and bring is damaged, thus
Extend the service life of semiconductor memory.
In conclusion the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (9)
1. a kind of semiconductor memory, which is characterized in that the semiconductor memory includes at least semiconductor substrate, described partly to lead
A storage bit architecture is included at least in body substrate, the storage bit architecture includes:
Form source doping region and drain doping region in the semiconductor substrate；
The storage grid stack architecture being formed in the semiconductor substrate between source doping region and drain doping region；
It is formed in the side wall of storage grid stacked structure two sides, including being located at the source electrode side wall of source doping region side and being located at
The drain electrode side wall of drain doping region side；
The metal contact structure being formed on the outside of side wall including the source metal contact structures being located on source doping region and is located at
Drain metal contacts structure on drain doping region；
Wherein, the thickness of the drain electrode side wall is less thanIn the storage bit architecture, with the storage bit architecture of a line
Drain metal contacts structure is electrically connected to mutually bit line, and the source metal contact structures of the storage bit architecture of same row are mutual
It is mutually electrically connected to wordline, the storage grid stack architecture with the storage bit architecture of a line is electrically connected to mutually control
Grid line；The control gate when carrying out erasing operation to the semiconductor memory, in the selected storage bit architecture
Line and the semiconductor substrate provide identical voltage.
2. semiconductor memory according to claim 1, it is characterised in that: the drain metal contacts structure is lower than described
Storage grid stack architecture.
3. semiconductor memory according to claim 1, it is characterised in that: the storage grid stack architecture includes:
Positioned at the tunnel oxide of the semiconductor substrate surface；Floating gate layer on the tunnel oxide；Positioned at the floating gate
ONO layer on layer；Control grid layer on the ONO layer.
4. semiconductor memory according to claim 3, it is characterised in that: the floating gate layer and control grid layer are polysilicon
Layer.
5. semiconductor memory according to claim 1, it is characterised in that: the drain electrode side wall is upper and lower consistency of thickness
Strip.
6. a kind of semiconductor memory array, it is characterised in that: the semiconductor memory array includes at least two rows two column such as right
It is required that the 1 storage bit architecture.
7. semiconductor memory array according to claim 6, it is characterised in that: the semiconductor memory array includes at least
One storage unit, the storage unit include two the first storage bit architectures being oppositely arranged and the second storage bit architecture, and described the
A drain metal contacts structure is shared between the drain electrode side wall of one storage bit architecture and the drain electrode side wall of the second storage bit architecture.
8. semiconductor memory array according to claim 7, it is characterised in that: the semiconductor memory array includes at least
The first storage unit and the second storage unit being oppositely arranged, first storage unit and the adjacent source electrode of the second storage unit
Source metal contact structures are shared between side wall.
9. a kind of operating method of semiconductor memory array, it is characterised in that: the operating method of the semiconductor memory array is extremely
Include: less
Semiconductor memory array as claimed in claim 6 is provided；
It carries out write operation: the storage bit architecture in the semiconductor memory array is chosen, to selected storage bit architecture institute
The bit line of connection provides voltage 3.5V~5.5V, and the wordline connected to selected storage position provides voltage 0V, to selected
The control grid line that is connected of storage bit architecture voltage 8V~10V is provided, provide voltage 0V to the semiconductor substrate；
It carries out erasing operation: the storage bit architecture in the semiconductor memory array is chosen, to selected storage bit architecture institute
The bit line of connection provides voltage 6V, and the wordline connected to selected storage bit architecture provides voltage -11V.
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| CN201410218841.XA CN105097814B (en) | 2014-05-22 | 2014-05-22 | Semiconductor memory, semiconductor memory array and its operating method |
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| CN105097814B true CN105097814B (en) | 2019-05-17 |
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| US9972635B2 (en) * | 2016-02-29 | 2018-05-15 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing same |
| CN108493190B (en) * | 2018-03-06 | 2021-03-23 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674257A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | Fast-flash memory structure and producing method thereof |
| CN1917209A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Programmable and eraseable digital switch component, manufacturing method, and operation method |
| TW201001717A (en) * | 2008-04-17 | 2010-01-01 | Sandisk Corp | Non-volatile memory with sidewall channels and raised source/drain regions |
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2014
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674257A (en) * | 2004-03-26 | 2005-09-28 | 力晶半导体股份有限公司 | Fast-flash memory structure and producing method thereof |
| CN1917209A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Programmable and eraseable digital switch component, manufacturing method, and operation method |
| TW201001717A (en) * | 2008-04-17 | 2010-01-01 | Sandisk Corp | Non-volatile memory with sidewall channels and raised source/drain regions |
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