JP2007142448A5 - - Google Patents

Claims (3)

An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A charge storage layer equivalent to a non-conductor charge trap such as a floating gate, a nanocrystal layer, a silicon nitride film, etc. formed through a tunnel insulating film, and an insulating film formed above the charge storage layer A non-volatile semiconductor memory device having a gate electrode, and voltages Vg, Vsub, Vs and Vd having a relationship of “Vg> Vsub> Vs> Vd”, “Vsub> 0V”, “Vd ≦ Vcc” at the time of writing Are applied to the gate electrode, n-type well, source and drain, respectively, so that interband tunneling occurs near the drain. In those hot electrons are generated, writes the bit data by injecting the hot electrons into the charge storage layer,
A non-volatile semiconductor device, wherein a Y-system circuit is formed of a Vcc transistor. An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A charge storage layer equivalent to a non-conductor charge trap such as a floating gate, a nanocrystal layer, a silicon nitride film, etc. formed through a tunnel insulating film, and an insulating film formed above the charge storage layer A non-volatile semiconductor memory device having a gate electrode, and voltages Vg, Vsub, Vs and Vd having a relationship of “Vg> Vsub> Vs> Vd”, “Vsub> 0V”, “Vd ≦ Vcc” at the time of writing Are applied to the gate electrode, n-type well, source and drain, respectively, so that interband tunneling occurs near the drain. In those hot electrons are generated, writes the bit data by injecting the hot electrons into the charge storage layer,
A nonvolatile semiconductor device comprising a circuit that applies only 0 V to a positive voltage to a drain at the time of writing. 3. A nonvolatile semiconductor memory device, wherein the memory cells according to claim 1 or 2 are connected in a NOR type or a NAND type to form an array.