JP2006128594A5

JP2006128594A5 -

Info

Publication number: JP2006128594A5
Application number: JP2005030972A
Authority: JP
Filing date: 2005-02-07
Publication date: 2008-03-27
Anticipated expiration: 2024-11-01

Claims

And n-type well formed on a semiconductor substrate, a drain and a source and p + region formed at predetermined intervals on the n-type well surface, and the drain, a channel region formed between the source, the channel A charge storage layer such as a nanocrystal layer and a non-conductive charge trap layer formed above the region via a tunnel oxide film, and a gate electrode formed above the charge storage layer via an insulating film A nonvolatile semiconductor memory device in which memory cells are arranged in a matrix of a plurality of rows (X) and a plurality of columns (Y) ,
A bit line provided in each column and connected to a drain of a memory cell in the column;
A Y-system circuit including a circuit for controlling the voltage of each bit line, which is formed of a transistor for a standard power supply voltage (Vcc);
The nonvolatile semiconductor memory device characterized by comprising a.

An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed at a predetermined interval on the surface of the n-type well, and formed between the first and second p + regions. A channel region, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel oxide film, and an insulating film above the charge storage layer A non-volatile semiconductor memory device in which memory cells having a plurality of gate electrodes are arranged in a matrix of a plurality of rows (X) and a plurality of columns (Y) ,
A bit line provided between the columns and connected to a first p + region of a memory cell in one adjacent column and a second p + region of a memory cell in the other column;
A Y-system circuit including a circuit for controlling the voltage of each bit line, which is formed of a transistor for a standard power supply voltage (Vcc);
The nonvolatile semiconductor memory device characterized by comprising a.

An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed at a predetermined interval on the surface of the n-type well, and formed between the first and second p + regions. A channel storage region, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel insulating film, and an insulating film formed above the charge storage layer A bit data written in a nonvolatile semiconductor memory device having a first p + region as a ground potential ,
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the first p + region, and the second p + region is grounded The written bit data is read depending on whether or not the first and second p + regions are conductive when the potential is applied.
Reading method of the nonvolatile semiconductor memory device comprising a call.

A method of reading bit data written in the nonvolatile semiconductor memory device according to claim 2 with the first p + region as a ground potential ,
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the first p + region, and the second p + region is grounded The written bit data is read depending on whether or not the first and second p + regions are conductive when the potential is applied.
Reading method of the nonvolatile semiconductor memory device comprising a call.

And n-type well formed on a semiconductor substrate, a source and drain and the source, channel region formed between the drain of said n-type well p + region formed at predetermined intervals on the surface, the channel region A floating gate formed above the tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate electrode formed above the charge storage layer via an insulating film, A method for writing bit data in a nonvolatile semiconductor memory device having:
By applying a read back gate voltage higher than the read back gate voltage and the power supply voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the drain to the ground potential, the band is close to the drain. hot electrons are generated by the tunneling, the writing method of a nonvolatile semiconductor memory device, characterized in that it row to write bit data by injecting the hot electrons into the charge storage layer.

A method for writing bit data in the nonvolatile semiconductor memory device according to claim 1 , comprising:
By applying a read back gate voltage higher than the read back gate voltage and the power supply voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the drain to the ground potential, the band is close to the drain. hot electrons are generated by the tunneling, the writing method of a nonvolatile semiconductor memory device, characterized in that it row to write bit data by injecting the hot electrons into the charge storage layer.

A method for writing bit data in the nonvolatile semiconductor memory device according to claim 2 ,
By applying a read back gate voltage higher than the read back gate voltage and the power supply voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the first p + region to the ground potential, hot electrons are generated by band-to-band tunneling in the vicinity first p + region, writing method for a nonvolatile semiconductor memory device, characterized in that it row to write bit data by injecting the hot electrons into the charge storage layer .

An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A floating gate formed above the tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate electrode formed above the charge storage layer via an insulating film, A method for reading bit data written in a nonvolatile semiconductor memory device having:
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the source, and the drain is set to the ground potential. A reading method of a nonvolatile semiconductor memory device, wherein bit data is read out depending on whether or not there is electrical continuity.

A method for reading bit data written in the nonvolatile semiconductor memory device according to claim 1 , comprising:
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the source, and the drain is set to the ground potential. A reading method of a nonvolatile semiconductor memory device, wherein bit data is read out depending on whether or not there is electrical continuity.

A method of reading bit data written in the nonvolatile semiconductor memory device according to claim 2 ,
a positive read back gate voltage is applied to the n-type well, by applying a negative read voltage to the gate electrode, the same voltage as the read back gate voltage is applied to the second p + region, grounding the first p + region A reading method of a nonvolatile semiconductor memory device, wherein bit data is read depending on whether or not the first and second p + regions are conductive when a potential is applied.

An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A floating gate formed above the tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate electrode formed above the charge storage layer via an insulating film, A method of erasing bit data written in a nonvolatile semiconductor memory device having
a negative back gate voltage is applied to the n-type well, the Rukoto to a negative high voltage is applied to the gate electrode and the source, the hot holes are injected from the substrate into the charge storage layer, whereby the charge of the charge storage layer A method for erasing a nonvolatile semiconductor memory device, wherein the data written in the nonvolatile semiconductor memory device is erased by neutralization .