JP2006128594A - Nonvolatile semiconductor memory device, and methods of wiring, reading and erasing therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate a data transfer rate in data writing in a p-channel MONOS memory cell. <P>SOLUTION: In order to operate a bit line in GND-VCC, a back gate voltage of 4 V is applied to a cell well in programming. In order to accelerate switching of a program mode and a verify mode, verifying is also performed while applying the back gate voltage of 4 V. Therefore, on verifying, a voltage (absolute value) greater than -5 V of a reading mode is applied to a word line (gate). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a p-channel nonvolatile semiconductor memory device and a method for writing / reading / erasing the same.

  In recent years, a charge trap layer such as a low-conductivity nitride film is formed in place of the floating gate of a conventional flash memory, and one charge is injected into each of the source side and the drain side of the charge trap layer. There has been proposed a nonvolatile semiconductor memory that can record 2-bit information in a memory cell (see Patent Document 1).

  The non-volatile semiconductor memory of this document has an n channel MOS transistor structure, and it is the electron emission (source) side of the channel region that affects whether or not it becomes conductive when a voltage is applied between the source and drain. And the MOS transistor structure is basically symmetrical, and if the source and drain are connected in reverse, the source functions as the drain and the drain functions as the source. It was proposed with a focus on.

  That is, one bit is stored by injecting / extracting electrons (program / erase) to the source side region of the charge trap layer and turning on / off the flow of electrons from the source to the drain at the time of reading, If the electrodes are connected in reverse, the drain becomes the electron emission side. Therefore, by injecting / withdrawing charges into / from the drain side region of the charge trapping layer, the flow of electrons from the drain to the source is turned on / off to further increase 1 Remember bit.

  Reading of the source side bit is performed by grounding the source and applying a positive voltage (Vdr) to the drain. Reading of the drain side bit is performed by reverse connection in which the drain is grounded and a positive voltage (Vdr) is applied to the source. If electrons are injected into the program region, the threshold value at the time of reading rises and no current flows between the source / drain. Therefore, if the current is non-conductive (OFF), the bit is in the programmed state (0). When turned on, the bit is in a non-programmed state (1).

  As described above, in this nonvolatile semiconductor memory, charges are separately injected / extracted into a partial region on both sides of the charge trap layer, and during reading, the direction of the applied voltage is reversed to conduct / non-conduct in each direction. By detecting this, it is possible to record and read out 2-bit information.

  The configuration of the nonvolatile semiconductor memory and the data write / read operation will be further described with reference to FIG. The nonvolatile semiconductor memory (memory cell) 100 includes a pair of n + regions 102 and 103 formed in a surface region of a p-type silicon semiconductor substrate 101, a channel region between the n + regions 102 and 103, and the channel region. A tunnel oxide film 104, a charge trap layer 105, a silicon oxide film 106, and a gate electrode 107. Here, the charge trap layer 105 is composed of a silicon nitride film. The pair of n + regions 102 and 103 each function as a source or a drain.

  In this structure, electrons are injected / extracted independently into the left and right program regions 108 and 109 which are both ends of the charge trap layer 105. Charge injection (programming) into the charge trap layer 105 is performed by channel hot electron (CHE) injection.

  The case where channel hot electrons are injected into the right program region 109 will be described below. A potential difference is generated between the source and drain by setting the source to 0 V and the drain to about 5 V, and a high voltage (about 10 V) is applied to the gate 107. A current flows between the source and the drain due to the high voltage of the drain 103 and the gate 107, but the channel 110 disappears in the middle of the channel region (range I1) due to the high voltage of the drain 103. The range l1 of the formed channel 110 is conductive and no electric field is generated, but in the range l2 where the channel 110 is not formed, the electric field is accelerated by the potential difference between the source and drain, and electrons pass, and a part thereof Channel hot electron (CHE). The channel hot electrons pass through the tunnel oxide film 104 by the high voltage of the gate 107 and are injected into the right program region 109 of the charge trap layer 105, and the right program region 109 is in a state where electrons are trapped (program state). Become.

  When reading the bit data in the right program area 109, the read voltage Vgread is applied to the gate 107, and the read voltage Vdread between the source and drain is applied in the opposite direction to that in the program. That is, the right n + region 103 is grounded and Vdread is applied to the left n + region 102. Note that the absolute voltage value at this time is lower than that at the time of programming, and is about Vdread = 1.5V and Vgread = 3V. At this time, when electrons are trapped in the right program region 109, a channel is not formed in the lower layer of the program region 109 due to the increase in threshold value due to this charge, and the source / drain is not turned on. On the other hand, when electrons are not trapped in the program region 109, a channel is formed between the source and the drain to turn on. In this way, the bit data in the program area 109 can be read by using the n + area on the program area 109 side as a source and the opposing n + area as a drain.

Even when electrons are trapped in the right program area 109, when a voltage is applied in the same direction as during programming, that is, when the left n + area 102 is grounded and Vdread is applied to the right n + area 103. In this case, the channel region under the program region 109 is depleted by the positive potential of the drain (n + region 103) and electrons pass therethrough, so that even if charge is trapped in the program region 109, the reading operation in this direction is affected. Not give.
The injection of electrons into the left program area 108 and the reading of bit data can also be performed in the same manner as described above.

  In this way, electrons can be injected independently into the left and right program areas, and the electrons trapped in the other program area have an effect during the read operation on either the left or right program area. Therefore, 1-bit data can be recorded / read on each of the left and right program areas in one memory cell.

Erase (data erasure) processing in this type of nonvolatile semiconductor memory is performed on the whole chip or on a block (generally 512 kbit) unit. The erase process of the nonvolatile semiconductor memory is performed by extracting electrons trapped in the charge trap layer. When electrons are withdrawn from the charge trapping layer, the threshold value drops and each bit returns to an unprogrammed state.
US Pat. No. 5,768,192

  As described above, the nonvolatile semiconductor memory device described in Patent Document 1 injects electrons into the charge trapping layer by using channel hot electron injection, thereby inverting the bit by increasing the threshold value. is doing.

However, the injection of charges by channel hot electrons turns on between the source and drain, that is, injects some of the electrons into the charge trapping layer while passing a current between the source and drain. There is a problem that the efficiency is as low as 10 ⁻⁶ , and the load of the built-in power supply circuit is heavy and high-speed writing cannot be performed.

  In addition, the extraction of electrons in the erase process is performed to such an extent that the electrons are completely extracted in each memory cell. However, since there is a characteristic variation in each memory cell, the erase process is performed to the extent that the extraction is completed in all memory cells. When this is done, in some memory cells, there has been a case where electrons are excessively erased and charged with positive charges (over erase). A memory cell charged with a positive charge has a problem that the threshold value becomes negative and depletion occurs, and the memory cell remains conductive, which hinders reading of bit data.

  In order to solve such a problem, it is conceivable to configure the nonvolatile semiconductor memory with p-channel MONOS. With the p-channel MONOS structure, electron injection (BBHE injection) by electrons generated by high-efficiency band-to-band tunneling (BTBT) can be performed, and the program state is a low threshold value with a negative potential. Since the absolute value of the threshold value is increased by processing (withdrawing electrons), there is an advantage that there is no possibility of over-erasing even if the entire chip or block is used.

However, as a result of the experiment, the applicant has a structure in which the program is performed by injecting electrons into the end portion of the channel region and lowering the threshold value with an absolute value when the p-channel MONOS structure is adopted. Discovered that the following problems that are not in the n-channel MONOS structure occur. (Note that in this specification, all threshold values (increase / decrease) are expressed in terms of absolute values.)
The first problem is that even if electrons are injected into the charge trap layer (program region) in the vicinity of the source, electrons do not move to the center of the charge trap layer, so the (local) threshold at the center of the channel region. The value does not decrease, and the threshold value as a memory cell decreases slightly. For this reason, it is difficult to ensure the reliability for holding the bit data for a long time.

  This state is shown in FIG. In the initial state ((A) in the figure), the channel region has almost the same local threshold value. In the programmed state ((B) in the same figure), charges (electrons) are injected only in the vicinity of the p + region, so the local threshold at the center of the channel does not decrease, and the overall decrease in threshold is slight. is there.

  The second problem is that in the case of a p-channel MOS, it is necessary to apply a negative voltage to the bit line (drain), and it is necessary to apply a high voltage to the bit line during writing / erasing. It is difficult to operate a circuit that handles voltage at high speed.

  The present invention provides a nonvolatile semiconductor memory device that improves the writing efficiency and does not cause over-erasing, and that can realize a high data transfer rate during data writing. With the goal.

(1) An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed on the surface of the n-type well at a predetermined interval, and the first and second p + regions A channel region formed therebetween, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel oxide film, and an insulating film above the charge storage layer A memory cell having a gate electrode formed therebetween,
Of the channel region, an impurity concentration in an intermediate region between the first p + region and the second p + region is set to be higher than an impurity concentration in a region in the vicinity of the first p + region and / or the second p + region. It is characterized by being lowered (see FIG. 2A).

  In the present invention, the channel region has a graded structure in which the impurity concentration in the channel region is low near the middle. In a p-channel MOS transistor, when the impurity concentration is low, the local threshold value of the region is lowered. In a p-channel MONOS type memory cell, writing is performed by injecting electrons into the edge of the charge storage layer to lower the on / off threshold. Both the charge accumulated in the nanocrystal layer and the charge trapped in the nonconductive charge trapping layer do not move. In this case, even if charge is injected only into the end portion of the charge storage layer, the threshold value in the middle portion of the channel region is originally low, so if the local threshold value in the end portion decreases, the entire threshold value is reduced. Is sufficiently reduced (see FIG. 2B). By sufficiently lowering the threshold value in this way, data can be retained for a long time.

  In order to reduce the impurity concentration in the middle part of the channel region, the impurity concentration in the channel region is formed lower than usual during the n-type well formation process, and after the ONO film and gate electrode are formed, oblique implantation is performed. The impurity concentration in the vicinity of the p + region may be increased to a normal level by (halo implantation).

(2) a first program region which is a partial region on the first p + region side of the charge storage layer, and a second region which is a partial region on the second p + region side of the charge storage layer. It is characterized in that 2-bit data is written by accumulating charges in the program area independently.

(3) A memory cell having the structure of (1) or (2) is used, and a plurality of memory cells are arranged in an XY matrix and connected by a virtual ground method.

  Since the memory cell of the present invention is composed of one transistor, various connection forms such as the virtual ground connection, NOR connection and contactless connection disclosed above can be realized with a simple configuration.

(4) An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed on the surface of the n-type well at a predetermined interval, and the first and second p + regions. A channel region formed therebetween, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel oxide film, and an insulating film above the charge storage layer A method of reading bit data written in a nonvolatile semiconductor memory device having a gate electrode formed therebetween,
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the first p + region, and the second p + region is grounded The bit data in the first program area is read depending on whether or not the first and second p + areas are electrically connected when the potential is applied.
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the second p + region, and the first p + region is grounded The bit data in the second program area is read depending on whether or not the first and second p + areas become conductive when the potential is applied.

  By applying a positive read back gate voltage to the n-type well, the first and second p + regions are biased in the positive direction. Therefore, a relatively negative potential is obtained by setting the p + region functioning as a drain during reading to the ground potential. As a result, there is no need to provide a circuit that handles negative voltage as a peripheral circuit for controlling the p + region (drain), and the circuit configuration can be simplified and speeded up.

(5) An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed at a predetermined interval on the surface of the n-type well, and the first and second p + regions A channel region formed therebetween, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel oxide film, and an insulating film above the charge storage layer A method of writing bit data in a nonvolatile semiconductor memory device having a gate electrode formed through
By applying a write back gate voltage higher than the read back gate voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the first p + region to the ground potential, the first p + Generating hot electrons by band-to-band tunneling in the vicinity of the region, injecting the hot electrons into the first program region of the charge storage layer, and writing the first bit;
By applying a write back gate voltage higher than the read back gate voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the second p + region to the ground potential, the second p + Hot electrons are generated by band-to-band tunneling in the vicinity of the region, and the second bits are written by injecting the hot electrons into the second program region of the charge storage layer.

  By applying a relatively high write back gate voltage to the n-type well, the first and second p + regions are relatively large and biased in the positive direction. Therefore, by applying a positive high voltage to the gate electrode and setting the p + region functioning as the drain to the ground potential, hot electrons are generated in the p + region due to band-to-band tunneling. As a result, there is no need to provide a circuit that handles negative voltage as a peripheral circuit for controlling the p + region (drain), and the circuit configuration can be simplified and speeded up.

(6) At the time of writing the first bit, with the write back gate voltage applied to the n-type well, a negative verify read voltage having a larger absolute value than the normal read voltage is applied to the gate electrode, Verify whether the first bit is written depending on whether the first and second p + regions are conductive when a positive voltage is applied to the p + region of 1 and the second p + region is set to the ground potential. And
At the time of writing the second bit, with the write back gate voltage applied to the n-type well, the verify read voltage is applied to the gate electrode, a positive voltage is applied to the second p + region, Whether or not the second bit is written is verified by whether or not the first and second p + regions are conductive when the p + region is set to the ground potential.

  The n-type well can be switched between program and verify by applying a verify read voltage having an absolute value larger than the normal read voltage to the gate electrode while the write back gate voltage is applied to the n-type well. It becomes unnecessary to change the voltage of the well. Since the n-type well has an extremely large charge capacity as compared with other constituent parts, high-speed switching, that is, high-speed writing becomes possible without changing the potential of the n-type well.

  The basic operation of the present invention described above is as follows. When charges (negative charges) are accumulated in the charge accumulation layer, the threshold voltage viewed from the gate electrode changes. This change in threshold value is stored as bit data. Since it is a p-channel, the threshold voltage is set to a negative voltage, and when a negative voltage having an absolute value larger than the threshold is applied to the gate electrode, a channel is formed between the first and second p + regions. Conduct. Note that one of the first and second p + regions functions as a source and the other functions as a drain, but the function is not fixed, and the function is changed depending on the applied voltage condition. When negative charge is accumulated in the charge accumulation layer, the negative potential generated by the negative charge causes conduction between the first and second p-type regions even when a low negative voltage is applied to the gate electrode, and apparently appears. The threshold voltage (absolute value) decreases.

  Since writing is performed bit by bit unlike erasing, charges can be injected until the threshold value reaches a constant potential while verifying the degree of charge accumulation even if the characteristics of the cells vary. For this reason, the variation in the threshold value of each bit cell can be reduced, and the threshold value of the memory cell becomes positive due to excessive charge accumulation, and depletion is not caused. On the contrary, the apparent threshold value increases in the negative direction by erasing performed on the entire chip or on a block basis, so that the memory cell is not depleted by over-erasing unlike the n-channel flash memory.

  In the present invention, a nanocrystal layer or a non-conductive charge trap layer in which the accumulated charge does not move is used as the charge accumulation layer. As the charge trap layer, a silicon nitride film having a relatively high dielectric constant is generally used. Charge injection is performed from the vicinity of the source and drain. For example, charges are accumulated in the first and second program regions at both ends of the charge accumulation layer by BBHE injection (charge injection by electrons generated by band-to-band tunneling (Band to Band Hot Electron)).

  Charge accumulation in the first and second charge accumulation layers can be performed independently, and the reading can also be performed independently by reversing the reading direction. Can be stored.

  In addition, the BBHE injection generates electrons by applying a high negative voltage to the p-type region (gate or drain) without passing a current between the gate and the drain, which is converted into hot electrons by a high electric field, and this is converted into a gate. It is injected into the charge storage layer by the positive voltage of the electrode. In this way, since channel current does not flow between the source and drain, it is about three orders of magnitude more efficient than channel hot electron injection, and three digits more cells can be programmed simultaneously using a high voltage generation circuit with the same internal power supply. Thus, it is possible to realize writing at a high speed equivalent to three digits.

(7) an n-type well formed in a semiconductor substrate, a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well, a channel region formed between the source and drain, A floating gate formed above the channel region via a tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate formed above the charge storage layer via an insulating film A bit data written in a nonvolatile semiconductor memory device having an electrode,
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the source, and the drain is set to the ground potential. The bit data is read out depending on whether or not there is electrical continuity.

(8) An n-type well formed in a semiconductor substrate, a source and drain that are p + regions formed at predetermined intervals on the surface of the n-type well, a channel region formed between the source and drain, A floating gate formed above the channel region via a tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate formed above the charge storage layer via an insulating film And a method for writing bit data in a nonvolatile semiconductor memory device having electrodes,
By applying a write back gate voltage higher than the read back gate voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the drain to the ground potential, hot by band tunneling near the drain Electrons are generated, and hot data is injected into the charge storage layer to write bit data.

(9) At the time of writing the bit data, in the state where the write back gate voltage is applied to the n-type well, a negative verify read voltage having an absolute value larger than a normal read voltage is applied to the gate electrode, Whether the bit data is written depending on whether the source and drain are conductive when a positive voltage is applied to the drain or when a positive voltage is applied to the source and the drain is set to the ground potential. It is characterized by verifying.

(10) An n-type well formed in a semiconductor substrate, a source and drain that are p + regions formed at predetermined intervals on the surface of the n-type well, a channel region formed between the source and drain, A floating gate formed above the channel region via a tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate formed above the charge storage layer via an insulating film And erasing bit data written in a nonvolatile semiconductor memory device having an electrode,
A negative back gate voltage is applied to the n-type well, a negative high voltage is applied to the gate electrode and the source, and the drain is opened, thereby injecting hot holes from the substrate to the charge storage layer, whereby the charge storage The charge of the layer is erased.

  As described above, according to the present invention, by adopting the p-channel structure, writing by BTHE injection can be performed, the writing efficiency can be improved, and the threshold value is lowered at the time of writing which can be controlled in bit units. Therefore, no overerasing occurs. Further, since the local threshold value in the central portion of the channel region is controlled to be low, the difference between the threshold value at the time of programming and the erasing is large, and data can be retained stably for a long period of time.

  Further, according to the present invention, by applying an appropriate back gate voltage to the n-type well (cell well), the p + region (drain, bit line) may be operated at GND-positive VCC, and the Y system Since the peripheral circuit can be a high-speed VCC circuit, a high-speed write operation can be performed.

<< First Embodiment >>
Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing the structure of a p-channel MONOS memory cell according to the first embodiment of the present invention. This memory cell includes an n-type well (cell well) 12 formed on a p-type semiconductor substrate 11, a p + region (source) 13 and a p + region formed at a predetermined interval near the surface of the n-type well 12. (Drain) 14, channel region 20 formed between these two p-type regions 13, 14, ONO film and gate electrode 18 formed so as to cover channel region 20 above channel region 20 Have.

  The ONO film includes a tunnel oxide film 15 made of silicon oxide, a charge trap layer 16 made of silicon nitride for accumulating injected charges (electrons), and an insulating film 17 made of silicon oxide. The thickness of these three layers is about 2.5 to 5 nm for the tunnel oxide film 15, about 10 nm for the charge trap layer 16, and about 5 nm for the insulating film 17 (see FIG. 3). The gate electrode 18 is made of polysilicon.

This memory cell can be used as a 1-bit / cell or 2-bit / cell memory cell. When used as a 2-bit / cell memory cell, each bit is stored in the right and left regions of the charge trap layer 16 as a virtual ground array (VGA) type configuration. At the time of reading, it is determined which one of the p + regions 13 and 14 is used as the source or drain depending on whether the bit data in the left region or the bit data in the right region is read.
When used as a 1-bit / cell memory cell, the NOR connection is used, and the p + region 13 is fixed to the source and the p + region 14 is fixed to the drain.

  Here, the control of the impurity concentration of the channel region 20 will be described with reference to FIG. In the process of forming the cell well 12, the impurity concentration is controlled to be higher than that of the deep region so that the region on the uppermost surface of the substrate is the channel region 20. In the case of this memory cell, the impurity concentration is higher than that of a normal p-channel MOS transistor. Control is performed so that the concentration is slightly lowered, that is, the threshold value is lowered. Then, an ONO film and a gate electrode 18 are formed, and p + regions 13 and 14 (source and drain) are formed by self-alignment. Then, impurities (P phosphorus and the like) are implanted from an oblique direction, whereby p + in the channel region 20 is formed. Control is performed so that the impurity concentration in the regions (20L, 20R) in the vicinity of the regions 13 and 14 is higher than the impurity concentration in the central portion (20C) of the channel region. Thereby, the local threshold value in the center of the channel region is controlled to be lower than the local threshold value in the vicinity of the p + regions 13 and 14 (see FIG. 2A).

When electrons are injected into the vicinity of the p + regions 13 and 14 by BBHE injection into the memory cell in which the impurity concentration is controlled in this way, only the local threshold value near the p + regions 13 and 14 is lowered by this electron injection, and the channel region The threshold value at the center of 20 is not affected. However, since the threshold value at the center of the channel region 20 is originally controlled to be low as shown in FIG. 2A, the channel region 20 as a whole is caused by the decrease in the local threshold value near the p + regions 13 and 14. Can be sufficiently lowered to increase the difference between the programmed and non-programmed thresholds (see FIG. 2B). As a result, long-term data retention is possible.
FIG. 2B shows a state where electrons are injected into both the left and right program areas, but the same applies to only one program area.

  When data is erased, the local threshold value in the vicinity of the p + regions 13 and 14 having the most influence on on / off in the channel region 20 rises again, so that the state returns to a state almost the same as the initial state. .

With reference to FIGS. 4 and 5, an example of a memory array in which a plurality of memory cells of FIG. By using this virtual ground array, writing / reading of the 2 bits / cell is possible.
4A is a cross-sectional perspective view of the memory cell array, FIG. 4B is a diagram showing a configuration of one of the memory cells, and FIG. 5 is an equivalent circuit thereof. In FIG. 4A, a broken line is a virtual line indicating the boundary of each memory cell. Further, the equivalent circuit of FIG. 5 shows voltages applied to each word line (gate) and column line (source, drain) at the time of writing.

  A plurality of p + linear regions 30 in the Y direction are formed in stripes at predetermined intervals on the surface of the n-type well 12. The p + linear region 30 is formed across the boundary of the memory cell, and one p + linear region 30 is formed of p-type regions 13 and 14 (source and drain) of two memory cells adjacent in the X direction. Doubles as a column line. This column line functions as both a bit line and a source line depending on the connection with the Y gate.

  The word line 31 is formed in a stripe shape in the X direction so as to be orthogonal to the p + linear region 30 and also serves as the gate electrode 18 above the channel region 20 of each memory cell. An ONO film 32 is formed between the word line 31 and the semiconductor substrate (p + regions 13 and 14 and channel region 20). The ONO film 32 is also formed continuously in the X direction, like the word line 31. In the ONO film 32, the section above the channel region 20 functions as the tunnel oxide film 15, the charge trap layer 16, and the insulating film 17, and the section above the p-type regions 13 and 14 functions as an interlayer insulating film.

  In this embodiment, the ONO film 32 is formed in a stripe shape in the X direction like the word line 31. However, since the ONO film 32 is not a conductive film, it may be formed in the entire memory cell array. By doing so, the processing process for etching the ONO film 32 in a stripe shape can be omitted.

  Thus, in this memory cell array, one p + linear region (column line) 30 also serves as the p-type regions 13 and 14 of two memory cells adjacent in the X direction, so that the memory configuration is simplified. High integration is possible.

<< Second Embodiment >>
Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment relates to the memory potential arrangement during programming, verifying, reading, and erasing, and can be applied to a NOR connection array and a virtual ground array.

  First, the architecture of a nonvolatile semiconductor memory device having a NOR connection array structure will be described with reference to FIG. The NOR connection array may be configured using the memory cell of FIG. 1, but in addition to this, the MONOS structure nonvolatile semiconductor memory, the floating gate type nonvolatile semiconductor memory, and the nano structure in which the channel is not a graded structure may be used. The present invention can be applied to a nonvolatile semiconductor memory that retains charges in a crystal layer.

  In this nonvolatile semiconductor memory device, two cell wells 12 are paired. In each cell well 12, 1kB = 8k (8192) in the X direction × 64 in the Y direction = 512k (524288) memory cells are formed. The number of main bit lines 21 is 8k, and is connected to one sub bit line 25 of the two cell wells 12 through a select gate 24. A latch is connected to each of the 8k main bit lines 21. This latch is used for verifying the write operation. The select gate 24 is formed in a select gate well (n-type well) 20 different from the cell well 12, and is composed of a p-channel MOS transistor. The potential of the select gate well 20 is fixed at VCC. VCC is applied to the gate electrode of the select gate 24 when not selected, and −2.2 V is applied when selected. When −2.2 V is applied, the gate becomes conductive and connects the main bit line 21 to the sub bit line 25 connected to the drain of each memory cell. The word lines connect the gate electrodes of the memory cells in the X direction, and 64 word lines are provided for each cell well 12. The source line is common to 512 k memory cells in each cell well 12.

  In the NOR-connected nonvolatile semiconductor memory device of FIG. 6, operations for writing (program verify), reading, and erasing will be described with reference to FIGS. FIGS. 7 to 18 are diagrams showing potential arrangements and operating principles during write (program verify), read, and erase operations.

  In this nonvolatile semiconductor memory device, by applying an appropriate back gate voltage to the cell well, the bit line that requires the highest speed operation at the time of writing and reading can be operated by GND-VCC. As a result, the bit line control circuit can be configured with a high-speed standard positive VCC circuit, which enables high-speed and simplified configuration.

First, the program operation of the write operation will be described. As described above, in the MONOS memory cell, since the nitride film having low electrical conductivity is used as the charge trap layer 16, the trapped electrons do not move in the film and remain in the trapped position.
Writing (programming) into the memory cell is performed by injecting electrons into the charge trap layer 16. The electrons are injected by BBHE injection by applying a positive and negative high voltage between the gate electrode 18 and the drain (one p + region) 14, and the electrons are injected into the charge trap layer 16.

  Charge injection into the charge trap layer 16 is performed by hot electrons (BBHE: Band-to-Band) by band-to-band tunneling using a high electric field in the depletion layer generated by a high potential difference between the positive potential gate electrode 18 and the negative potential drain 13. tunneling induced hot electron) However, a positive back gate voltage is applied to the cell well 12 so that the drain (= bit line) can be controlled within a positive potential range. As a result, the ground potential of the drain becomes a relatively negative potential.

  Specifically, as shown in FIGS. 7, 8, and 9, + 4V is applied as the back gate voltage Vbgw to the cell well 12, and the drain 13 (bit line) is set to the ground potential (Vdw = 0). Then, 10 V is applied as the gate voltage Vgw to the gate 18 (word line). At this time, VCC (= 1.8 V) is applied to the source 14 (source line).

  With this potential arrangement, a depletion layer region 21 is generated at the junction surface between the drain 13 and the cell well 12 as shown in FIG. 10, and electrons (electrons) / electrons / electron / electron / electron / electron / A hole pair is generated. These electrons are accelerated by a strong electric field in the depletion layer region 21 and become hot electrons having high energy. A part of the voltage is attracted to the positive voltage applied to the gate electrode 18, gets over the tunnel oxide film 15, and is injected into the charge trap layer 16.

This charge injection is performed in a state where the source 13 and the drain 14 are turned off, so that an injection efficiency of about 10 ⁻² can be secured, which is × 10 ³ compared to the conventional channel hot electron injection method. A degree of high efficiency can be obtained.

  In this way, by applying an appropriate positive back gate voltage to the cell well 12 at the time of programming, the drain (bit line) can be controlled in the range of 0 V to VCC (positive potential), and high speed operation can be performed at the time of writing. The required Y-system (bit line) peripheral circuit can be formed by a positive voltage circuit using a high-performance VCC transistor, and high-speed writing and a simplified circuit configuration can be realized.

  Here, the bit writing (injection of electrons) is repeatedly carried out little by little while verifying until the threshold value Vth reaches a predetermined voltage. Therefore, the threshold value of the bit to which writing has been performed is substantially the same. Injecting too much does not deplete the cell.

  Next, with reference to FIG. 7, FIG. 11, and FIG. 12, an operation at the time of verifying among write operations will be described. The verify is an operation that is repeatedly executed alternately with a program in order to check whether the threshold value Vth is a predetermined potential at the time of writing a bit.

In order to realize high-speed writing, it is necessary to switch between the program and verify operations at high speed. In the operation at the time of programming, a back gate voltage is applied to the cell well 12, and it is difficult to change the voltage of the cell well having a large parasitic capacitance from VCC to 4V at a high speed when switching between program and verify. Therefore, in this embodiment, verification is performed while the back gate voltage (4 V) is applied to the cell well 12.
In the verify operation, since the voltage of the cell well 12 remains 4V, the word line 22 (gate electrode 18) is set to −5V, which is higher than a normal read voltage (−2.2V; described later). In this state, after the source line 23 and the bit lines 21 and 25 are charged to VCC, the source line 23 is driven to GND. When the program is completed, since the channel is conducted, the bit lines 21 and 25 are discharged and become GND. When the program is not completed, the bit lines 21 and 25 remain at VCC. The potential of this bit line is taken into the latch, and based on this, the bit line voltage at the time of the next program pulse application is determined. That is, only the bit line whose latched potential is VCC is to inject electrons again at the next program pulse.

  As described above, since the verify is performed in a state where the back gate voltage (4 V) is applied to the cell well 12, the program / verify can be switched at a high speed, and a high-speed bit write can be realized.

  On the other hand, the read (read) operation requires a higher speed operation than the write operation, and it is necessary to switch not only the bit line but also the word line, so that the back gate voltage applied to the cell well 12 is a normal voltage. (VCC = 1.8V), and the read voltage applied to the word line is -2.2V.

  Next, the read operation will be described with reference to FIGS. At the time of reading, VCC is applied to the cell well 12 as a back gate voltage, and VCC (= 1.8 V) is applied to the source line 23 (source 13). After the bit lines 21 and 25 (drain 14) to be read are set to GND, the word line 22 (gate 18) to be read is changed from VCC to the read voltage Vgr = −2.2V. As a result, the source 14 is equivalently grounded, the drain is at a potential of −1.8V, and the gate voltage is −4V. In this potential arrangement, the bit lines 21 and 25 rise to VCC if the cell is in the programmed state, and remain GND if the cell is in the non-programmed state.

  Next, the erase operation will be described. As an erasing method, there are an FN (Fowler-Nordheim) tunnel extraction and a substrate hot hole injection erasing method.

  First, extraction by the FN tunnel will be described with reference to FIGS. Erasing is performed in units of 12 cell wells. A high voltage of −13 V is applied to the word line 22 (gate 18) while the cell well 12 and the source line 23 remain at VCC, and the bit lines 21 and 25 (drain 14) are set to GND. As a result, a large potential difference is generated between the gate 18 and the drain 14, and electrons trapped in the charge trap layer 16 are extracted by jumping to the drain 14 through the tunnel oxide film 15 by the FN tunnel effect.

  Next, an erasing method by substrate hot hole injection will be described with reference to FIGS. The cell well 12 is −1V, the select gate is closed, and the sub bit line 25 (drain 14) is opened. -13V is applied to the word line 22 (gate 18), and -4V is applied to the source line 23 (source 13). By applying the voltage in this way, the p-type substrate 11, the n-well 12 and the source 13 function as a pnp bipolar transistor, and holes are emitted from the p-type semiconductor substrate 11 toward the source 13. On the other hand, since a negative high voltage is applied to the gate electrode 18, some of the holes are attracted in the direction of the gate electrode and pass through the tunnel oxide film 15 and enter the charge trap layer 16. The positive charge of the holes cancels the negative charge of the electrons, and as a result, the charge of the charge trap layer 16 is erased.

  With the above-described potential arrangement and operation, the Y-system circuit can be configured with a high-speed circuit operating at GND-VCC.

  In the case of a virtual ground array (VGA), programming, verifying, reading, and erasing may be performed with a potential arrangement as shown in FIG. In this figure, the drain (Drain) and the source (Source) do not indicate the p + regions 13 and 14 in a fixed manner, but the side on which bit data is written (injecting electrons) or the side on which bit data is read is the drain, and vice versa. The functions assigned to the p + regions 13 and 14 so that the side becomes the source are shown.

  This virtual ground array may be the one shown in FIGS. 4 and 5, and holds charges in a MONOS structure nonvolatile semiconductor memory, a floating gate type nonvolatile semiconductor memory, and a nanocrystal layer whose channel is not a graded structure. The present invention can also be applied to a virtual ground array composed of a nonvolatile semiconductor memory or the like.

  Further, a memory cell having a structure in which the trapped charge does not move, for example, a MONOS structure nonvolatile semiconductor memory shown in FIGS. 4 and 5, or a normal (channel not having a graded structure) MONOS structure nonvolatile semiconductor memory In the case of using a memory or a non-volatile semiconductor memory that holds charges in the nanocrystal layer, it is possible to store 2 bits / cell by using both ends of the gate length. In this case, in addition to applying positive and negative high voltages between the gate electrode 18 and the left p + region 14 to inject electrons into the right program region 16R, the cell is reversed left and right so that the left p + Using region 13 as a drain, positive and negative high voltages are applied between gate electrode 18 and p + region 13 to inject electrons into left program region 16L.

  By doing so, electrons injected into the left program area 16L or the right program area 16R do not move to the opposite side, so that writing can be performed independently in the left and right program areas 16L, R. At the time of reading, the left and right program regions 16L and R are selected depending on which of the p + regions 13 and 14 functions as a drain / source, that is, which one is applied with a read voltage and which is grounded. be able to.

As described above, in the second embodiment, the following two points are realized in order to realize high-speed writing.
(1) By applying an appropriate back gate voltage to the cell well 12, all the operations can be performed with the voltage applied to the bit line between 0 V and VCC (1.8 V). As a result, a Y-system circuit that plays an important role for high-speed writing can be formed with a high-performance VCC transistor, and since no negative voltage is handled, no special circuit configuration is required.

  (2) Further, a back gate voltage of about 4 V is applied at the time of writing, but the verification is performed in this back gate voltage application state. This makes it possible to switch between program and verify at high speed without using a large-capacity power supply circuit.

<< Other Embodiments >>
Further, by applying the back gate voltage to the cell well as in this embodiment, it becomes possible to greatly improve the scalability of the gate length (shortening of the gate). In the NOR type structure, it is 0.1 μm or less. Realizing the gate length is no longer difficult. This is because the voltage applied between the drain and the source is lowered by applying the back gate voltage, and the Vth (absolute value) is equivalently increased due to the back gate effect, so that it is difficult to punch through.

  As described above, the memory cell of the MONOS structure can store 2 bits / cell. However, in order to manufacture the memory cell of 2 bits / cell, left and right independent program areas are secured. The gate length must be as long as possible. On the other hand, the gate length can be significantly shortened by applying an appropriate back gate voltage to the cell well as described above, so that a 1-bit / cell memory cell is manufactured with a short gate length. Even so, a storage density close to 2 bits / cell can be realized.

  Further, even in this case, the following excellent effects can be obtained as compared with a normal floating gate type flash memory having a single bit configuration (for example, disclosed in JP-A-9-8153).

  (1) The MONOS type is more resistant to defective defects than the floating gate type. That is, in the floating gate type, even if the tunnel oxide film (bottom oxide film) has a defect that causes a very small leak, all the charge in the floating gate flows out due to this leak, and the stored contents are lost. It will be broken. In a non-volatile memory that requires storage for 10 years, an allowable leak level is very small compared to other devices (for example, a leak level that is 8 orders of magnitude smaller than that of a DRAM is required), and is extremely small. It has become very difficult to realize a process that does not cause defects.

  On the other hand, in the MONOS type, charges are trapped in an insulating film called a nitride film, so even if a small defect exists in the upper or lower oxide film, the charge near the defect may flow out. However, all the charges will not flow out. Therefore, the MONOS structure has a much higher resistance to defects than the floating gate type.

(2) The MONOS structure is more scalable than the floating gate type.
In the floating gate type, since the floating gate is capacitively coupled to the four electrodes of the source, drain, substrate, and control gate, at the time of writing, an unselected cell (drain) connected to the same bit line as the memory cell to be written. In the cell in which a write voltage (= a relatively high voltage) is applied to the gate and 0 V is applied to the gate, the potential of the floating gate rises due to capacitive coupling between the drain and the floating gate. Therefore, according to scaling (reducing the gate length), the proportion of capacitive coupling with the drain increases relatively, and the proportion of capacitive coupling with the substrate via the channel decreases. The potential rise cannot be ignored, and the unselected cells are weakly turned on at the time of writing. As a result, the leakage current flowing through the channel of the non-selected cell at the time of writing increases, and eventually the writing operation cannot be performed normally.

  On the other hand, in the MONOS structure, since there is no floating gate which is a conductive film that causes capacitive coupling, there is no such problem, so scaling (even if the gate length is shortened), The problem of increase does not occur.

  In this specification, a memory cell having a p-channel MONOS structure is described. However, the above graded channel structure can be similarly applied to an n-channel MONOS memory cell, and the potential arrangement shown in FIG. Etc. can be applied to an n-channel MONOS memory cell with the polarity reversed. Furthermore, these can be applied to the twin MONOS memory cell shown in FIG.

  Here, FIG. 20 is a diagram showing a structure of a P-channel twin MONOS memory cell. In the twin MONOS memory cell, sidewall control gates 205L, R and nitride films 206L, R are formed on both sides of a gate (word gate) 207 of a normal MOS transistor by a sidewall technique. By trapping charges in each, the channel length can be shortened while realizing the storage of 2 bits / cell.

The figure which shows the structure of the p channel MONOS memory cell of the grading channel structure which is embodiment of this invention The figure explaining the threshold voltage of the p channel MONOS memory cell The figure explaining the relationship between the thickness of the tunnel oxide film of the same p channel MONOS memory cell, and an upper insulating layer Structure diagram when virtual ground array is configured by arranging the same p-channel MONOS memory cells in XY Equivalent circuit diagram of the virtual ground array Equivalent circuit diagram showing the architecture when the p-channel MONOS memory cells are arranged in XY to form a NOR connection array Diagram showing potential arrangement at the time of writing (programming), verifying, erasing, and reading in the NOR connection array Diagram showing potential arrangement in equivalent circuit during programming Diagram showing potential arrangement in cross-sectional structure during programming The figure explaining the principle of the program by BTHE injection The figure which shows the electric potential arrangement in the equivalent circuit at the time of verification Diagram showing potential arrangement in cross-sectional structure during verification The figure which shows the electric potential arrangement | positioning in the equivalent circuit at the time of reading The figure which shows the electric potential arrangement | positioning in the cross-sectional structure at the time of reading The figure which shows the electric potential arrangement | positioning in the equivalent circuit at the time of erasing by FN tunnel The figure which shows the electric potential arrangement | positioning in the cross-sectional structure at the time of erasing by FN tunnel The figure which shows the electric potential arrangement in the equivalent circuit at the time of erasing by substrate hot electron injection The figure which shows the electric potential arrangement in the section structure at the time of erasing by substrate hot electron injection The figure showing potential arrangement at the time of writing (programming), verifying, erasing and reading when storing 2 bits / cell in the virtual ground array The figure which shows the structure of a P channel twin MONOS memory cell The figure which shows the structure of the conventional N channel MONOS memory cell The figure explaining the threshold voltage of the p channel MONOS memory cell which does not have a graded channel structure

Explanation of symbols

11 ... p-type semiconductor substrate 12 ... n-type well (cell well)
13, 14 ... p + region (source, drain)
15 ... Tunnel oxide film 16 ... Charge trap layer (nitride film)
17 ... Upper insulating layer 18 ... Gate 20 ... Select gate well (n-type well)
21 ... Main bit line 22 ... Word line 23 ... Source line 24 ... Select gate 25 ... Sub bit line

Claims (10)

An n-type well formed in a semiconductor substrate;
A first p + region and a second p + region formed at predetermined intervals on the n-type well surface;
A channel region formed between the first and second p + regions;
A charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc. formed above the channel region via a tunnel oxide film;
A gate electrode formed above the charge storage layer via an insulating film;
A non-volatile semiconductor memory device comprising:
Of the channel region, an impurity concentration in an intermediate region between the first p + region and the second p + region is set to be higher than an impurity concentration in a region in the vicinity of the first p + region and / or the second p + region. A non-volatile semiconductor memory device characterized by being lowered.   A first program region which is a partial region on the first p + region side of the charge storage layer, and a second program region which is a partial region on the second p + region side of the charge storage layer; The nonvolatile semiconductor memory device according to claim 1, wherein 2-bit data is written by accumulating charges independently of each other. The nonvolatile semiconductor memory device according to claim 1 or 2 is used as a memory cell,
A non-volatile semiconductor memory device comprising a plurality of memory cells arranged in an XY matrix and connected in a virtual ground system. An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed at predetermined intervals on the surface of the n-type well, and formed between the first and second p + regions. A channel region, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel oxide film, and an insulating film above the charge storage layer A bit data written in a nonvolatile semiconductor memory device having a gate electrode,
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the first p + region, and the second p + region is grounded The bit data in the first program area is read depending on whether or not the first and second p + areas are electrically connected when the potential is applied.
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the second p + region, and the first p + region is grounded A read method for a nonvolatile semiconductor memory device, comprising: reading bit data in the second program area depending on whether or not the first and second p + areas are conductive when a potential is applied. An n-type well formed in a semiconductor substrate, a first p + region and a second p + region formed at predetermined intervals on the surface of the n-type well, and formed between the first and second p + regions. A channel region, a charge storage layer such as a nanocrystal layer and a non-conductor charge trap layer formed above the channel region via a tunnel oxide film, and an insulating film above the charge storage layer A bit data written in a nonvolatile semiconductor memory device having a gate electrode,
By applying a write back gate voltage higher than the read back gate voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the first p + region to the ground potential, the first p + Generating hot electrons by band-to-band tunneling in the vicinity of the region, injecting the hot electrons into the first program region of the charge storage layer, and writing the first bit;
By applying a write back gate voltage higher than the read back gate voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the second p + region to the ground potential, the second p + Non-volatile semiconductor memory device, wherein hot electrons are generated by band-to-band tunneling in the vicinity of the region, and the hot bits are injected into the second program region of the charge storage layer to write the second bit. Method. At the time of writing the first bit, with the write back gate voltage applied to the n-type well, a negative verify read voltage having an absolute value larger than a normal read voltage is applied to the gate electrode, and the first p + Verifying whether the first bit is written depending on whether the first and second p + regions are conductive when a positive voltage is applied to the region and the second p + region is set to the ground potential;
At the time of writing the second bit, with the write back gate voltage applied to the n-type well, the verify read voltage is applied to the gate electrode, a positive voltage is applied to the second p + region, 6. The nonvolatile memory according to claim 5, wherein whether or not the second bit is written is verified depending on whether or not the first and second p + regions are conductive when the p + region is set to a ground potential. Semiconductor memory device writing method. An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A floating gate formed above the tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate electrode formed above the charge storage layer via an insulating film, A method for reading bit data written in a nonvolatile semiconductor memory device having:
A positive read back gate voltage is applied to the n-type well, a negative read voltage is applied to the gate electrode, the same voltage as the read back gate voltage is applied to the source, and the drain is set to the ground potential. A reading method of a nonvolatile semiconductor memory device, wherein bit data is read out depending on whether or not there is electrical continuity. An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A floating gate formed above the tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate electrode formed above the charge storage layer via an insulating film, A method for writing bit data in a nonvolatile semiconductor memory device having:
By applying a write back gate voltage higher than the read back gate voltage to the n-type well, applying a positive high voltage to the gate electrode, and setting the drain to the ground potential, hot by band tunneling near the drain A writing method of a nonvolatile semiconductor memory device, wherein electrons are generated and the hot electrons are injected into the charge storage layer to write bit data.   When writing the bit data, with the write back gate voltage applied to the n-type well, a negative verify read voltage having an absolute value larger than the normal read voltage is applied to the gate electrode, and the source is set to the ground potential. When the positive voltage is applied to the drain or when the positive voltage is applied to the source and the drain is set to the ground potential, whether the bit data is written is verified by whether or not the source and the drain are conductive. 9. A writing method for a nonvolatile semiconductor memory device according to claim 8, wherein: An n-type well formed in a semiconductor substrate; a source and drain which are p + regions formed at predetermined intervals on the surface of the n-type well; a channel region formed between the source and drain; and the channel region A floating gate formed above the tunnel oxide film, a charge storage layer such as a nanocrystal layer, a non-conductor charge trap layer, etc., and a gate electrode formed above the charge storage layer via an insulating film, A method of erasing bit data written in a nonvolatile semiconductor memory device having
A negative back gate voltage is applied to the n-type well, a negative high voltage is applied to the gate electrode and the source, and the drain is opened, thereby injecting hot holes from the substrate to the charge storage layer, whereby the charge storage A method for erasing a nonvolatile semiconductor memory device, wherein the charge of the layer is erased.

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