CN102543890B - Method for improving erasing speed of SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing strained silicon technology - Google Patents
Method for improving erasing speed of SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing strained silicon technology Download PDFInfo
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- CN102543890B CN102543890B CN201210047380.5A CN201210047380A CN102543890B CN 102543890 B CN102543890 B CN 102543890B CN 201210047380 A CN201210047380 A CN 201210047380A CN 102543890 B CN102543890 B CN 102543890B
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Abstract
The invention discloses a method for improving an erasing speed of an SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing a strained silicon technology. The method is characterized by comprising the following steps of: after manufacturing a sidewall of a grid electrode on a P-type substrate forming a plurality of shallow channel isolation regions, (1) depositing a baffle layer to cover a transistor; (2) etching to remove the baffle layer covering above an NMOS (N-channel Metal Oxide Semiconductor) region to expose the NMOS region; (3) etching silicon of active regions on two sides of the grid electrode of the NMOS region; (4) depositing silicon carbide at the active regions through a selectivity epitaxy process; and (5) carrying out high-temperature annealing to enable the silicon carbide to generate tensile stress on a channel. According to the method for increasing the erasing speed of the SONOS by utilizing the strained silicon technology, disclosed by the invention, an energy band of silicon is broken up so that effective mass of electron in the direction of the channel is reduced; simultaneously, energy valley scattering probability of the electron is also reduced, and mobility of the electron of the SONOS unit transistor is remarkably improved, thus the SONOS programming efficiency and speed of a hot electron injection mechanism are improved.
Description
Technical field
The present invention relates to silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) memory, particularly, relate to a kind of method of utilizing strained silicon technology to improve the erasable speed of SONOS.
Background technology
The basic functional principle of non-volatile semiconductor memory is stored charge in the gate medium of a MOSFET.The device that wherein electric charge is stored in the discrete trapping centre of a suitable dielectric layer is called as electric charge capture device.The most frequently used in this class device is silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) memory.
The main two kinds of memory mechanisms that are used for the storage data of flash memory cells are that channel hot electron (CHE) injects and F-N tunneling effect.Channel hot electron injects and is considered to after long-term circulation, remaining quite reliable, and reason is that it does not apply very large stress on tunnel oxide.But the shortcoming of CHE is that programming efficiency is low.It is to accelerate electronics with the transverse electric field of raceway groove that channel hot electron injects, and when electronics is accelerated to while obtaining a high-energy that is enough to overcome potential barrier, hot electron injection will occur.When programming, drain and gate all will apply relatively high voltage, and drain electrode is directly connected with voltage source, and grid voltage depends on capacitive coupling.For effective programming, transistor should be biased in saturation region, makes in drain terminal depletion region, to set up large transverse electric field through the electronics of pinch-off point.This bias state of grid makes near channel inversion layer source wider, and along with convergence pinch-off point, it is narrower that channel inversion layer becomes so that through the electronics of pinch-off point in the high electric field in drain terminal depletion region by strong acceleration.When portions of electronics obtains enough high-energy like this, just there is hot electron and inject, but be that effectively therefore hot electron injection programming efficiency is not high owing to only having sub-fraction raceway groove to programming.
Therefore, provide a kind of method of erasable speed and SONOS cell transistor of high erasable speed that utilizes strained silicon technology to improve SONOS just to seem particularly important.
Summary of the invention
The electron mobility the object of the invention is by making SONOS cell transistor improves, and injects machine-processed SONOS programming efficiency and speed thereby realize raising hot electron.
The present invention discloses a kind of method of utilizing strained silicon technology to improve the transistorized erasable speed of SONOS, wherein, on the P type substrate that forms some shallow channel isolation areas, has made after the side wall of grid, also comprises the steps:
Step 1, precipitation barrier layer covers described transistor;
Step 2, the barrier layer that etching removal covers top, territory, nmos area exposes territory, described nmos area;
Step 3 is carried out carbon ion injection on the P type substrate between described grid both sides and shallow channel isolation area;
Step 4, carries out high annealing, makes described carborundum produce tensile stress to raceway groove.
Above-mentioned method, wherein, after completing steps 4, also comprises the step of removing barrier layer.
According to another aspect of the present invention, also disclose a kind of SONOS cell transistor that adopts above-mentioned method to make, comprised some paired PMOS and NMOS, described NMOS comprises:
The P type silicon substrate with some paired active areas, is formed with raceway groove between every a pair of active area;
Grid, is positioned at described raceway groove top, has silica-silicon-nitride and silicon oxide layer between the side wall of described grid, on described silica-silicon-nitride and silicon oxide layer, is polysilicon;
The peripheral both sides of described paired active area are respectively arranged with shallow channel isolation area;
Wherein, paired active area, the active area of described NMOS comprises carborundum.
Above-mentioned SONOS cell transistor, wherein, described paired active area comprises source electrode and drain electrode.
Inject machine-processed SONOS programming efficiency and speed in order to improve hot electron, the present invention sets about from the angle that improves channel carrier mobility.Carrier mobility can determine by equation μ=qt/m*, and wherein q is electron charge, and m* is charge carrier effective mass, and t is the average life span between double scattering, and therefore probability of scattering is 1/t.
The present invention utilizes stress silicon technology, after SONOS side wall forms, return and carve rear depositing silicon carbide at source-drain area, by annealing, source is leaked SONOS cell channel is produced to tensile stress, being with of silicon divided, and the result of division causes reducing along the electron effective mass of channel direction, and the energy valley probability of scattering of electronics also reduces simultaneously, the electron mobility of SONOS cell transistor is significantly improved, inject machine-processed SONOS programming efficiency and speed thereby improve hot electron.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified part parts, for same parts, only indicated wherein part, those skilled in the art can understand in conjunction with embodiment part.
Fig. 1 shows according to the present invention, the profile after SONOS unit component side wall forms;
Fig. 2 is that territory, nmos area window is opened, and carries out carbon ion and injects the schematic diagram that forms carborundum; And
Fig. 3, for by high-temperature annealing process, makes the carborundum of source and drain areas produce the schematic diagram of tensile stress to raceway groove.
Embodiment
Below in conjunction with the drawings and the specific embodiments, the present invention is further elaborated.Embodiment described herein is only for explaining the present invention, the protection range being not intended to limit the present invention.
In conjunction with reference to figure 1 and Fig. 2, disclose the present invention and utilized strained silicon technology to improve the method for the erasable speed of SONOS, in Fig. 1, on the P type substrate 104 that forms some shallow channel isolation areas 105, make after the side wall 102 of grid 101, also comprise the steps:
Step 1, precipitation barrier layer (not shown in figure 1) covers described transistor;
Step 2, the barrier layer that etching removal covers top, territory, nmos area exposes territory, described nmos area, in this step, first spin coating photoresist is on described barrier layer, carry out photoetching, those skilled in the art can, in conjunction with step described in existing techniques in realizing, not repeat them here again;
Step 3 is carried out carbon ion injection, as shown in Figure 2 on the P type substrate 104 between described grid 101 both sides and shallow channel isolation area 105;
Step 4, carries out high annealing, makes described carborundum produce tensile stress (as shown in Figure 3) to raceway groove.
The present invention divides being with of silicon, the result of division causes reducing along the electron effective mass of channel direction, the energy valley probability of scattering of electronics also reduces simultaneously, the electron mobility of SONOS cell transistor is significantly improved, inject machine-processed SONOS programming efficiency and speed thereby improve hot electron.
Further, in above-mentioned method, after completing steps 4, also comprise the step of removing barrier layer.
Referring again to Fig. 3, the SONOS cell transistor of the erasable speed of height of the present invention comprises as shown in the figure: comprise that some paired PMOS(are attached not shown) and NMOS, described NMOS comprises: have the P type silicon substrate 104 of some paired active areas 103, be formed with raceway groove (not shown in Fig. 3) between every a pair of active area 103; Grid 101, is positioned at described raceway groove top, has silica-silicon-nitride and silicon oxide layer 111(ONO layer between the side wall 102 of described grid 101), on described silica-silicon-nitride and silicon oxide layer 111, be polysilicon 121; The peripheral both sides of described paired active area 103 are respectively arranged with shallow channel isolation area 105; Wherein, the paired active area 103, active area 103 of described NMOS comprises carborundum (SiC).
Particularly, in the SONOS cell transistor of the described erasable speed of height, described paired active area 103 comprises source electrode and drain electrode.
The present invention improves by the electron mobility that makes SONOS cell transistor, injects machine-processed SONOS programming efficiency and speed thereby realize raising hot electron.
Those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, and such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (2)
1. utilize strained silicon technology to improve a method for the transistorized erasable speed of SONOS, it is characterized in that, on the P type substrate that forms some shallow channel isolation areas, made after the side wall of grid, also comprise the steps:
Step 1, precipitation barrier layer covers described transistor;
Step 2, spin coating photoresist is on described barrier layer, and the barrier layer that etching removal covers top, territory, nmos area exposes territory, described nmos area;
Step 3 is carried out carbon ion injection on the P type substrate between described grid both sides and shallow channel isolation area;
Step 4, carries out high annealing, makes carborundum produce tensile stress to raceway groove, removes described barrier layer, and wherein, described SONOS transistor comprises some paired PMOS and NMOS, and described NMOS comprises:
The P type silicon substrate with some paired active areas, is formed with raceway groove between every a pair of active area;
Grid, is positioned at described raceway groove top, has silica-silicon-nitride and silicon oxide layer between the side wall of described grid, on described silica-silicon-nitride and silicon oxide layer, is polysilicon;
The peripheral both sides of described paired active area are respectively arranged with shallow channel isolation area;
The paired active area of described NMOS comprises carborundum.
2. SONOS cell transistor according to claim 1, is characterized in that, described paired active area comprises source electrode and drain electrode.
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| CN111463217B (en) * | 2020-04-09 | 2023-04-18 | 中国科学院微电子研究所 | Charge trapping memory and manufacturing method thereof |
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| US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
| US7112495B2 (en) * | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
| US7923363B2 (en) * | 2004-09-15 | 2011-04-12 | Nxp B.V. | SONOS memory device with optimized shallow trench isolation |
| KR100719219B1 (en) * | 2005-09-20 | 2007-05-16 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| US8900980B2 (en) * | 2006-01-20 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect-free SiGe source/drain formation by epitaxy-free process |
| CN102130179B (en) * | 2010-01-20 | 2013-04-24 | 上海华虹Nec电子有限公司 | Silicon-oxide-nitride-oxide-silicon (SONOS) device |
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