JP2007142450A - Manufacturing method of nonvolatile semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a manufacturing method of a nonvolatile semiconductor storage having a floating gate electrode with high charge holding capacity. <P>SOLUTION: The manufacturing method of the nonvolatile semiconductor storage comprises a step (a) of forming a tunnel insulating film made of a silicon oxide film on a semiconductor region in a substrate by performing heat treatment in atmosphere containing oxygen and hydrogen; a step (b) of diffusing nitrogen into the tunnel insulating film by performing heat treatment in atmosphere containing N<SB>2</SB>O or NO; a step (c) of diffusing hydrogen into the tunnel insulating film by performing heat treatment in a temperature range of 300-950°C in atmosphere containing hydrogen; a step (d) of forming a memory gate electrode section 8 on the tunnel insulating film after the step (c); and a step (e) of forming two impurity diffusion regions 30, 31 having a conductivity type opposite to that of the semiconductor region, by introducing impurities into a region positioned at both the sides of a floating gate electrode in the semiconductor region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and more particularly to measures for improving the reliability of a nonvolatile semiconductor memory device.

  Conventionally, a nonvolatile semiconductor memory device represented by a flash EEPROM basically has a structure in which a floating gate electrode for accumulating charges is interposed between a control gate electrode functioning as a gate electrode of a MIS transistor and a channel region. To do. In the most general structure, the information of the floating gate electrode is read by detecting whether the MIS transistor is turned on or not according to the presence or absence of charge in the floating gate electrode. Here, in this nonvolatile semiconductor memory device, in order to rewrite information in the floating gate electrode, charge is injected into the floating gate electrode by using tunneling of charges in the tunnel insulating film below the floating gate electrode, or floating. It is possible to extract charges from the gate electrode. Here, although an oxide film is generally used as the tunnel insulating film, it is empirically known that the gate insulating film deteriorates with time when charges pass through the tunnel oxide film. Therefore, many efforts have been made to improve the reliability of the tunnel insulating film.

  Hereinafter, a conventional nonvolatile semiconductor memory device in which measures for improving the reliability of the tunnel insulating film are taken will be described with reference to FIGS.

  First, in the step shown in FIG. 13A, an element isolation region 102 and an active region 103 surrounded by the element isolation region 102 are formed on the p-type semiconductor substrate 101. Next, in a step shown in FIG. 13B, a tunnel oxide film 104 having a thickness of about 10 nm is formed on the surface of the semiconductor substrate 101. Next, in the step shown in FIG. 13C, after the first polysilicon film, the ONO film, and the second polysilicon film are sequentially volumed on the substrate, the respective films are patterned to thereby form the floating gate electrode 105. Then, the gate electrode portion 108 including the interelectrode insulating film 106 and the control gate electrode 107 is formed. Here, the ONO insulating film is a laminated film composed of an oxide film, a nitride film, and an oxide film. Finally, in the step shown in FIG. 13D, sidewalls 109 are formed on the side surfaces of the tunnel insulating film 104, the floating gate electrode 105, the interelectrode insulating film 106, and the control gate electrode 107. Then, ion implantation is performed using the gate electrode portion 108 and the sidewall 109 as a mask, and the n-type source diffusion layer 110 and the n-type drain diffusion layer 111 are formed in regions located on both sides of the gate electrode portion 108 in the semiconductor substrate 101. Form.

  In the above prior art, the write operation is performed by injecting electrons from the entire channel region, which is a region located below the tunnel insulating film 104 in the semiconductor substrate 101, into the floating gate electrode 105 through the tunnel insulating film 104. . This electron injection uses, for example, FN tunneling. Further, extraction of electrons from the floating gate electrode 105 is performed, for example, by movement from the floating gate electrode 105 to the channel region of the semiconductor substrate 101. At this time, it is known that by repeatedly performing FN tunneling of electrons through the tunnel insulating film 104, defects such as trap sites gradually increase in the tunnel insulating film 104, resulting in deterioration of reliability. ing. Therefore, a promising measure for diffusing nitrogen into the oxide film constituting the tunnel insulating film has been proposed in order to suppress the occurrence of defects such as such trap sites.

  However, as a result of repeated experiments by the inventors, it has been found that it is difficult to effectively suppress the deterioration of the tunnel insulating film even if the improvement that nitrogen is diffused in the tunnel insulating film is added. It was. Then, when the cause was investigated, the following facts became clear.

  In general, when nitrogen is diffused into a silicon oxide film which is a thermal oxide film, the film quality of the tunnel insulating film on the substrate side is improved, but the film quality of the tunnel insulating film on the floating gate side is not improved. This is because nitrogen is distributed at a relatively high concentration in the tunnel insulating film near the interface with the semiconductor substrate, but almost all nitrogen is distributed in the tunnel insulating film near the interface with the floating gate electrode. Because there is no.

  By the way, in the conventional heat treatment for forming a thermal oxide film, pyrooxidation using oxygen gas and hydrogen gas is generally used for forming the oxide film. The oxide film formed by the pyro-oxidation contains a lot of hydrogen, but this hydrogen terminates dangling bonds in the oxide film, thereby reducing the stress generated in the underlying semiconductor substrate, It is known that it contributes to maintaining good transistor characteristics. That is, it is known that a silicon oxide film formed by a pyro-oxidation method can exhibit higher reliability than a silicon oxide film formed by dry oxidation using only oxygen gas.

  However, according to the experiments of the present inventors, hydrogen introduced into the thermal oxide film by pyro-oxidation is diffused outward during the process of diffusing nitrogen in the thermal oxide film (nitrogen diffusion process). The data was obtained. This experimental data will be described later. The deterioration of the film quality of the tunnel insulating film that has been subjected to the nitrogen diffusion treatment as described above is, according to the inventor's estimation, that hydrogen existing on the surface of the oxide film diffuses outward due to high-temperature heat treatment, and the vicinity of the oxide film surface This is thought to be due to the generation of charge trapping sites. Hereinafter, the mechanism of deterioration of the tunnel insulating film considered by the present inventors will be described.

  FIG. 14 is a band diagram showing an energy band structure at the time of electron injection in a cross section passing through the floating gate electrode, the tunnel insulating film, and the semiconductor substrate. As shown in the figure, when electrons are injected from the semiconductor substrate to the floating gate electrode using FN tunneling, in a region near the floating gate electrode in the tunnel insulating film, which is a thermal oxide film in which nitrogen is diffused. When dangling bonds due to the loss of hydrogen are present, it is considered that holes are captured at those sites. On the other hand, as described above, nitrogen is diffused in a high concentration in a region close to the semiconductor substrate in the tunnel insulating film, so that the dangling bond from which hydrogen has escaped is terminated by nitrogen and the probability that holes are captured Is considered low.

  FIG. 15 is a band diagram showing an energy band structure at the time of reading operation in a cross section passing through the floating gate electrode, the tunnel insulating film, and the semiconductor substrate when holes are captured. As shown in the figure, when holes are trapped in a region near the floating gate electrode in the tunnel insulating film, the energy band structure changes so that the potential decreases at a part of the conduction band edge of the tunnel insulating film. Therefore, it is considered that the reliability of the memory cell occurs, for example, the charge (electrons) accumulated in the floating gate electrode easily leaks to the semiconductor substrate side by tunneling and the memory retention capability is reduced. Although electrons are also captured, it is considered that electrons are widely distributed in the gate insulating film.

  The present invention takes measures to effectively prevent the deterioration of the tunnel insulating film based on the elucidation of the cause of the decrease in reliability in the tunnel insulating film constituted by diffusing nitrogen in the thermal oxide film as described above. Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can improve the reliability of the memory cell by suppressing the deterioration of the charge retention capability of the floating gate electrode.

The method for manufacturing a nonvolatile semiconductor memory device of the present invention includes a step (a) of forming a tunnel insulating film made of a silicon oxide film on a semiconductor region in a substrate by performing heat treatment in an atmosphere containing oxygen and hydrogen. And a step (b) of diffusing nitrogen in the tunnel insulating film by performing heat treatment in an atmosphere containing N ₂ O or NO, and a heat treatment in a temperature range of 300 ° C. to 950 ° C. in an atmosphere containing hydrogen. A step (c) of diffusing hydrogen into the tunnel insulating film, and a memory gate electrode comprising a floating gate electrode, an interelectrode insulating film, and a control gate electrode on the tunnel insulating film after the step (c). Forming step (d) and introducing impurities into regions located on both sides of the floating gate electrode in the semiconductor region, And a step (e) to form a net things diffusion region.

  With this method, the charge trapping sites in the silicon oxide film are reduced by the hydrogen diffusion process in the step (c), and this silicon oxide film functions as a tunnel insulating film below the floating gate electrode. Accordingly, a nonvolatile semiconductor device having a floating gate electrode with reduced charge leakage from the tunnel insulating film and high charge holding capability is formed.

  In addition, since the step (b) of diffusing nitrogen into the tunnel insulating film is included, the silicon oxide film in which nitrogen is diffused functions as a tunnel insulating film below the floating gate electrode, so that electrons are extracted from the floating gate electrode. A highly reliable tunnel insulating film with few defects is obtained.

  According to the nonvolatile semiconductor memory device of the present invention, it is possible to improve the reliability of the memory cell by suppressing the deterioration of the charge retention capability of the floating gate electrode.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIGS. 1A to 1E are cross-sectional views showing manufacturing steps of the nonvolatile semiconductor memory device (memory cell) in the first embodiment of the present invention.

  First, in the step shown in FIG. 1A, an n-type well 1a is formed in a silicon substrate 1 containing a p-type impurity by ion implantation of an n-type impurity, and a memory cell is formed in the n-type well 1a. An element isolation region 2 for partitioning the active region 3 to be formed is formed.

  Next, in the step shown in FIG. 1B, the surface portion of the active region 3 is oxidized by a known pyro-oxidation method to form a silicon oxide film 4a having a thickness of about 7 nm.

Subsequently, in the step shown in FIG. 1C, lamp annealing is performed at 1050 ° C. in an N ₂ O atmosphere, so that nitrogen penetrates into the silicon oxide film 4a and diffuses in the silicon oxide film. The thickness of the silicon oxide film is increased to 10 nm to obtain a nitrogen-containing silicon oxide film 4x having a thickness of about 10 nm. At this time, nitrogen is unevenly distributed in the nitrogen-containing silicon oxide film 4x so as to have a high concentration near the n-type well 1a.

  Next, in the step shown in FIG. 1D, a first polysilicon film, an ONO film (silicon oxide film / silicon nitride film / silicon oxide film laminated film), and a second film are formed on the nitrogen-containing silicon oxide film 4x. After sequentially depositing the polysilicon films, a resist mask is formed by photolithography and dry etching is performed to form the second polysilicon film, the ONO film, the first polysilicon film, and the nitrogen-containing silicon oxide film 4x. By sequentially patterning, a tunnel insulating film 4, a floating gate electrode 5, an interelectrode insulating film 6 made of an ONO film, and a control gate electrode 7 are formed. Through this process, a memory gate electrode portion 8 including a floating gate electrode 5, an interelectrode insulating film 6 and a control gate electrode 7 is formed on the tunnel insulating film 4. Further, a gate insulating film 14, a select gate electrode 15, a dummy interelectrode insulating film 16, and a dummy control gate electrode 17 are interposed between the plates on the side of the memory gate electrode portion 8. Form. Through this process, a select gate electrode portion 18 including a select gate electrode 15, a dummy inter-electrode insulating film 16, and a dummy control gate electrode 17 is formed on the gate insulating film 14. The select gate electrode 15 and the dummy control gate electrode 17 are partially short-circuited so as to be electrically connected to each other, and a voltage is directly applied to the select gate electrode 15 by applying a voltage to the dummy control gate electrode 17. It is comprised so that it may apply.

  Next, in the step shown in FIG. 1E, sidewalls 9 and 19 having a thickness of about 100 nm are formed on the side surfaces of the memory gate electrode portion 8 and the select gate electrode portion 18, respectively. , A region located on the side of the floating gate electrode 5 in the n-type well 1a by implanting p-type impurities into the n-type well 1a using the select gate electrode portion 18 and the sidewalls 9 and 19 as a mask. P-type source diffusion layer 10, p-type drain diffusion layer 11 in the region located beside the select gate electrode 15, and p-type source diffusion layer 11 in the region located between the floating gate electrode 5 and the select gate electrode 15. The mold intermediate diffusion layers 12 are respectively formed.

  Next, FIGS. 2A and 2B are cross-sectional views for explaining a method of writing and erasing the memory cell formed in this embodiment.

  As shown in FIG. 2A, when writing into this memory cell (Program), for example, the p-type source diffusion layer 10 is opened, and a negative intermediate voltage (− 5.5V), a negative large voltage (−7.5V) at the select gate electrode 15, a positive high voltage (+ 10V) at the control gate electrode 7, and a positive low voltage Vcc (at the n-type well 1a). +3.0 V) is applied. By such voltage setting, the slope of the pn junction between the n-type well 1a and the p-type intermediate diffusion layer 12 becomes steep, so that holes are band-band from the n-type well 1a to the p-type intermediate diffusion layer 12. It moves at high speed by inter-tunneling. At this time, holes collide with electrons in the depletion layer (region near the boundary between the n-type well 1a and the intermediate diffusion layer 12), thereby causing hot electrons (band-band tunneling). Current induced hot electrons) are generated, and the hot electrons are attracted to the floating gate electrode 5 capacitively coupled to the control gate electrode 7, and a portion of the tunnel insulating film 4 close to the p-type intermediate diffusion layer 12 is tunneled. It is injected into the floating gate electrode 5. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 2B, when erasing the memory cell, the p-type drain diffusion layer 11 is opened and a positive high voltage (+10 V) is applied to the p-type source diffusion layer 10. ), A positive high voltage (+ 10V) is applied to the select gate electrode 15, a negative high voltage (−7.5) is applied to the control gate electrode 7, and a positive high voltage (+ 10V) is applied to the n-type well 1a. Apply. With such a voltage setting, electrons in the floating gate electrode 5 are drawn by the high voltage of the n-type well 1a, tunneled over the entire surface of the tunnel insulating film 4, and drawn out to the n-type well 1a. As a result, erase is performed.

  Here, according to the structure of the nonvolatile semiconductor memory device (memory cell) of the present embodiment, nitrogen is diffused in the tunnel insulating film 4 and becomes thicker in the tunnel insulating film 4 near the n-type well 1a. Thus, the film quality in this part is good. Therefore, when electrons tunnel through substantially the entire tunnel insulating film 4 from the floating gate electrode 5, the occurrence of defects in the portion of the tunnel insulating film 4 near the n-type well 1a is suppressed.

  On the other hand, in the portion close to the floating gate electrode 5 in the tunnel insulating film 4, a charge trapping site due to the outward diffusion of hydrogen can occur as in the above-described conventional nonvolatile semiconductor memory device. However, in the memory cell of the present embodiment, at the time of writing, hot electrons induced by a band-to-band tunnel current in a region near the boundary between the n-type well 1a and the p-type intermediate diffusion layer 12 are transferred to the tunnel insulating film 4. In order to pass only a local region in the vicinity of the p-type intermediate diffusion layer 12 of the tunnel insulating film 4, holes are trapped in the charge trapping site during tunneling. It is limited only to a local region in the vicinity of. That is, the area where holes can be captured is extremely small compared to the area of the entire interface between the tunnel insulating film 4 and the floating gate electrode 5. Therefore, the amount of electrons leaking from the site where the hole structure is changed by trapping holes at the charge trapping site is very small. Therefore, in the nonvolatile semiconductor memory device (memory cell) of the present embodiment, the characteristics of the band-to-band tunneling current induced hot electron injection method, that is, the difference in threshold voltage between writing and erasing can be increased, and the number of rewrites can be increased. In many cases, it is possible to suppress a decrease in the charge retention capability of the floating gate electrode 5 due to the generation of a new charge trapping site while taking advantage of the short writing time.

  Further, according to the manufacturing method of the present embodiment, rapid annealing can be performed by using lamp annealing (rapid heating / cooling treatment by halogen lamp irradiation or the like) when diffusing nitrogen into the tunnel insulating film 4. Nitrogen can be diffused while maintaining the impurity profile in the n-type well 1a. Thereby, variation and fluctuation of the threshold voltage can be suppressed.

  In the above embodiment, a structure in which the select gate electrode 15 is not provided may be used. In that case, the band-to-band tunneling current-induced hot electrons in the boundary region with the p-type drain diffusion layer 11 instead of the p-type intermediate diffusion layer 12 are generated in the vicinity of the p-type drain diffusion layer 11 in the tunnel insulating film 4. Only through the local region, the floating gate electrode 5 is injected. Therefore, the same effect as this embodiment can be exhibited.

  In FIG. 2A, the p-type drain diffusion layer 11 may be opened and a negative voltage (−5.5 V) may be applied to the p-type source diffusion layer 10. In that case, band-to-band tunneling current-induced hot electrons in the vicinity of the p-type source diffusion layer 10 pass only through a local region in the vicinity of the p-type source diffusion layer 10 in the tunnel insulating film 4 and float. It will be injected into the gate electrode 5. Therefore, the same effect as this embodiment can be exhibited.

(Second Embodiment)
FIGS. 3A to 3E are cross-sectional views showing the manufacturing process of the nonvolatile semiconductor memory device (memory cell) in the second embodiment of the present invention.

  First, in the step shown in FIG. 3A, an element isolation region 2 for partitioning an active region 3 in which a memory cell is formed in the p-type silicon substrate 1 is formed on the p-type silicon substrate 1.

Next, in the step shown in FIG. 3B, the surface portion of the active region 3 is oxidized by a known pyro-oxidation method to form a silicon oxide film having a thickness of about 7 nm. Subsequently, by performing lamp annealing at 1050 ° C. in an N ₂ O atmosphere, nitrogen is penetrated into the silicon oxide film to diffuse nitrogen in the silicon oxide film, and the thickness of the silicon oxide film is increased to 10 nm. Thus, a nitrogen-containing silicon oxide film 4x having a thickness of about 10 nm is obtained. At this time, nitrogen is unevenly distributed in the nitrogen-containing silicon oxide film 4x so as to have a high concentration in a portion close to the silicon substrate 1.

  Next, in the step shown in FIG. 3C, on the nitrogen-containing silicon oxide film 4x, a first polysilicon film, an ONO film (a laminated film of silicon oxide film / silicon nitride film / silicon oxide film) and a second film are formed. After sequentially depositing the polysilicon films, a resist mask is formed by photolithography and dry etching is performed to form the second polysilicon film, the ONO film, the first polysilicon film, and the nitrogen-containing silicon oxide film 4x. By sequentially patterning, a tunnel insulating film 4, a floating gate electrode 5, an interelectrode insulating film 6 made of an ONO film, and a control gate electrode 7 are formed. Through this process, a memory gate electrode portion 8 including a floating gate electrode 5, an interelectrode insulating film 6 and a control gate electrode 7 is formed on the tunnel insulating film 4.

Next, sidewalls 9 having a thickness of about 100 nm are formed on the side surfaces of the memory gate electrode portion 8 in the step shown in FIG. Next, a photoresist mask Re1 is formed on the substrate to cover a portion extending from the vicinity of the center of the memory gate electrode portion 8 to the region where the drain diffusion layer is to be formed. The photoresist film Re1, the memory gate electrode portion 8 Then, using the side wall 9 as a mask, arsenic ions are implanted into the p-type silicon substrate 1 under conditions of an acceleration energy of about 40 keV and a dose of about 2 × 10 ¹⁵ atoms · cm ⁻³ , and phosphorus ions A deep n-type source diffusion layer 20 is formed by implanting into the p-type silicon substrate 1 under conditions of an acceleration energy of about 70 keV and a dose of about 4 × 10 ¹⁵ atoms · cm ⁻³ .

Next, in the step shown in FIG. 3E, a photoresist mask Re2 is formed on the substrate to cover a portion extending from the vicinity of the center of the memory gate electrode portion 8 to the n-type source diffusion layer 20, and this photoresist film Ar 2 ions are implanted into the p-type silicon substrate 1 under conditions of an acceleration energy of about 40 keV and a dose of about 3 × 10 ¹⁴ atoms · cm ^{−3 using} Re 2, the memory gate electrode portion 8 and the sidewall 9 as a mask. Thus, a shallow n-type drain diffusion layer 21 is formed.

  Next, FIGS. 4A and 4B are cross-sectional views for explaining a method of writing and erasing the memory cell formed in the present embodiment.

  As shown in FIG. 4A, when writing (Program) to this memory cell, for example, the p-type silicon substrate 1 is grounded, and a voltage of 0 V is applied to the n-type source diffusion layer 20. A positive intermediate voltage (5 V) is applied to the drain diffusion layer 21, and a positive high voltage (+10 V) is applied to the control gate electrode 7. With such a voltage setting, electrons flow from the n-type source diffusion layer 20 to the n-type drain diffusion layer 21, but since the impurity concentration profile becomes steep in the vicinity of the n-type drain diffusion layer 21, the electrons are accelerated, Electron / hole pairs are generated by collisions with. At this time, high-speed hot electrons (channel hot electrons) generated in the region near the boundary between the p-type silicon substrate 1 and the n-type drain diffusion layer 21 are transferred to the floating gate electrode 5 capacitively coupled to the control gate electrode 7. As a result, a portion of the tunnel insulating film 4 close to the n-type drain diffusion layer 21 is tunneled and injected into the floating gate electrode 5. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 4B, when erasing the memory cell, the p-type silicon substrate 1 is grounded, the n-type drain diffusion layer 21 is opened, and the control gate electrode 7 is opened. A voltage of 0 V is applied to the n-type source diffusion layer 20 and a positive high voltage (+12 V) is applied to the n-type source diffusion layer 20. By such voltage setting, electrons in the floating gate electrode 5 are attracted by the high voltage of the n-type source diffusion layer 20, and FN tunneling is performed on a portion of the tunnel insulating film 4 close to the n-type source diffusion layer 20. The n-type source diffusion layer 20 is extracted. As a result, erase is performed.

  However, in the voltage setting of FIG. 2B, even when a large negative voltage (−8 V) is applied to the control gate electrode 7, electrons are applied even when a positive low voltage (+5 V) is applied to the n-type source diffusion layer 20. Can be extracted to the n-type source diffusion layer 20, and the erase operation can be performed smoothly.

  Here, according to the structure of the nonvolatile semiconductor memory device (memory cell) of the present embodiment, nitrogen is diffused in the tunnel insulating film 4, and is deeper in the portion near the p-type silicon substrate 1 in the tunnel insulating film 4. Therefore, the film quality in this part is good. Therefore, when electrons tunnel the tunnel insulating film 4 from the floating gate electrode 5, the occurrence of defects in the portion of the tunnel insulating film 4 near the p-type silicon substrate 1 (n-type source diffusion layer 20) is suppressed. .

  On the other hand, in the portion close to the floating gate electrode 5 in the tunnel insulating film 4, a charge trapping site due to the outward diffusion of hydrogen can occur as in the above-described conventional nonvolatile semiconductor memory device. However, in the memory cell of the present embodiment, at the time of writing, since hot electrons pass only through a local region in the vicinity of the n-type drain diffusion layer 21 in the tunnel insulating film 4, holes are charged during tunneling. The location captured by the capture site is limited to only a local region in the vicinity of the n-type drain diffusion layer 21 in the tunnel insulating film 4. That is, the area where holes can be captured is extremely small compared to the area of the entire interface between the tunnel insulating film 4 and the floating gate electrode 5. Therefore, the amount of electrons leaking from the site where the hole structure is changed by trapping holes at the charge trapping site is very small. Therefore, in the nonvolatile semiconductor memory device (memory cell) of the present embodiment, the hole is trapped at the charge trapping site while exhibiting the advantage of the channel hot electron injection method that the control circuit can be simplified. A decrease in charge retention capability can be suppressed.

  In particular, in the present embodiment, by forming the n-type drain diffusion layer 21 shallow and forming a steep concentration profile at the pn junction, the acceleration with respect to hot electrons can be increased during writing, Since the n-type source diffusion layer 20 has a so-called DD structure (double drain structure) by introducing two impurities, phosphorus having a high diffusibility and arsenic having a low diffusivity, the n-type source diffusion layer 20 has a high level in the erasure. There is an advantage that the pressure resistance when a voltage (10 V) is applied is improved.

  Further, the effect of using lamp annealing when diffusing nitrogen into the tunnel insulating film 4 is the same as that of the first embodiment.

(Third embodiment)
FIG. 5A to FIG. 5E are cross-sectional views showing manufacturing steps of the nonvolatile semiconductor memory device (memory cell) in the third embodiment of the present invention.

  First, in the step shown in FIG. 5A, an element isolation region 2 for partitioning an active region 3 in which a memory cell is formed in the p-type silicon substrate 1 is formed on the p-type silicon substrate 1.

  Next, in the step shown in FIG. 5B, the surface portion of the active region 3 is oxidized by a known pyro-oxidation method to form a silicon oxide film having a thickness of about 7 nm. Subsequently, a heat treatment at 950 ° C. is performed in an NO atmosphere, so that nitrogen penetrates into the silicon oxide film and nitrogen is diffused in the silicon oxide film to form a nitrogen-containing silicon oxide film 4y. At this time, almost no increase in the thickness of the nitrogen-containing silicon oxide film 4y as in the first and second embodiments is observed, and it remains at about 7 nm. However, as in the first and second embodiments, nitrogen is unevenly distributed in the nitrogen-containing silicon oxide film 4y so as to have a high concentration at a portion close to the silicon substrate 1.

  Next, in the step shown in FIG. 5C, the first polysilicon film, the ONO film (silicon oxide film / silicon nitride film / silicon oxide film laminated film) and the second film are formed on the nitrogen-containing silicon oxide film 4y. After sequentially depositing the polysilicon films, a resist mask is formed by photolithography and dry etching is performed to form the second polysilicon film, the ONO film, the first polysilicon film, and the nitrogen-containing silicon oxide film 4y. By sequentially patterning, a tunnel insulating film 4, a floating gate electrode 5, an interelectrode insulating film 6 made of an ONO film, and a control gate electrode 7 are formed. Through this process, a memory gate electrode portion 8 including a floating gate electrode 5, an interelectrode insulating film 6 and a control gate electrode 7 is formed on the tunnel insulating film 4.

Next, in the step shown in FIG. 5D, a sidewall 9 having a thickness of about 100 nm is formed on the side surface of the memory gate electrode portion 8. Next, a photoresist mask Re3 is formed on the substrate to cover a portion extending from the vicinity of the center of the memory gate electrode portion 8 to the region where the drain diffusion layer is to be formed. The photoresist film Re3, the memory gate electrode portion 8 Then, using the sidewall 9 as a mask, arsenic ions are implanted into the p-type silicon substrate 1 under the conditions of an acceleration energy of about 40 keV and a dose of about 3 × 10 ¹⁴ atoms · cm ⁻³ to form a shallow n-type source A diffusion layer 30 is formed.

Next, in the step shown in FIG. 5E, a photoresist mask Re4 is formed on the substrate so as to cover a portion extending from the vicinity of the central portion of the memory gate electrode portion 8 to the n-type source diffusion layer 30, and this photoresist film. Ar 4 ions are implanted into the p-type silicon substrate 1 under the conditions of acceleration energy of about 40 keV and dose of about 2 × 10 ¹⁵ atoms · cm ^{−3 using} Re 4, memory gate electrode portion 8 and sidewall 9 as a mask. Further, a deep n-type drain diffusion layer 31 is formed by implanting phosphorus ions into the p-type silicon substrate 1 under conditions of an acceleration energy of about 70 keV and a dose of about 4 × 10 ¹⁵ atoms · cm ^−3. To do.

  Next, FIGS. 6A and 6B are cross-sectional views for explaining a method of writing and erasing the memory cell formed in this embodiment.

  As shown in FIG. 6A, when writing to this memory cell (Program), for example, the p-type silicon substrate 1 is grounded, the n-type source diffusion layer 30 is opened, and the n-type drain diffusion layer is formed. A positive and relatively high voltage (+6 V) is applied to 31 and a large negative voltage (−8 V) is applied to the control gate electrode 7. With such a voltage setting, electrons in the floating gate electrode 5 are extracted to the n-type drain diffusion layer 31 by FN tunneling of the tunnel insulating film 4 near the n-type drain diffusion layer 31. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 6B, when erasing the memory cell, the n-type drain diffusion layer 31 is opened and the p-type silicon substrate 1 and the n-type source diffusion layer 30 are formed. A negative large voltage (−8 V) is applied, and a positive high voltage (+8 V) is applied to the control gate electrode 7. By such voltage setting, electrons in the p-type silicon substrate 1 are attracted to the floating gate electrode 5 capacitively coupled to the control gate electrode 7, and FN tunneling is performed from almost the entire channel region to the entire tunnel insulating film 4. Then, it is injected into the floating gate electrode 5. As a result, erase is performed.

  Here, according to the structure of the nonvolatile semiconductor memory device (memory cell) of the present embodiment, nitrogen is diffused in the tunnel insulating film 4, and is deeper in the portion near the p-type silicon substrate 1 in the tunnel insulating film 4. Therefore, the film quality in this part is good. Therefore, when electrons tunnel through substantially the entire tunnel insulating film 4 from the floating gate electrode 5, the occurrence of defects in the portion of the tunnel insulating film 4 near the p-type silicon substrate 1 (n-type drain diffusion layer 31) It is suppressed.

  On the other hand, in the step shown in FIG. 5B, when the nitrogen-containing silicon oxide film 4y is formed by the nitrogen diffusion process, the diffusion of nitrogen is performed at about 950 ° C. Therefore, the floating in the nitrogen-containing silicon oxide film 4y is performed. Even in a portion close to the gate electrode 5, new generation of charge trapping sites due to outward diffusion of hydrogen during the nitrogen diffusion treatment can be suppressed as follows.

  FIG. 7 is a graph showing the nitrogen diffusion temperature dependence of the amount of trapped holes on the surface of the tunnel insulating film 4 (region close to the floating gate electrode 5) obtained by patterning the nitrogen-containing silicon oxide film 4y of this embodiment. is there. In the figure, the horizontal axis represents the nitrogen diffusion temperature (° C.) during the nitrogen diffusion treatment in the NO atmosphere, and the vertical axis represents the gate voltage shift amount (mV) that serves as an index of the hole trapping amount. That is, when a constant voltage is applied to the gate, it recovers after the gate voltage decreases with time, and the shift amount (mV) from the initial value of the minimum value at that time is evaluated as the hole trapping amount. Yes. As shown in the figure, at the nitrogen diffusion temperature of 950 ° C. or lower in the nitrogen diffusion treatment, the hole trapping amount is significantly reduced compared with the nitrogen diffusion temperature of 1050 ° C., and the nitrogen diffusion temperature is 950 ° C. or lower. The hole trapping amount at is substantially equal to the value of the hole trapping amount of the silicon oxide film not subjected to the nitrogen diffusion treatment. That is, at a nitrogen diffusion temperature of 950 ° C. or less, no new charge trapping site is formed near the oxide film surface. As a result, the amount of holes captured when electrons are injected into the floating gate electrode 5 hardly increases as compared with a silicon oxide film not subjected to nitrogen diffusion treatment. Therefore, it is possible to suppress a decrease in the charge retention capability of the floating gate electrode 5 due to the nitrogen diffusion treatment. However, in order to effectively diffuse nitrogen into the silicon oxide film, it is preferable to perform the heat treatment under conditions of 800 ° C. or higher.

  In the memory cell formed by the manufacturing process of this embodiment, there is no new generation of the charge trapping site in the tunnel insulating film 4 due to the nitrogen diffusion process. Therefore, the memory cell structure and the memory cell write / erase method are not affected. Regardless of this, the charge retention capability can be maintained high. Specifically, it is possible to employ the memory cell structure and the write / erase method described in the first and second embodiments and each embodiment described later.

  The injection (writing or erasing) of electrons into the floating gate electrode 5 may not be limited to the vicinity of the drain diffusion layer or the source diffusion layer. That is, by performing heat treatment at 950 ° C. or lower in an atmosphere containing nitrogen, it becomes possible to use electron injection from the entire channel region on the substrate surface using the FN tunnel current to the floating gate.

  However, as shown in FIG. 6B of the present embodiment, electrons are injected by injecting (writing or erasing) electrons into the floating gate electrode 5 from the entire channel region using the FN tunnel current. The large area allows electrons to be efficiently injected into the floating gate. As a result, a high-speed write operation or erase operation can be realized.

  In this embodiment, a memory cell having a shallow n-type source diffusion layer 30 and a deep n-type drain diffusion layer 31 is used. For example, an n-type impurity is simultaneously injected into the source diffusion layer and the drain diffusion layer. Even in the formed memory cell having the n-type source diffusion layer and the n-type drain diffusion layer having the same depth, the tunnel diffusion film 4 is subjected to the nitrogen diffusion treatment according to the present embodiment to obtain the present embodiment. The same effect can be obtained.

(Fourth embodiment)
FIGS. 8A to 8E are cross-sectional views showing manufacturing steps of the nonvolatile semiconductor memory device (memory cell) in the fourth embodiment of the present invention.

  First, in the process shown in FIG. 8A, an element isolation region 2 for partitioning an active region 3 in which a memory cell is formed in the p-type silicon substrate 1 is formed on the p-type silicon substrate 1.

Next, in the step shown in FIG. 8B, the surface portion of the active region 3 is oxidized by a known pyro-oxidation method to form a silicon oxide film having a thickness of about 7 nm. Subsequently, by performing lamp annealing at 1050 ° C. in an N ₂ O atmosphere, nitrogen is penetrated into the silicon oxide film to diffuse nitrogen in the silicon oxide film, and the thickness of the silicon oxide film is increased to 10 nm. Thus, a nitrogen-containing silicon oxide film 4z having a thickness of about 10 nm is obtained. At this time, nitrogen is unevenly distributed in the nitrogen-containing silicon oxide film 4z so as to have a high concentration in a portion close to the silicon substrate 1.

  Thereafter, in the present embodiment, the heat formed by diffusing hydrogen into the nitrogen-containing silicon oxide film 4z by performing heat treatment at 750 ° C. in an atmosphere containing hydrogen gas and oxygen gas to release the hydrogen. A nitrogen-containing silicon oxide film 4z is formed by inactivating the trap sites and the charge trap sites that existed before the nitrogen diffusion treatment. Performing this processing is the greatest feature of the manufacturing process in the present embodiment. At this time, it is preferable to perform heat treatment in an atmosphere containing hydrogen gas and oxygen gas in a temperature range of 300 ° C. to 950 ° C. If the temperature exceeds 950 ° C., a new charge trapping site may be formed, and if it is less than 300 ° C., a sufficient amount of hydrogen may not be introduced.

  Note that, by performing heat treatment in an atmosphere containing fluorine instead of an atmosphere containing hydrogen, the fluorine may be diffused in the nitrogen-containing silicon oxide film and the charge trapping site may be deactivated by fluorine. .

  Next, in the step shown in FIG. 8C, on the nitrogen-containing silicon oxide film 4z, the first polysilicon film, the ONO film (silicon oxide film / silicon nitride film / silicon oxide film laminated film) and the second film are formed. After sequentially depositing the polysilicon films, a resist mask is formed by photolithography and dry etching is performed to form the second polysilicon film, the ONO film, the first polysilicon film, and the nitrogen-containing silicon oxide film 4z. By sequentially patterning, a tunnel insulating film 4, a floating gate electrode 5, an interelectrode insulating film 6 made of an ONO film, and a control gate electrode 7 are formed. Through this process, a memory gate electrode portion 8 including a floating gate electrode 5, an interelectrode insulating film 6 and a control gate electrode 7 is formed on the tunnel insulating film 4.

Next, a sidewall 9 having a thickness of about 100 nm is formed on the side surface of the memory gate electrode portion 8 in the step shown in FIG. Next, a photoresist mask Re5 is formed on the substrate to cover a portion extending from the vicinity of the central portion of the memory gate electrode portion 8 to the region where the drain diffusion layer is to be formed. The photoresist film Re5, the memory gate electrode portion 8 Then, using the sidewall 9 as a mask, arsenic ions are implanted into the p-type silicon substrate 1 under the conditions of an acceleration energy of about 40 keV and a dose of about 3 × 10 ¹⁴ atoms · cm ⁻³ to form a shallow n-type source A diffusion layer 30 is formed.

Next, in the step shown in FIG. 8E, a photoresist mask Re6 is formed on the substrate to cover a portion extending from the vicinity of the center of the memory gate electrode portion 8 to the n-type source diffusion layer 30, and this photoresist film Ar6 ions are implanted into the p-type silicon substrate 1 under the conditions of acceleration energy of about 40 keV and dose of about 2 × 10 ¹⁵ atoms · cm ^{−3 using} Re 6, memory gate electrode portion 8 and sidewall 9 as a mask. Further, a deep n-type drain diffusion layer 31 is formed by implanting phosphorus ions into the p-type silicon substrate 1 under conditions of an acceleration energy of about 70 keV and a dose of about 4 × 10 ¹⁵ atoms · cm ^−3. To do.

  Since the write or erase operation for the memory cell formed by the manufacturing process of this embodiment is the same as that of the third embodiment, description thereof is omitted.

  Here, according to the structure of the nonvolatile semiconductor memory device (memory cell) of the present embodiment, nitrogen is diffused in the tunnel insulating film 4, and is deeper in the portion near the p-type silicon substrate 1 in the tunnel insulating film 4. Therefore, the film quality in this part is good. Therefore, when electrons pass through the tunnel insulating film 4 from the floating gate electrode 5 by tunneling, generation of defects in a portion of the tunnel insulating film 4 near the p-type silicon substrate 1 (n-type drain diffusion layer 31) is generated. It is suppressed.

  In particular, in the manufacturing method of the present embodiment, in the step shown in FIG. 8B, the portion near the surface of the nitrogen-containing silicon oxide film 4z is formed by the outward diffusion of hydrogen during the first nitrogen diffusion treatment. In addition to the new charge trapping sites, the charge trapping sites (such as dangling bonds) that existed in the silicon oxide film before the nitrogen diffusion treatment are also treated by heat treatment in an atmosphere containing hydrogen (or fluorine). Combined with hydrogen (or fluorine) to render it inactive. Therefore, charge trap sites can be reduced more effectively than in the third embodiment. As a result, the amount of holes captured when electrons are injected into the floating gate electrode 5 can be further reduced as compared with a silicon oxide film not subjected to nitrogen diffusion treatment. Therefore, the charge retention capability of the floating gate electrode 5 in the memory cell can be improved.

  In the memory cell formed by the manufacturing process of this embodiment, there is no new generation of the charge trapping site in the tunnel insulating film 4 due to the nitrogen diffusion process. Therefore, the memory cell structure and the memory cell write / erase method are not affected. Regardless of this, the charge retention capability can be maintained high. Specifically, it is possible to employ the memory cell structure and the write / erase method described in the first and second embodiments and each embodiment described later.

  In the present embodiment, hydrogen is diffused into the nitrogen-containing silicon oxide film 4z by performing heat treatment at 750 ° C. in an atmosphere containing hydrogen gas and oxygen gas in the step shown in FIG. 8B. However, if the atmosphere contains hydrogen (or fluorine), the same effects as in the present embodiment can be obtained even if other types of gases are used. Further, the same effect as this embodiment can be obtained by performing heat treatment at a temperature lower than 750 ° C. in an atmosphere containing hydrogen (or fluorine), for example, about 400 ° C., or performing plasma treatment in an atmosphere containing hydrogen or fluorine. Is obtained.

  Furthermore, in this embodiment, immediately after nitrogen is introduced into the silicon oxide film and changed to the nitrogen-containing silicon oxide film 4z, the nitrogen-containing silicon oxide film 4z is heat-treated in an atmosphere containing hydrogen. Although hydrogen is introduced into the nitrogen-containing silicon oxide film 4z, other methods are possible as the introduction method. For example, a nitrogen-containing silicon oxide film is formed by a high-temperature nitrogen diffusion process by the same process as in the first and second embodiments, and the first polysilicon film for forming the floating gate electrode 5 is formed. Hydrogen (or fluorine) is introduced into the first polysilicon film during deposition, or ion implantation of ions containing hydrogen (or fluorine) in the first polysilicon film after the first polysilicon film is deposited As a result, hydrogen (or fluorine) is introduced into the first polysilicon film in advance. Thereafter, hydrogen (or fluorine) is diffused from the first polysilicon film into the nitrogen-containing silicon oxide film by heat treatment, or the memory gate electrode portion 8 and the tunnel insulating film 4 are patterned, and then heat treatment is performed to form the floating gate. Even if hydrogen (or fluorine) introduced into the electrode 5 is diffused into the tunnel insulating film 4, the same effect as in the present embodiment can be obtained.

  In this embodiment, a memory cell having a shallow n-type source diffusion layer 30 and a deep n-type drain diffusion layer 31 is used. For example, an n-type impurity is simultaneously injected into the source diffusion layer and the drain diffusion layer. Even in the formed memory cell having the n-type source diffusion layer and the n-type drain diffusion layer having the same depth, the diffusion process of hydrogen (or fluorine) of the present embodiment is performed on the tunnel insulating film 4. The same effect as this embodiment can be obtained.

  Further, in the memory cell formed by the manufacturing process of this embodiment, there is no new generation of charge trapping sites in the tunnel insulating film 4 due to the nitrogen diffusion process, so that the memory cell structure and the memory cell writing / erasing method Regardless of the case, the charge retention capability can be maintained high. Specifically, it is possible to employ the memory cell structure and the write / erase method described in the first and second embodiments and each embodiment described later.

-Modification of the fourth embodiment-
FIGS. 16A to 16E are cross-sectional views showing manufacturing steps of the nonvolatile semiconductor memory device (memory cell) in the modification of the fourth embodiment of the present invention.

  First, in the step shown in FIG. 16A, an element isolation region 2 for partitioning an active region 3 in which a memory cell is formed in the p-type silicon substrate 1 is formed on the p-type silicon substrate 1.

Next, in the step shown in FIG. 16B, the surface portion of the active region 3 is oxidized by a known pyro-oxidation method to form a silicon oxide film having a thickness of about 7 nm. Subsequently, by performing lamp annealing at 1050 ° C. in an N ₂ O atmosphere, nitrogen is penetrated into the silicon oxide film to diffuse nitrogen in the silicon oxide film, and the thickness of the silicon oxide film is increased to 10 nm. Thus, a nitrogen-containing silicon oxide film 4w having a thickness of about 10 nm is obtained. At this time, nitrogen is unevenly distributed in the nitrogen-containing silicon oxide film 4w so as to have a high concentration in a portion close to the silicon substrate 1. At this time, if the processing temperature in the nitrogen atmosphere is 800 ° C. or higher, the nitrogen can be unevenly distributed so as to have a high concentration in a portion near the silicon substrate 1 in the nitrogen-containing silicon oxide film 4w. However, since the charge trapping site may be formed when the temperature is too high, the temperature is preferably 1200 ° C. or lower.

  Thereafter, in the present embodiment, lamp annealing is performed at 600 ° C. in a nitrogen radical atmosphere, so that nitrogen penetrates into the silicon oxide film and nitrogen is diffused in the silicon oxide film. Nitrogen radicals are generated by converting nitrogen and helium mixed gas into plasma in a chamber different from the chamber in which lamp annealing is performed, and are introduced into the chamber in which lamp annealing is performed in an active state. In this method, since nitrogen can be diffused at a low temperature, nitrogen is unevenly distributed in the nitrogen-containing silicon oxide film 4w so as to have a high concentration near the surface.

  FIG. 17 is a diagram showing the concentration distribution of nitrogen in the nitrogen-containing silicon oxide film in this modification. As shown in the figure, nitrogen is distributed in the nitrogen-containing silicon oxide film 4w so as to have a high concentration in both the portion close to the silicon substrate 1 and the portion close to the surface. The processing of such a nitrogen concentration distribution is the greatest feature of the manufacturing process in the present embodiment. At this time, in order to obtain a nitrogen concentration profile as shown in FIG. 17, it is preferable that the nitrogen diffusion treatment temperature by the nitrogen radical is in the range of 300 ° C. to 800 ° C. That is, if the processing temperature at this time is 800 ° C. or higher, the nitrogen introduced by the nitrogen radical treatment easily diffuses into the nitrogen-containing silicon oxide film 4w, but the nitrogen radical treatment contains a sufficient amount of nitrogen. This is because the temperature must be 300 ° C. or higher in order to introduce the silicon oxide film 4w into the surface portion.

  Next, in the step shown in FIG. 16C, the first polysilicon film, the ONO film (silicon oxide film / silicon nitride film / silicon oxide film laminated film) and the second film are formed on the nitrogen-containing silicon oxide film 4w. After sequentially depositing the polysilicon films, a resist mask is formed by photolithography and dry etching is performed to form the second polysilicon film, the ONO film, the first polysilicon film, and the nitrogen-containing silicon oxide film 4w. By sequentially patterning, a tunnel insulating film 4, a floating gate electrode 5, an interelectrode insulating film 6 made of an ONO film, and a control gate electrode 7 are formed. Through this process, a memory gate electrode portion 8 including a floating gate electrode 5, an interelectrode insulating film 6 and a control gate electrode 7 is formed on the tunnel insulating film 4.

Next, a sidewall 9 having a thickness of about 100 nm is formed on the side surface of the memory gate electrode portion 8 in the step shown in FIG. Next, a photoresist mask Re5 is formed on the substrate to cover a portion extending from the vicinity of the central portion of the memory gate electrode portion 8 to the region where the drain diffusion layer is to be formed. The photoresist film Re5, the memory gate electrode portion 8 Then, using the sidewall 9 as a mask, arsenic ions are implanted into the p-type silicon substrate 1 under the conditions of an acceleration energy of about 40 keV and a dose of about 3 × 10 ¹⁴ atoms · cm ⁻³ to form a shallow n-type source A diffusion layer 30 is formed.

Next, in the step shown in FIG. 16E, a photoresist mask Re6 is formed on the substrate so as to cover a portion extending from the vicinity of the central portion of the memory gate electrode portion 8 to the n-type source diffusion layer 30, and this photoresist film Ar6 ions are implanted into the p-type silicon substrate 1 under the conditions of acceleration energy of about 40 keV and dose of about 2 × 10 ¹⁵ atoms · cm ^{−3 using} Re 6, memory gate electrode portion 8 and sidewall 9 as a mask. Further, a deep n-type drain diffusion layer 31 is formed by implanting phosphorus ions into the p-type silicon substrate 1 under conditions of an acceleration energy of about 70 keV and a dose of about 4 × 10 ¹⁵ atoms · cm ^−3. To do.

  Since the write or erase operation for the memory cell formed by the manufacturing process of this modification is the same as that of the third embodiment, the description is omitted.

  Here, according to the structure of the nonvolatile semiconductor memory device (memory cell) of this modification, nitrogen is diffused in the tunnel insulating film 4, and is deeper in the portion near the p-type silicon substrate 1 in the tunnel insulating film 4. Therefore, the film quality in this part is good. Therefore, when electrons pass through the tunnel insulating film 4 from the floating gate electrode 5 by tunneling, generation of defects in a portion of the tunnel insulating film 4 near the p-type silicon substrate 1 (n-type drain diffusion layer 31) is generated. It is suppressed. Further, by lamp annealing at 600 ° C. in a nitrogen radical atmosphere, nitrogen is unevenly distributed so as to be concentrated even in a portion near the surface in the tunnel insulating film 4. As a result, in the vicinity of the surface of the tunnel insulating film 4, not only a new charge trapping site formed by the outward diffusion of hydrogen is deactivated before the lamp annealing treatment at 600 ° C. in a nitrogen radical atmosphere, The amount of holes trapped when electrons are injected into the floating gate electrode 5 by nitrogen can be more effectively reduced than in the fourth embodiment.

  In this modification, a memory cell having a shallow n-type source diffusion layer 30 and a deep n-type drain diffusion layer 31 is used. For example, an n-type impurity is simultaneously injected into the source diffusion layer and the drain diffusion layer. Even in a memory cell having an n-type source diffusion layer and an n-type drain diffusion layer formed with the same depth, the tunnel insulating film 4 is subjected to nitrogen annealing by lamp annealing in the nitrogen radical atmosphere of this modification. By performing the diffusion process, the same effect as in the present modification can be obtained.

  Further, in the memory cell formed by the manufacturing process of this modification, there is no new generation of the charge trapping site in the tunnel insulating film 4 due to the nitrogen diffusion process, so the memory cell structure and the memory cell writing / erasing method Regardless of the case, the charge retention capability can be maintained high. Specifically, it is possible to employ the memory cell structure and the write / erase method described in the first and second embodiments and each embodiment described later.

(Fifth embodiment)
FIGS. 9A and 9B are cross-sectional views for explaining the structure and write / read operations of the nonvolatile semiconductor memory device (memory cell) in the fifth embodiment of the present invention. In this embodiment, the description of the manufacturing process of the memory cell is omitted, but the tunnel insulating film TI is formed through the processing according to the third or fourth embodiment.

  As shown in FIG. 9A, when writing (Program) to this memory cell, for example, the silicon substrate SUB is grounded, the source diffusion layer S and the drain diffusion layer D are opened, and the control gate electrode A positive high voltage (+ 16V) is applied to CG. With such a voltage setting, electrons in the silicon substrate SUB are injected into the floating gate electrode FG through FN tunneling from almost the entire channel region to almost the entire tunnel insulating film TI. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 9B, when erasing the memory cell, the source diffusion layer S and the drain diffusion layer D are opened and a positive high voltage (+ 18V) is applied to the silicon substrate SUB. ) To ground the control gate electrode CG. With such a voltage setting, electrons in the floating gate electrode FG capacitively coupled to the control gate electrode CG are extracted to the entire channel region of the silicon substrate SUB by FN tunneling of the entire tunnel insulating film TI. As a result, erase is performed.

  In the present embodiment, both writing and erasing are performed by electrons FN tunneling the entire tunnel insulating film TI. Therefore, power consumption can be reduced during rewriting. In the memory cell of this embodiment, no charge trapping sites are newly generated in the tunnel insulating film TI by the nitride film processing, or the charge trapping sites are reduced by the subsequent hydrogen (or fluorine) diffusion processing. Therefore, high reliability can be exhibited. Therefore, in the memory cell having the structure and the write / erase method of the present embodiment, the manufacturing process in the first and second embodiments is not applied, and the third nitrogen diffusion treatment at a relatively low temperature or the fourth The manufacturing process for performing the nitrogen diffusion treatment and the hydrogen (or fluorine) diffusion treatment in the embodiment is applied. However, the depths of the source diffusion layer and the drain diffusion layer may be equal, and both may be formed by ion implantation at the same time.

(Sixth embodiment)
FIGS. 10A and 10B are cross-sectional views for explaining the structure and write / read operations of the nonvolatile semiconductor memory device (memory cell) in the sixth embodiment of the present invention. In this embodiment, the description of the manufacturing process of the memory cell is omitted, but the tunnel insulating film TI is formed through the processing according to the third or fourth embodiment. In the present embodiment, a select gate electrode SG is provided in addition to the floating gate electrode FG and the control gate electrode CG.

  As shown in FIG. 10A, when writing (Program) to the memory cell, for example, the silicon substrate SUB is grounded, the source diffusion layer S is opened, and the select gate electrode SG and the drain diffusion layer are formed. A voltage of 0V is applied to D, and a positive high voltage (+ 11V) is applied to the control gate electrode CG. With such a voltage setting, electrons in the silicon substrate SUB are injected into the floating gate electrode FG through FN tunneling from almost the entire channel region to almost the entire tunnel insulating film TI. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 10B, when erasing the memory cell, the source diffusion layer S and the drain diffusion layer D are opened, and a positive high voltage (+ 18V) is applied to the silicon substrate SUB. ), A positive low voltage (+2 V) is applied to the select gate electrode SG, and the control gate electrode CG is grounded. With such a voltage setting, electrons in the floating gate electrode FG capacitively coupled to the control gate electrode CG are extracted to the entire channel region of the silicon substrate SUB by FN tunneling of the entire tunnel insulating film TI. As a result, erase is performed.

  Also in this embodiment, both writing and erasing are performed by electrons FN tunneling the entire tunnel insulating film TI. Therefore, it has the same advantages as the fifth embodiment. In the memory cell of this embodiment, no charge trapping sites are newly generated in the tunnel insulating film TI by the nitride film processing, or the charge trapping sites are reduced by the subsequent hydrogen (or fluorine) diffusion processing. Therefore, high reliability can be exhibited. Therefore, in the memory cell having the structure and the write / erase method of the present embodiment, the manufacturing process in the first and second embodiments is not applied, and the third nitrogen diffusion treatment at a relatively low temperature or the fourth The manufacturing process for performing the nitrogen diffusion treatment and the hydrogen (or fluorine) diffusion treatment in the embodiment is applied. However, the depths of the source diffusion layer and the drain diffusion layer may be equal, and both may be formed by ion implantation at the same time.

(Seventh embodiment)
11A and 11B are cross-sectional views for explaining the structure and write / read operations of the nonvolatile semiconductor memory device (memory cell) in the seventh embodiment of the present invention. In the present embodiment, the description of the manufacturing process of the memory cell is omitted, but the tunnel insulating film TI is hydrogen (or fluorine) without the treatment according to the third embodiment, the treatment according to the fourth embodiment, or the nitrogen diffusion treatment. It is formed through a diffusion treatment. The memory cell of this embodiment has a so-called split gate structure, both the control gate electrode CG and the floating gate electrode CG are provided on the channel region, and the floating gate electrode FG has the channel region and the drain diffusion. The control gate electrode CG straddles the channel region and the source diffusion layer S across the layer D. The interelectrode insulating film EI between the floating gate electrode FG and the control gate electrode CG functions as a tunnel insulating film at the time of erasing. In addition, the memory cell of this embodiment is provided with a shallow source diffusion layer S and a deep drain diffusion layer D formed by the same processing as in the third or fourth embodiment.

  As shown in FIG. 11A, when writing to this memory cell (Program), for example, the silicon substrate SUB is grounded, a voltage of 0 V is applied to the source diffusion layer S, and a positive voltage is applied to the drain diffusion layer D. A high voltage (+12 V) is applied, and a positive low voltage (+2 V) is applied to the control gate electrode CG. With this voltage setting, electrons flowing from the source diffusion layer S toward the drain diffusion layer D are attracted by the floating gate electrode FG capacitively coupled to the control gate electrode CG, and the tunnel insulating film TI is removed from the channel region. Tunneled and injected into the floating gate electrode FG. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 11B, when erasing the memory cell, the silicon substrate SUB is grounded, and a voltage of 0 V is controlled on the source diffusion layer S and the drain diffusion layer D. A positive high voltage (+14 V) is applied to each gate electrode CG. With this voltage setting, electrons in the floating gate electrode FG are attracted to the control gate electrode CG at a high potential, and the interelectrode insulating film EI is tunneled to the control gate electrode CG by FN tunneling. As a result, erase is performed.

  In the present embodiment, the write operation is performed by tunneling electrons through the tunnel insulating film TI. Therefore, the silicon oxide film is subjected to hydrogen (or fluorine) diffusion treatment without being subjected to nitrogen diffusion treatment to form a tunnel insulating film, or the silicon oxide film is subjected to nitrogen diffusion treatment and then subjected to hydrogen (or fluorine) diffusion treatment. By forming the tunnel insulating film TI in the same manner (the manufacturing method of the fourth embodiment), high reliability can be exhibited. This is because the charge trapping sites in the tunnel insulating film are reduced by any of these treatments, so that the charge retention capability of the floating gate electrode FG is improved. However, since the generation of new charge trapping sites during the nitrogen diffusion process can also be suppressed by performing the low temperature nitrogen diffusion process according to the third embodiment, the film quality of the tunnel insulating film TI by the nitrogen diffusion process is improved. On the other hand, it is possible to obtain an effect that it is possible to suppress a decrease in the charge retention capability of the floating gate electrode FG.

(Eighth embodiment)
12A and 12B are cross-sectional views for explaining the structure and write / read operations of the nonvolatile semiconductor memory device (memory cell) according to the eighth embodiment of the present invention. In the present embodiment, the description of the manufacturing process of the memory cell is omitted, but the tunnel insulating film TI is formed of hydrogen (or a non-nitrogen diffusion process) according to the process according to the third embodiment, the process according to the fourth embodiment, or the nitrogen diffusion process. It is formed through a fluorine) diffusion treatment. The memory cell of this embodiment has a so-called split gate structure, both the control gate electrode CG and the floating gate electrode CG are provided on the channel region, and the floating gate electrode FG has the channel region and the drain diffusion. The control gate electrode CG straddles the channel region and the source diffusion layer S across the layer D. Furthermore, the memory cell of this embodiment includes an erase gate electrode EG, and the interelectrode insulating film ERI between the floating gate electrode FG and the erase gate electrode EG functions as a tunnel insulating film at the time of erasing. Further, the memory cell of the present embodiment is provided with the source diffusion layer S and the drain diffusion layer D having the same depth formed by the same processing as that of the first embodiment.

  As shown in FIG. 12A, when writing into this memory cell (Program), for example, the silicon substrate SUB is grounded, the erase gate electrode EG is opened, and a voltage of 0 V is applied to the source diffusion layer S. A positive intermediate voltage (+5 V) is applied to the drain diffusion layer D, and a positive high voltage (+10 V) is applied to the control gate electrode CG. With this voltage setting, hot electrons are generated from electrons flowing from the source diffusion layer S toward the drain diffusion layer D by the same action as in the second embodiment, and the hot electrons are connected to the control gate electrode CG and the capacitance. Pulled by the coupled floating gate electrode FG, the tunnel insulating film TI is tunneled from the channel region and injected into the floating gate electrode FG. Thus, writing (Program) is performed.

  On the other hand, as shown in FIG. 12B, when erasing the memory cell, the silicon substrate SUB and the control gate electrode CG are grounded, and the source diffusion layer S and the drain diffusion layer D are opened. Then, a positive high voltage (+12 V) is applied to the erase gate electrode EG. By such voltage setting, electrons in the floating gate electrode FG are attracted to the erase gate electrode EG having a high potential, and the interelectrode insulating film ERI is tunneled to the erase gate electrode EG by FN tunneling. As a result, erase is performed.

  In the present embodiment, the write operation is performed by tunneling electrons through the tunnel insulating film TI. Therefore, the silicon oxide film is subjected to hydrogen (or fluorine) diffusion treatment without being subjected to nitrogen diffusion treatment to form a tunnel insulating film, or the silicon oxide film is subjected to nitrogen diffusion treatment and then subjected to hydrogen (or fluorine) diffusion treatment. Then, the tunnel insulating film TI is formed (the manufacturing method of the fourth embodiment). By any of these treatments, the charge trapping sites in the tunnel insulating film are reduced, so that the charge retention capability of the floating gate electrode FG is improved. However, since the generation of new charge trapping sites during the nitrogen diffusion process can also be suppressed by performing the low temperature nitrogen diffusion process according to the third embodiment, the film quality of the tunnel insulating film TI by the nitrogen diffusion process is improved. On the other hand, it is possible to obtain an effect that it is possible to suppress a decrease in the charge retention capability of the floating gate electrode FG.

  The nonvolatile semiconductor memory device or the manufacturing method thereof according to the present invention can improve the reliability of the memory cell by suppressing the deterioration of the charge retention capability of the floating gate electrode, and can improve the reliability. Useful as such.

(A)-(e) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device (memory cell) in the 1st Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the method to write and erase to the memory cell formed in this embodiment. (A)-(e) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device (memory cell) in the 2nd Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the method to write and erase to the memory cell formed in 3rd Embodiment. (A)-(e) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device (memory cell) in the 3rd Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the method to write and erase to the memory cell formed in 3rd Embodiment. It is a figure which shows the nitrogen diffusion temperature dependence of the hole trapping amount in the surface of the tunnel insulating film obtained by patterning the nitrogen containing silicon oxide film of 3rd Embodiment. (A)-(e) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device (memory cell) in the 4th Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the structure and write / read operation | movement of the non-volatile semiconductor memory device (memory cell) in the 5th Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the structure and write / read operation | movement of the non-volatile semiconductor memory device (memory cell) in the 6th Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the structure and write / read operation | movement of the non-volatile semiconductor memory device (memory cell) in the 7th Embodiment of this invention. (A), (b) is sectional drawing for demonstrating the structure and write / read operation | movement of the non-volatile semiconductor memory device (memory cell) in the 8th Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing process of the conventional non-volatile semiconductor memory device (memory cell). It is a band figure which shows the energy band structure at the time of the electron injection in the cross section which passes a floating gate electrode, a tunnel insulating film, and a semiconductor substrate. FIG. 4 is a band diagram showing an energy band structure during a read operation in a cross section passing through a floating gate electrode, a tunnel insulating film, and a semiconductor substrate when holes are captured. (A)-(e) is sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device (memory cell) in the modification of the 4th Embodiment of this invention. It is a figure which shows the density | concentration distribution of the nitrogen in the nitrogen containing silicon oxide film in the modification of the 4th Embodiment of this invention.

Explanation of symbols

1 p-type silicon substrate 2 element isolation region 3 active region 4 tunnel insulating film 4a silicon oxide film 4x, 4y, 4z, 4w nitrogen-containing silicon oxide film 5 floating gate electrode 6 interelectrode insulating film 7 control gate electrode 8 memory gate electrode portion DESCRIPTION OF SYMBOLS 9 Side wall 10 p-type source diffusion layer 11 p-type drain diffusion layer 12 p-type intermediate diffusion layer 14 Gate insulating film 15 Dummy floating gate electrode 16 Dummy inter-electrode insulating film 17 Dummy control gate electrode 18 Select gate electrode portion 19 Side wall 20 n-type source diffusion layer 21 n-type drain diffusion layer 30 n-type source diffusion layer 31 n-type drain diffusion layer

Claims (1)

(A) forming a tunnel insulating film made of a silicon oxide film on a semiconductor region in the substrate by performing heat treatment in an atmosphere containing oxygen and hydrogen;
Performing a heat treatment in an atmosphere containing N ₂ O or NO to diffuse nitrogen in the tunnel insulating film (b);
A step (c) of diffusing hydrogen into the tunnel insulating film by performing a heat treatment in a temperature range of 300 ° C. to 950 ° C. in an atmosphere containing hydrogen;
After the step (c), a step (d) of forming a memory gate electrode portion comprising a floating gate electrode, an interelectrode insulating film and a control gate electrode on the tunnel insulating film;
Non-volatile semiconductor memory including a step (e) of introducing impurities into regions located on both sides of the floating gate electrode in the semiconductor region to form two impurity diffusion regions having a conductivity type opposite to that of the semiconductor region Device manufacturing method.

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