JPH07183405A - Semiconductor device and formation method - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which excels in the film quality even when an insulating film is made thinner and provides little deterioration of the insulating film even when writing and erasing operation is performed, and also its formation method. CONSTITUTION:In a semiconductor device which is provided with a semiconductor substrate 10 in which a first and a second impurity diffusion layer 12, 14 are provided and an electrode part 23 having an insulating film 16b over a part of the upper surface of the first and the second impurity diffusion layer 12, 14 on the semiconductor substrate and a conducting layer 18a on the upper side thereof, it is provided with nitrogen infection regions 12, 26 in the vicinity of the boundary between the insulating film 16b and the first and the second impurity diffusion layers 12, 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to
The present invention relates to a non-volatile semiconductor memory device (so-called EEPROM) having a memory effect in which information can be electrically written and erased and an external power need not be applied to retain information, and a method for forming the same.

[0002]

2. Description of the Related Art A conventional semiconductor device (for example, a non-volatile semiconductor memory device) is described in a document (reference: “Monthly Semiconductor”).
Actor World ", April 1991, P.
P. 94-98, Press Janal).

An example of the structure of a semiconductor device (ETOX cell) disclosed in this document will be described below.

According to the structure of this ETOX cell, an n ⁺ type source region and an n ⁺ type drain region are provided on a P conductive type semiconductor substrate. Further, the lower layer portion of the source region of n ⁺ -type, n ^- -type source region provided, also, the lower layer portion of the n ⁺ -type drain region are provided drain region of p ⁺ -type. A tunnel oxide film as an insulating film, a floating gate electrode, an interlayer insulating film, and a control gate electrode are laminated on the semiconductor substrate over a part of the upper surfaces of the source region and the drain region on the opposite end side.

Next, a method of operating the cell using the above-mentioned ETOX cell will be briefly described.

The write operation of the ETOX cell is performed by injecting electrons from the drain region into the floating gate electrode. That is, when a high voltage is applied to the control gate and the drain region, hot electrons (thermoelectrons) generated in the vicinity of the channel are injected into the floating gate, so that the threshold voltage seen from the control gate electrode is high (“ 0 "state)
Becomes On the other hand, erasing is performed by extracting the electrons in the floating gate to the source region through the tunnel oxide film. That is, the control gate electrode is set to the ground potential (0V) and a positive high voltage is applied to the source region. At this time, a tunnel current (also referred to as Fowler-Nordheim tunnel current) flows through the tunnel oxide film from the floating gate to the source region side, and electrons in the floating gate electrode are extracted. At this time, the threshold voltage is low (“1”
State). For reading, the threshold voltage of the memory cell transistor is set by applying a high potential to the control gate electrode and by selecting a memory cell and applying a sufficiently low voltage so as not to generate thermoelectrons in the drain region. Read the "1" or "0" state depending on the difference between.

[0007]

However, in the above-mentioned conventional ETOX cell, when information is repeatedly written and erased, the stress applied to the tunnel oxide film increases with the number of times information is rewritten. There is a correlation between the stress, the tunnel oxide film, and the data retention characteristic. For example, as the stress increases, the data retention characteristic deteriorates and the number of writing and erasing decreases. In general, as the thickness of the tunnel oxide film is increased, the electric field applied to the tunnel oxide film is reduced, and the number of times of writing and erasing information is increased.
Along with this, the data retention time also becomes longer. However, when the tunnel oxide film becomes thicker, in order to erase the electrons accumulated in the floating gate to the source region side by using the tunnel current at the time of erasing to erase the data, it is necessary to remove the data between the source region and the floating gate. It becomes necessary to apply a high voltage.
For this reason, the booster circuit must be incorporated in the semiconductor device, which requires an occupied area for the booster circuit in the semiconductor device in addition to the memory section and the peripheral drive circuit.
As a result, miniaturization of the entire circuit cannot be achieved. Therefore, in order to miniaturize the circuit, it is inevitable to make the tunnel oxide film thinner.

Further, a tunnel oxide film (eg, SiO 2
_As a conventional method for improving the film quality of ( ₂ films), for example, N ₂
By performing a heat treatment at 1100 ° C. for 30 seconds using O gas to form a Si—N bond in the tunnel oxide film,
The quality of the tunnel oxide film was made uniform. But,
In the above heating method, it is difficult to control the film thickness of the tunnel oxide film uniformly because the treatment is performed at a high heating temperature. Therefore, a method of making the film thickness of the tunnel film uniform without using a heating method. Was desired. Further, when the insulating film is used as a tunnel oxide film in, for example, a non-volatile semiconductor memory device (EEPROM) with the thinning of the tunnel oxide film (for example, 100 angstroms or less), the operating characteristics of the EEPROM deteriorate. Here, the deterioration of the operating characteristics mainly means the dielectric breakdown of the tunnel oxide film and the increase of the leak current. Accordingly, there has been a demand for a semiconductor device and a method for forming the same that have uniform film quality and little deterioration in operating characteristics even if the tunnel oxide film is thinned.

[0009]

Therefore, the semiconductor device of the present invention comprises a semiconductor substrate and an electrode portion provided on the surface thereof, and the electrode portion is at least the insulating film on the substrate surface and the upper portion thereof. And a conductive layer. First and second impurity diffusion layers are provided on the substrate, and an electrode portion is provided on the semiconductor substrate over a part of the upper surfaces of the first and second impurity diffusion layers on the opposite end side. The nitrogen implantation region is provided near the boundary between the insulating film and the first and second impurity diffusion layers.

Further, in implementing the present invention, it is preferable that the nitrogen implantation region provided near the boundary between the insulating film and the first and second impurity diffusion layers is provided in the insulating film.

In implementing the present invention, preferably, the nitrogen-implanted region is preferably provided over the insulating film and the first and second impurity diffusion layers.

Further, in carrying out the present invention, preferably, the nitrogen concentration in the nitrogen implantation region is at least 1 × 10 ²⁰ atoms / min.
It is good to use cm ³ .

In implementing the present invention, preferably, the semiconductor device is a non-volatile semiconductor memory device.

In the method for forming a semiconductor device of the present invention, (a) a step of providing the first and second impurity diffusion layers on the semiconductor substrate, and (b) an electrode having at least an insulating film and a conductive layer on the semiconductor substrate. And (c) nitrogen (N ₂ ) to the insulating film from diagonally above the semiconductor substrate surface.
Implanting atoms.

In implementing the present invention, the step of providing the first and second impurity diffusion layers on the semiconductor substrate may be performed after the step of implanting nitrogen atoms.

[0016]

The above-described semiconductor device of the present invention has the nitrogen implantation region near the boundary between the insulating film and the first and second impurity diffusion layers. Therefore, in the nitrogen implantation region near the boundary between the insulating film and the first and second impurity diffusion layers, hydrogen atoms contained in the insulating film are replaced with nitrogen atoms. This phenomenon can be predicted from the distribution curves of the impurity atom concentration and the depth of FIGS. 4A and 4B, which will be described later.
And in the nitrogen implantation region near the boundary of the second impurity diffusion layer,
It exhibits a phenomenon that hydrogen atoms decrease and nitrogen atoms increase.
Therefore, an insulating film (for example, when using a SiO ₂ film)
A Si—N bond having a strong bonding force is formed therein. On the other hand, Si-N bonds are also formed in the nitrogen implantation region of the semiconductor substrate (for example, when a silicon substrate is used). When this insulating film is applied to the tunnel oxide film of the nonvolatile semiconductor memory device, the trapping of electrons in the insulating film at the time of writing and erasing is suppressed, so that the threshold voltage (V Fluctuations in _t ) are reduced.

Further, according to the method for forming a semiconductor device of the present invention, the first and second impurity diffusion layers are provided on the semiconductor substrate, and the electrode portion having the insulating film and the conductive layer is provided on the substrate. After that, nitrogen (N ₂ ) atoms are ion-implanted into the insulating film from obliquely above the semiconductor substrate surface. With such a forming method, a nitrogen implantation region having a predetermined nitrogen concentration can be partially formed near the boundary between the insulating film and the first and second impurity diffusion layers by using the electrode portion as a mask. In the nitrogen-implanted region thus formed, nitrogen is bonded to Si in the insulating film to form an insulating film having a strong Si-N bond.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor device according to the present invention and the method for forming the same will be described below. Here, as an example of a semiconductor device, a nonvolatile semiconductor memory device (hereinafter referred to as an EEPROM) in which information can be electrically rewritten will be described as an example.

1A and 1B show an EEPROM
Plan view and AA for explaining the structure of one cell of FIG.
It is sectional drawing when it cut | disconnects along a line. Further, (A) to (D) of FIG. 2 and (A) to (C) of FIG.
FIG. 8 is a process chart for explaining a method for forming M. However, FIGS. 1 (A) to 1 (B), FIGS. 2 (A) to (D), and FIGS. 3 (A) to 3 (C) show the shapes and sizes of the respective constituents to the extent that the present invention can be understood. , And the arrangement is only shown schematically.

1. Structure of EEPROM Cell of the Present Invention First, referring to FIGS. 1A and 1B, an EEPROM cell
The structure of will be described.

A p-type silicon substrate (hereinafter referred to as a substrate) is used as the semiconductor substrate 10. The substrate 10 has, for example, a specific resistance of 10 Ω · cm and a crystal plane orientation of (10
0) face. The first impurity diffusion layer 12 (hereinafter, referred to as n ⁺ type source region) and the second impurity diffusion layer 14 (hereinafter, referred to as n ⁺ type drain region) are separated from the substrate 10.
And are provided. Also, if necessary, the drain region 14
-Type layer (not shown) is provided, also, n for preventing punch-through in the lower substrate 10 of the n ⁺ -type source region 12 ^{- -} type p for increasing injection efficiency into the substrate 10 of the lower A layer (not shown) may be provided.

A channel region 15 is provided between the n ⁺ type source region 12 and the n ⁺ type drain region 14. In addition, an n ⁺ type source region 12 is formed on the substrate 10.
And the insulating film 16b (hereinafter referred to as a tunnel oxide film), the conductive layer 18a (hereinafter referred to as a floating gate electrode), the interlayer insulating film 20a, and the control gate over a part of the upper surface of the opposite end of the n ⁺ type drain region 14. The electrode 22a is provided by stacking. In addition, here, the floating gate electrode 1
8a, the interlayer insulating film 20a, and the control gate electrode 22a are collectively referred to as an electrode portion 23.

Further, nitrogen implantation regions 24a, 24b, 26a and 26b are provided near the boundaries between the tunnel oxide film 16b and the n ⁺ type source region 12 and the n ⁺ type drain region 14. At this time, the nitrogen implantation regions 24a to 26b are formed.
Is a tunnel oxide film, an n ⁺ type source region and an n ⁺
Although it is formed across both of the mold drain regions,
It may be formed only in the tunnel oxide film 16b.

The nitrogen implantation region 24 of the tunnel oxide film
It is preferable that a and 26a are formed larger than the surfaces 28 and 30 where the n ⁺ type source region 12 and the n ⁺ type drain region 14 are joined to the tunnel insulating film 16b.

2. Method of Forming EEPROM of Present Invention Next, (A) to (D) of FIG. 2 and (A) to (C) of FIG.
The method of forming the EEPROM of the present invention will be described with reference to FIG.

First, the substrate 10 is washed with any suitable washing liquid to remove impurities adhering to the substrate 10, and the washed substrate 10 is immediately washed with any suitable oxide film forming reaction furnace (not shown). No)).

Then, oxygen gas is introduced into the reaction furnace and heat treatment is performed at about 900 ° C. for 20 minutes to form a tunnel oxide film 16 on the substrate 10 ((A) of FIG. 2). The material of the tunnel oxide film 12 is, for example, SiO ₂ , and the film thickness is, for example, about 110 A ° (the symbol A ° represents angstrom).

Subsequently, the structure shown in FIG. 2A is immediately transferred to a silicon thin film forming apparatus (not shown). Then, the floating gate preliminary layer 18 is formed on the tunnel oxide film 16 under any suitable condition ((B) of FIG. 2). The material of the floating gate preliminary layer 18 is, for example, polycrystalline silicon. Further, the thickness of the floating gate preliminary layer 18 is set to about 1000.
Set to A °. Further, phosphorus (P) is diffused into the floating gate preliminary layer 18 by any suitable method to form an N ⁺ conductivity type floating gate preliminary layer (not shown).

Next, the interlayer insulating film 20 is formed on the N ⁺ conductive type floating gate preliminary layer by chemical vapor deposition (CVD).
Are formed ((C) in FIG. 2). Interlayer insulating film 2 at this time
The material of No. 0 is SiO ₂ , for example, and the film thickness is about 200 A °.

Next, the control gate preliminary layer 22 is formed on the interlayer insulating film 20 by using a method similar to the step of FIG. 2B described above (FIG. 2D). The material of the control gate preliminary layer 22 is, for example, polycrystalline silicon, and phosphorus is diffused into the control gate preliminary layer 22 in the same manner as in the floating gate preliminary layer described above to control the N ⁺ conductivity type. A preliminary layer for gate is formed.

Next, a part of the control gate preliminary layer 22 is masked by any suitable method, and the structure of FIG. 3A is obtained by photoetching and dry etching. 22a, 20a, 18a and 1 remaining at this time
6a are referred to as a control gate electrode, an interlayer insulating film, a floating gate electrode and a tunnel oxide film, respectively. Further, here, the control gate electrode 22a, the interlayer insulating film 20a, and the floating gate electrode 18a are collectively referred to as an electrode portion 23.

Next, using the electrode portion 23 as a mask, nitrogen atoms are ion-implanted into the tunnel oxide film 16a from obliquely above the surface of the substrate 10. At this time, nitrogen implantation regions 24 (24a, 24b), 26 (26a, 26b) are formed in a part of the vicinity of the boundary between the tunnel oxide film 16a and the substrate 10.
Are formed ((B) of FIG. 3). 24a and 26a are regions formed in the insulating film (tunnel oxide film), and 24b and
26b is an impurity diffusion layer (source region and drain region)
The regions 12 and 14 and the channel region 15 are formed. The conditions for forming the nitrogen-implanted regions 24a to 26b will be described below.

Equipment used: Ion implantation equipment Ions used: N ₂ ⁺ ions Accelerating voltage: 50 KeV (However, the accelerating voltage must be arbitrarily selected depending on the size of the shape of the wafer and the shape of the electrode portion.) Dosage amount: 1 × 10 ¹⁶ cm ^{−2 Under the} above ^- mentioned ion implantation conditions, while rotating the substrate 10 at, for example, one rotation or more per minute, the nitrogen ( N
₂ ) Implant ions. At this time, the tunnel oxide film 16b
Nitrogen implantation regions 24a, 2 containing a high concentration of nitrogen atoms
6a is formed. On the other hand, nitrogen implantation regions 24b and 26b containing a high concentration of nitrogen atoms are also formed in the substrate 10. It should be noted that nitrogen ion implantation into the channel region 15 should be avoided if possible. Why, EEPROM
This is because it does not affect the operating characteristics of.

After that, an n ⁺ conductivity type source region 12 and drain region 14 are formed on the substrate 10 by ion implantation (FIG. 3C). Although the n ⁺ type source region 12 and the drain region 14 are provided after forming the tunnel oxide film 16b and the electrode portion 23 in the embodiment of the present invention, they may be provided in advance on the substrate 10.

In FIGS. 4A and 4B, the atomic concentrations near the boundary between the tunnel oxide film (SiO ₂ film) 16b and the silicon (Si) substrate 10 are measured by SIMS (secondary ion mass spectrometry). The results of measurement are shown below. In the figure, the horizontal axis represents the depth of impurities (A °) and the vertical axis represents the concentrations of hydrogen and nitrogen (atoms / cm ³ ).

Curve I represents the impurity concentration distribution when the SiO ₂ film is not doped with nitrogen (N ₂ ),
Curve II is an annealing treatment of the SiO ₂ film with N ₂ O gas (1
100 ° C., 30 seconds), and the curve III shows the impurity concentration distribution when the SiO ₂ film formed in the embodiment of the present invention is used.

As can be seen from FIGS. 4A-4B, EEEPRO formed according to an embodiment of the present invention.
M is the hydrogen concentration of the conventional curve I and the conventional curve II as it approaches the upper surface of the SiO ₂ film from the SiO ₂ / Si interface.
It has decreased compared to.

Further, looking at the distribution of nitrogen concentration, the nitrogen concentration when not doped with nitrogen (curve I) is SiO ₂ / S.
3 × 10 ¹⁹ atoms / cm ³ near the i-boundary, and SiO ₂
In the vicinity of the surface of, the value is 1 × 10 ¹⁸ atoms / cm ³ . On the other hand, the nitrogen concentration (curve II) when the N ₂ O gas is annealed has a peak at the SiO ₂ / Si interface,
It begins to decrease rapidly as it approaches the upper surface of the SiO ₂ film. That is, at the peak of 3 × 10 ²¹ atoms / cm
^The nitrogen concentration of ³ was S from the SiO ₂ / Si interface.
Approximately 2 × 10 when separated by a depth of approximately 50 A ° in the direction of the iO ₂ film.
^It has been reduced to ¹⁸ atoms / cm ³ . On the other hand, looking at the distribution of nitrogen concentration in the example of the present invention (curve III),
The nitrogen concentration at the SiO ₂ / Si interface is 7 × 10 ²² atoms /
cm ³ but about 50 from the boundary surface to the upper surface of the SiO ₂ film
It decreases once to about 1 × 10 ²⁰ atoms / cm ³ at a depth of A °. After that, the nitrogen concentration does not decrease to the upper surface of the SiO ₂ film and the value of about 1 × 10 ²⁰ atoms / cm ³ is maintained.
The following is predicted from this measurement result. In the tunnel oxide film of the present invention, hydrogen atoms and nitrogen atoms are replaced,
A stable nitrogen-implanted region of the tunnel oxide film having a strong Si—N bond is formed. Further, nitrogen atoms of 1 × 10 ²⁰ atoms / cm ³ or more are formed uniformly in the nitrogen implantation regions 24a and 26a over the entire region in the film thickness of the tunnel oxide film.

FIG. 5 shows E of the conventional example and the embodiment of the present invention.
The relation between the threshold voltage of EPROM and the number of times of rewriting is shown. Here, the curve I represents the threshold voltage when the SiO ₂ film is not doped with nitrogen, and the curve II is the case where the SiO ₂ film is formed and then annealed in N ₂ O gas. Is an EEPROM formed in the embodiment of the present invention.
Represents the threshold voltage when used. White circles, white squares and white triangles distributed above represent the threshold voltage (V _t ) at the time of writing, and black circles distributed below,
Black squares and black triangles represent threshold voltages at the time of erasing.

As can be seen from FIG. 5, conventional SiO 2
Looking at the threshold voltage when the _two films are not doped with nitrogen (curve I) and when annealed in N ₂ O gas (curve II), the threshold voltage at the time of writing of the EEPROM is The number of erase repetitions (hereinafter referred to as the number of rewrites) is 1
It gradually decreases from the point when it exceeds × 10 ³ times. That is, when the number of rewrites is 1 × 10 ³ times, the threshold voltage is about 5V, but when it is 4 × 10 ⁴ times, the threshold voltage is about 3.5V.
Changes to. That is, the amount of change in the threshold voltage is 1.
It is 5V. On the other hand, the threshold voltage at the time of writing of the EEPROM of the present invention is about 5V at the start of operation, and remains 5V even if the number of rewriting times reaches 4 × 10 ⁴ , and the threshold voltage does not change. That is, the amount of change in the threshold voltage is 0
V. On the other hand, looking at the threshold voltage at the time of erasing, the threshold voltage in the case where the conventional SiO ₂ film is not doped with nitrogen (curve I) is −1 V at the first time, but is 4 × 10 ^4.
When the number of times of rewriting is reached, it changes to about 0.5V. That is, the amount of change in the threshold voltage is 1.5V.

Further, the threshold voltage in the case of annealing in N ₂ O gas (curve II) was −0.
Although it is 5 V, it changes to about 0 V when the number of rewriting times is 4 × 10 ⁴ . That is, the amount of change in the threshold voltage is 0.5 V
Is.

On the other hand, looking at the change amount (curve III) of the threshold voltage at the time of erasing according to the present invention, the threshold voltage is 0.5 V at the initial point, but it is 4 × 10 ⁴ times. When the number of times of rewriting is reached, it changes to about 0.7V. That is, the amount of change in the threshold voltage is 0.2V.

As can be understood from this result, the amount of change in the threshold voltage depending on the number of times of rewriting of the EEPROM of the present invention is smaller than in the conventional case.

As can be understood from the results shown in FIG. 5, the tunnel oxide film formed according to the present invention has excellent dielectric breakdown resistance even when it is thinned, and has a floating gate electrode, an n ⁺ type source and an n ⁺ type drain. It suppresses an increase in leak current between regions.

Further, since a nitrogen implantation region is provided in the insulating film (tunnel oxide film), the Si--N bond can be strengthened,
The tunnel oxide film can be thinned. Therefore, there is an advantage that the boosting circuit is not necessary and the area occupied by the circuit formed in the semiconductor device can be miniaturized.

In the above-mentioned embodiment, the nitrogen-implanted region is formed in the vicinity of the boundary between the tunnel oxide film as the insulating film and the substrate and in the impurity diffusion layer below the electrode portion. Depending on the method, the nitrogen implantation region may spread to the electrode part, the entire impurity diffusion layer, or even the channel region. However, as described in the above-described embodiments, if the nitrogen-implanted region is formed in at least a part of the insulating film, the characteristics of the semiconductor device are not affected even if the nitrogen-implanted region is formed in such an enlarged manner. There is no.

Further, in the embodiment of the present invention, the nonvolatile semiconductor memory device (EEPROM) has been described, but the present invention is not limited to this EEPROM and can be applied to, for example, an EPROM and other memory devices.

[0048]

As is apparent from the above description, the semiconductor device of the present invention has the nitrogen implantation region near the boundary between the insulating film and the first and second impurity diffusion layers. Therefore, an insulating film having a strong Si—N bond is formed in this nitrogen-implanted region. When the insulating film thus formed is used as, for example, a nonvolatile semiconductor memory device, it suppresses trapping of electrons at the time of writing and erasing, so that the dielectric breakdown resistance of the insulating film is improved and the insulating film is improved. Leakage current flowing through is reduced. Further, by providing a nitrogen-implanted region in the insulating film, the stress resistance is also improved. For example, when this insulating film is used in a nonvolatile semiconductor memory device, the number of writing and erasing becomes long. Moreover, since the thickness of the insulating film can be reduced,
Since it is not necessary to provide a boosting circuit, the size of the circuit mounted in the semiconductor device can be reduced.

According to the method for forming a semiconductor device of the present invention, the first and second impurity diffusion layers are provided on the semiconductor substrate, and the electrode portion having the insulating film and the conductive layer is provided on the semiconductor substrate. After that, nitrogen atoms are ion-implanted into the insulating film from obliquely above the semiconductor substrate surface. By such a method, a high-concentration nitrogen implantation region can be formed near the boundary between the insulating film and the first and second impurity layers. Since such a nitrogen-implanted region is formed in the insulating film or the insulating film and the first and second impurity diffusion layers, electrons trapped in the insulating film during writing and erasing are suppressed. Therefore, the threshold voltage is stable even if the number of times of writing and erasing is increased.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view taken along the line AA of a nonvolatile semiconductor device according to an embodiment of the present invention.

2 (A) to (D) are process drawings provided for explaining a manufacturing process of an embodiment of the present invention.

3 (A) to 3 (C) are process drawings provided for explaining the manufacturing process of the embodiment of the present invention following FIG.

4 (A) to (B) are distribution curve diagrams of the depth of impurities and the concentration of each atom by SIMS (secondary ion mass spectrometry).

FIG. 5 is a diagram for explaining the relationship between the number of times of repeating writing and erasing and the threshold voltage (V _t ) according to the present invention.

[Explanation of symbols]

10: Silicon (Si) substrate 12: n ⁺ type source region 14: n ⁺ type drain region 16: tunnel oxide film preliminary layer 16a, 16b: tunnel oxide film 18: floating gate preliminary layer 18a: floating gate electrode 20, 20a : Interlayer insulating film 22: Control gate preliminary layer 22a: Control gate electrode 23: Electrode parts 24a, 24b, 26a, 26b: Nitrogen implantation region 28: Junction surface between tunnel oxide film and source region 30: Tunnel oxide film and drain region Joining surface of

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[Procedure amendment]

[Submission date] December 27, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (7)

[Claims] 1. A semiconductor substrate provided with first and second impurity diffusion layers, and a part of the upper surface of the semiconductor substrate on the opposite end side of the first and second impurity diffusion layers, And a semiconductor device including at least an insulating film and an electrode portion having a conductive layer on the upper side thereof, wherein a nitrogen implantation region is provided near a boundary between the insulating film and the first and second impurity diffusion layers. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the nitrogen-implanted region is provided in an insulating film. 3. The semiconductor device according to claim 1, wherein the nitrogen implantation region is provided in the insulating film and the first and second impurity diffusion layers. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a non-volatile semiconductor memory device. 5. The semiconductor device according to claim 1, wherein the nitrogen concentration in the nitrogen implantation region is at least 1 × 10 ²⁰ atoms / min.
A method for forming a semiconductor device, wherein the method is cm ³ . 6. In forming the semiconductor device according to claim 1, (a) a step of providing the first and second impurity diffusion layers on the semiconductor substrate, and (b) the insulating film on the semiconductor substrate. And a step of providing an electrode portion having at least the conductive layer, and (c) a step of ion-implanting nitrogen (N ₂ ) atoms into the insulating film from obliquely above the semiconductor substrate surface. Method of forming a semiconductor device. 7. The method of forming a semiconductor device according to claim 6, wherein the step (a) is performed after the step (c).