CN102569408A - SONOS (Silicon Oxide Nitride Oxide Silicon) unit transistor with high erasing speed and manufacturing method thereof - Google Patents

Abstract

The invention discloses a method for increasing erasing speed of an SONOS (Silicon Oxide Nitride Oxide Silicon) unit transistor by using a strained silicon technology. The method is characterized by comprising the step of making a side wall of a gate on a P type substrate with a plurality of shallow trench isolation regions and also comprises the following steps of: (step 1) depositing a barrier layer to cover the transistor; (step 2) etching the barrier layer so as to remove the barrier layer covering above a NMOS (N-channel Mental-Oxide-Semiconductor) region so that the NMOS region is exposed; (step 3) carrying out carbon ion implantation on the P type substrate between the two sides of the gate and the shallow trench isolation regions; and (step 4) carrying out high temperature annealing so that tensile stresses are generated on the trenches through the silicon carbide. By using the method for increasing erasing speed of the SONOS unit transistor by using the strained silicon technology, disclosed by the invention, the energy band of the silicon is cracked and the electron effective mass is reduced along the trench direction due to the cracking result; meanwhile, the energy valley scattering probability of the electron is also reduced and the electron mobility of the SONOS unit transistor is obviously increased so that SONOS programming efficiency and speed of a hot electron injection mechanism are increased.

Description

A kind of SONOS cell transistor and manufacturing approach thereof of high erasable speed

Technical field

The present invention relates to silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) memory, particularly, relate to a kind of SONOS cell transistor and manufacturing approach thereof of high erasable speed.

Background technology

The basic functional principle of non-volatile semiconductor memory is a stored charge in the gate medium of a MOSFET.Wherein the device that is stored in the trapping centre of separation of a suitable dielectric layer of electric charge is called as the electric charge capture device.The most frequently used in this type device is silicon-silica-silicon-nitride and silicon oxide-silicon (SONOS) memory.

The main two kinds of memory mechanisms that are used for the storage data of flash memory cells are that channel hot electron (CHE) injects and the F-N tunneling effect.Channel hot electron injects and is considered to after through long-term circulation, remain quite reliable, and reason is that it does not apply very big stress on tunnel oxide.But the shortcoming of CHE is that programming efficiency is low.It is that transverse electric field with raceway groove comes accelerated electron that channel hot electron injects, and obtains one when being enough to overcome the high-energy of potential barrier when electronics is accelerated to, and the hot electron injection will take place.During programming, drain and gate all will apply relative higher voltage, and drain electrode directly links to each other with voltage source, and grid voltage then depends on capacitive coupling.For effective programming, transistor should be biased in the saturation region, makes the electronics that passes pinch-off point in the drain terminal depletion region, set up big transverse electric field.This bias state of grid makes near the channel inversion layer broad the source, and along with the convergence pinch-off point, it is narrower that channel inversion layer becomes, so that pass in the high electric field of electronics in the drain terminal depletion region of pinch-off point by strong acceleration.When portions of electronics obtains enough high-energy like this, hot electron just takes place inject, but because to have only the sub-fraction raceway groove be effectively to programming, so hot electron injection programming efficient is not high.

Therefore, provide a kind of erasable method of velocity of strained silicon technology raising SONOS and SONOS cell transistor of high erasable speed of utilizing just to seem particularly important.

Summary of the invention

The objective of the invention is to improve, thereby realize improving SONOS programming efficiency and the speed that hot electron injects mechanism through the electron mobility that makes the SONOS cell transistor.

The present invention discloses a kind of SONOS cell transistor of high erasable speed, comprises some paired PMOS and NMOS, and said NMOS comprises:

Have the P type silicon substrate of some paired active areas, each is to being formed with raceway groove between the active area;

Grid is positioned at said raceway groove top, has silica-silicon-nitride and silicon oxide layer between the side wall of said grid, is polysilicon on said silica-silicon-nitride and silicon oxide layer;

The both sides of the periphery of said paired active area are respectively arranged with shallow channel isolation area;

Wherein, the paired active area of the active area of said NMOS comprises carborundum.

The SONOS cell transistor of above-mentioned high erasable speed, wherein, said paired active area comprises source electrode and drain electrode.

According to an aspect of the present invention, also disclose a kind of method of making the SONOS cell transistor of the erasable speed of above-mentioned height, wherein, after having made the side wall of grid on the P type substrate that forms some shallow channel isolation areas, also comprise the steps:

Step 1, the deposition barrier layer covers said transistor;

Step 2, etching are removed the barrier layer that covers top, nmos area territory exposes said nmos area territory;

Step 3, the silicon of the active area position, both sides of etching N MOS zone grid;

Step 4, through selective epitaxial process, the deposition carborundum in said active area position;

Step 5 is carried out high annealing, makes said carborundum produce tensile stress to raceway groove.

Above-mentioned method wherein, behind completing steps 5, also comprises the step of removing the barrier layer.

In order to improve SONOS programming efficiency and the speed that hot electron injects mechanism, the present invention sets about from the angle that improves the channel carrier mobility.Carrier mobility can be by equation μ=qt/m* decision, and wherein q is an electron charge, and m* is the charge carrier effective mass, and t is the average life span between double scattering, so probability of scattering is 1/t.

The present invention utilizes the stress si technology, after the SONOS side wall forms, returns back depositing silicon carbide at quarter at source-drain area; Through annealing the source is leaked the SONOS cell channel is produced tensile stress; Being with of silicon divided, and the result of division causes reducing along the electron effective mass of channel direction, and the energy valley probability of scattering of electronics also reduces simultaneously; The electron mobility of SONOS cell transistor is significantly improved, thereby improve SONOS programming efficiency and speed that hot electron injects mechanism.

Description of drawings

Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the part parts, for same parts, only indicated wherein part, those skilled in the art can combine embodiment partly to understand.

Fig. 1 shows according to the present invention, the profile after SONOS unit component side wall forms;

Fig. 2 is that nmos area territory window is opened, the sketch map of deposition carborundum;

Fig. 3 is the structural representation of carborundum after forming; And

Fig. 4 makes the sketch map of the carborundum of source and drain areas to raceway groove generation tensile stress for through high-temperature annealing process.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is further elaborated.Embodiment described herein only is used to explain the present invention, and is not used in qualification protection scope of the present invention.

Earlier with reference to figure 3 and Fig. 4; As shown in the figure the comprising of SONOS cell transistor of the erasable speed of height of the present invention: comprise some paired PMOS (not shown in the accompanying drawing) and NMOS; Said NMOS comprises: have the P type silicon substrate 104 of some paired active areas 103, each is to being formed with raceway groove (not shown among Fig. 3 and Fig. 4) between the active area 103; Grid 101 is positioned at said raceway groove top, has silica-silicon-nitride and silicon oxide layer 111 (ONO layer) between the side wall 102 of said grid 101, is polysilicon 121 on said silica-silicon-nitride and silicon oxide layer 111; The both sides of the periphery of said paired active area 103 are respectively arranged with shallow channel isolation area 105; It is characterized in that the active area 103 paired active areas 103 of said NMOS comprise carborundum (SiC).

Particularly, in the SONOS cell transistor of the erasable speed of described height, said paired active area 103 comprises source electrode and drain electrode.

Combine again with reference to figure 1 and Fig. 2, disclosed the manufacturing approach of the SONOS cell transistor of the erasable speed of height of the present invention,, after having made the side wall 102 of grid 101 on the P type substrate 104 that forms some shallow channel isolation areas 105, also comprise the steps: with reference to figure 1

Step 1, deposition barrier layer (not shown in figure 1) covers said transistor;

Step 2, etching are removed the barrier layer that covers top, nmos area territory exposes said nmos area territory, in this step; Elder generation's spin coating photoresist is on said barrier layer; Carry out photoetching again, those skilled in the art can combine the said step of existing techniques in realizing, do not repeat them here;

Step 3, the silicon (as shown in Figure 2) of both sides active area 103 positions of etching N MOS zone grid 101;

Step 4, through selective epitaxial process, deposition carborundum it will be appreciated by those skilled in the art that and utilizes the selective epitaxial process growing silicon carbide to be prior art in said active area 103 positions, does not repeat them here;

Step 5 is carried out high annealing, makes said carborundum produce tensile stress (as shown in Figure 4) to raceway groove.

The present invention divides being with of silicon; The result of division causes reducing along the electron effective mass of channel direction; The energy valley probability of scattering of electronics also reduces simultaneously; The electron mobility of SONOS cell transistor is significantly improved, thereby improve SONOS programming efficiency and speed that hot electron injects mechanism.

Further, in above-mentioned method, behind the completing steps 5, also comprise the step of removing the barrier layer.

Those skilled in the art combine prior art and the foregoing description can realize said variant, and such variant does not influence flesh and blood of the present invention, does not repeat them here.

More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (4)

1. the SONOS cell transistor of a high erasable speed comprises some paired PMOS and NMOS, and said NMOS comprises:

Have the P type silicon substrate of some paired active areas, each is to being formed with raceway groove between the active area;

Grid is positioned at said raceway groove top, has silica-silicon-nitride and silicon oxide layer between the side wall of said grid, is polysilicon on said silica-silicon-nitride and silicon oxide layer;

The both sides of the periphery of said paired active area are respectively arranged with shallow channel isolation area;

It is characterized in that the paired active area of the active area of said NMOS comprises carborundum.

2. the SONOS cell transistor of the erasable speed of height according to claim 1 is characterized in that, said paired active area comprises source electrode and drain electrode.

3. a method of making the SONOS cell transistor of claim 1 or the erasable speed of 2 said height is characterized in that, after having made the side wall of grid on the P type substrate that forms some shallow channel isolation areas, also comprises the steps:

Step 1, the deposition barrier layer covers said transistor;

Step 2, etching are removed the barrier layer that covers top, nmos area territory exposes said nmos area territory;

Step 3, the silicon of the active area position, both sides of etching N MOS zone grid;

Step 4, through selective epitaxial process, the deposition carborundum in said active area position;

Step 5 is carried out high annealing, makes said carborundum produce tensile stress to raceway groove.

4. method according to claim 3 is characterized in that, behind completing steps 5, also comprises the step of removing the barrier layer.

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