KR20050112651A - Flash memory device and method for programming/erasing the same - Google Patents

Abstract

The present invention implements a flash memory device having a sonos (SONOS: polySilicon-Oxide-Nitride-Oxide-Silicon) structure in the form of PMOS, and then the program is implemented and erased by a hot electron injection method to provide endurance. The present invention relates to a flash memory device having improved characteristics, and a method of programming and erasing the same, wherein the flash memory device includes a semiconductor substrate, an ONO film formed on a surface of the semiconductor substrate, and a P + type poly gate formed on the ONO film. And source / drain regions defined by implanting P + type impurities into the surface of the semiconductor substrate on both sides of the poly gate.

Description

Flash Memory Device and Method for Programming / Erasing the Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular, implements a device having a sonos (SONOS: polySilicon-Oxide-Nitride-Oxide-Silicon) structure in the form of PMOS, and then programs and erases the same by hot electron injection. Accordingly, the present invention relates to a flash memory device and a method of programming / erasing the same, which effectively improve endurance characteristics.

In general, a typical memory device of a non-volatile memory device (Flash Memory Device, Non-volatile Memory Device) that is not erased even if power is not supplied is EEPROM (Electrically Erasable and Programmable Read Only Memory).

The EEPROM is a nonvolatile memory device that can be electrically rewritten, and a structure using a floating gate cell has been widely used. Recently, as the high integration is rapidly progressed, the reduction of the conventional floating gate type cell is very urgently required, but a high voltage is required at the time of program / erase and a reduction above a certain level is almost impossible. For this reason, various researches such as SONOS, FeRAM, SET, and NROM are being conducted as nonvolatile memory devices to cope with floating gate cells. Among these, the SONOS cell is attracting the most attention as a next-generation cell to replace the stacked floating gate cell.

Hereinafter, a conventional Sonos device will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a flash memory device having a conventional SONOS structure.

As shown in FIG. 1, the conventional SONS device is an NMOS device, and includes a P-type substrate 10, a tunnel oxide 12, and a trap nitride film over a predetermined region of the substrate 10. 13), a block oxide film 14 and a gate 15 of an N + type polysilicon component. In addition, a source / drain 11 into which N + type impurities are implanted is formed on a surface of the substrate 10 corresponding to both sides of the gate 15.

2 is a schematic diagram illustrating a method of programming a flash memory device having a conventional SONOS structure.

As shown in FIG. 2, in the case of programming a conventional Sonos device, a bias condition applies a predetermined positive voltage to the drain 11a and the gate 15. The source (Source, 11b) and the substrate (Body, 10) is grounded (GND).

The voltages applied to the gate 15 and drain 11a create a vertical and horizontal electric field along the length of the channel region from source 11b to drain 11a.

By the electric field, electrons are pushed out of the source 11b and begin to accelerate toward the drain 11a. The electrons get energy as they travel along the channel length, and some electrons are in a 'hot' state where they get enough energy to cross the potential barrier of the tunnel oxide 12 and enter the charge trapping layer. The likelihood of such a phenomenon is greatest in the channel region near the drain 11a because the channel region near the drain 11a is where the electrons obtain the greatest energy. As long as hot electrons are injected into the trap nitride film 13 made of an insulating material, hot electrons are trapped in the trap nitride film 13 and stored therein, and the threshold voltage of the flash memory device of the SONOS structure becomes high. .

The program method as described above is called a channel hot electron injection method, and at this time, a region where electrons are trapped in the trap nitride film 13 corresponds to an A region.

In the above description, a channel hot electron injection (CHEI) method has been described as a method of programming a flash memory device having a conventional SONOS structure. In addition, Fowler Nordheim Tunneling (hereinafter, referred to as “Fowler Nordheim Tunneling”) The program can also be done in the form of F / N tunneling).

At the present time, a high voltage is required in the case of the F / N tunneling, and the above-described channel thermal electron scanning method is more preferred.

3 is a schematic diagram illustrating a method of erasing a flash memory device having a conventional SONOS structure.

As shown in FIG. 3, in the case of erasing a conventional Sonos device, a bias condition is to apply a predetermined positive voltage to the drain 11a and a predetermined negative voltage to the gate 15. The source 11b and the substrate (body 10) are grounded (GND) or floating.

Under the bias condition, depletion is generated around the N + impurity region, which is the drain 11a, by a high electric field formed in a region where the drain 11a region and the gate 15 of the N + type polysilicon overlap. Is formed. In this depletion region (C region), electron / hole pairs are generated by band to band tunneling, and the generated electrons are transferred to the N + impurity region, which is the drain 11a. As it exits, the hole is accelerated by the Lateral Electric Field formed in the depletion region and turns into a hot hole. These hot holes are injected into the valence band of the trap nitride film 13 by crossing the energy barrier between the tunnel oxide film 12 and the silicon substrate 10 and present in the trap nitride film 13. By trapping at the level, electrons stored during programming are neutralized in response to the thermal holes, thereby erasing the memory cell. Through such an erase operation, a threshold voltage of the flash memory device having the SONOS structure is lowered.

This erasing method is called a hot hole injection method, and the area where the hot hole is captured onto the trap nitride film 13 is limited to the B area so that hot electrons during the program are captured. Erase occurs at a very small portion of the region, and an abnormal phenomenon in which electrons remain even after erasure occurs at a region corresponding to the region difference.

4 is a schematic diagram illustrating a method of reading a flash memory device having a conventional SONOS structure.

As shown in FIG. 4, when reading a flash memory device having a conventional SONS structure, a bias condition is a positive reference voltage applied to the gate 15 and a constant to the source 11b. The positive voltage is applied and the drain 11a and the substrate Body 10 are grounded.

In the bias condition, a current does not flow or flows according to a programming / erasing state near the drain 11a, thereby reading whether a current state is a programming state or an erase state. This reading method is called a reverse reading method.

Meanwhile, in the above-described programming / erasing / reading method, the bias conditions between the source 11b / drain 11a are changed to be different from each other in the drain 11a region and the source 11b region. The erase operation enables the flash memory device of one SONOS structure to operate with two bits.

Thus, a representative example of operating two bits with one sonos transistor is a device called NROM of Saifun Corporation.

FIG. 5 is a diagram illustrating energy levels of each layer and movement of electrons and holes during erasing of a flash memory device having a conventional SONOS structure.

As illustrated in FIG. 5, in the erasing operation of a flash memory device having a conventional SONOS structure, holes from the P-type substrate 10 tunnel through the tunnel oxide film 12 to form the trap nitride film 13. After being injected into the valence band, about 1% of the holes are trapped at the trap level of the trap nitride film 13, and most of the holes (approximately 99%) are trapped in the valence band of the gate 15, which is an N + type polysilicon. Electrons trapped at the trap level of the trap nitride film 13 before the erase operation are detrapted during the erase operation, and then tunnel through the tunnel oxide film 12 to the P-type substrate 10. As a result, the threshold voltage of the flash memory device of the SONOS structure is reduced.

As described above, another flow of electrons, which is unnecessary for the erasing operation, is generated, and the electrons present in the conduction band of the gate 15, which is n + polysilicon, may cause the block oxide layer 14 to F / N. (Fowler Nordheim) is tunneled and injected into the conduction band of the trap nitride film 13. This is called back Fowler Nordheim Tunneling.

Part of the electrons injected into the trap nitride film 13 by the back F / N tunneling is trapped at the trap level of the trap nitride film 13 to saturate the erase threshold voltage. Most of the injected electrons (approximately 99% of the injected electrons) tunnel through the tunnel oxide film 12 to exit the conduction band of the P-type substrate 10.

As such, the F / N tunneling stress is excessively applied to the tunnel oxide film 12 while the back F / N tunneled electrons exit the conduction band of the P-type substrate 10 through the tunnel oxide film 12. By forming a trap level between the type substrate 10 and the tunnel oxide film 12 or in the tunnel oxide film 12, a phenomenon in which the threshold voltage changes as the erase / programming operation is repeated several times, that is, the endurance characteristic becomes very poor. do.

In addition, since most of the back F / N tunneled electrons flow into the P-type substrate 10, ONO (Tunnel Oxide-Trap Nitride-Block Oxide) film-like brakes are applied when a negative voltage is applied to the gate. The breakdown voltage and time dependent dielectric breakdown (TDDB) characteristics are much worse than when a positive voltage is applied, and an erase voltage lower than a program voltage is inevitably applied.

The flash memory device of the conventional SONOS structure as described above has the following problems.

As described above, the flash memory device having a conventional SONOS structure uses a channel hot electron injection program method for programming and a hot hole injection erasing method for erasing. Is not exactly matched to the part where thermal hole scanning occurs, and as the programming and erasure is continued, electrons that cannot be canceled even by thermal hole scanning accumulate little by little near the edge of the N + impurity region, which is a source or a drain. There is a problem that the program threshold voltage and the erase threshold voltage are increased than the initial program threshold voltage and the erase threshold voltage.

It is said to have endurance when the threshold voltage does not continuously change when the programming / erase operation of the device is repeated, or it changes within a predetermined range and has a holding characteristic, which is a conventional 1-bit sonos device. In the case of 2-bit NROM devices, these durability characteristics are so bad that they are not commercially available.

The present invention has been made to solve the above problems and implements a device of the Sonos (SONOS: polySilicon-Oxide-Nitride-Oxide-Silicon) structure in the form of PMOS, and then programed by Hot Electron Injection. And a flash memory device and a method for programming / erasing the same, which have been erased to effectively improve endurance characteristics.

The flash memory device of the present invention for achieving the above object is a semiconductor substrate, the ONO film formed on the surface of the semiconductor substrate, the P + type poly gate formed on the ONO film and the surface of the semiconductor substrate on both sides of the poly gate It is characterized by including source / drain regions defined by implantation of P + type impurities.

The ONO film is a tunnel oxide film, a trap nitride film, and a block oxide film in order from the bottom.

In addition, the programming method of the flash memory device of the present invention for achieving the same object, the semiconductor substrate, the ONO film formed on the surface of the semiconductor substrate, the P + type poly gate formed on the ONO film and both sides of the poly gate A method of programming a flash memory device having a source / drain region defined by doping a P + type impurity on a surface of a semiconductor substrate, the method comprising: applying a positive voltage to the gate and a negative voltage to the drain region, thereby It is characterized by forming a high electric field in the overlap region and trapping hot electrons in the ONO film.

The source region and the substrate are grounded or floated.

In addition, a method of erasing a flash memory device of the present invention for achieving the same object includes a substrate, an ONO film formed on a surface of the semiconductor substrate, a P + type poly gate formed on the ONO film, and the semiconductor substrate on both sides of the poly gate. A method of erasing a flash memory device having a source / drain region defined by doping a P + type impurity on a surface thereof, the method comprising: applying a negative voltage to the gate and grounding the drain region to an overlap region between the drain and the gate; A high electric field is formed to draw hot electrons trapped in the ONO film to the drain region or to tunnel the thermal holes in the drain region to the ONO film.

The source region and the substrate are grounded or floated.

Hereinafter, a flash memory device and a programming / erasing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

6 is a cross-sectional view illustrating a flash memory device having a SONOS structure according to the present invention.

As illustrated in FIG. 6, the SONOS device of the present invention is a PMOS device, and includes an N-type substrate Nwell 100 and a tunnel oxide 102 formed on an upper portion of the substrate 100. A nitride film 103, a block oxide 104, and a gate 105 of a P + type polysilicon component are included. In addition, a source / drain 101 into which a P + type impurity is implanted is formed on a surface of the substrate 100 corresponding to both sides of the gate 105.

At this time, the tunnel oxide film 102, the trap nitride film 103, and the block oxide film 104, which are insulating films between the substrate 100 and the gate 105, are collectively referred to as an ONO-Nitride-Oxide film.

7 is a schematic diagram showing a method of programming a flash memory device of the SONOS structure of the present invention.

As illustrated in FIG. 7, programming of a SONOS device according to the present invention is performed under a bias condition as follows.

That is, a predetermined positive voltage is applied to the gate 105, a predetermined negative voltage is applied to the drain 101a, and the source 101b is ground (GND) or floating. The substrate 100 is grounded or floated.

Under such bias conditions, a high electric filed is formed in a region (region D) where the drain 101a portion and the P + type polysilicon gate 105 overlap, whereby the drain 101a in the substrate 100 is formed. A depletion region (region E) is formed near the region (P + region).

In the depletion region (E region), electron / hole pairs are generated by band to band tunneling, and the holes generated at this time are formed in the region of P + type drain 101a. Exit to At this time, electrons are accelerated by a lateral electric field formed in the depletion region (E region) to change into hot electrons, and the hot electrons are converted into the tunnel oxide film 102 and silicon. A program operation is performed in which a threshold voltage is lowered by crossing the energy barrier between the substrates 100 and being injected into the valence band of the trap nitride film 103 to be trapped at the trap level present in the trap nitride film 103. Such a programming method is called a hot electron injection method, and a conventional channel hot electron injection method is very local compared to the point where hot electron scanning occurs on a depletion region, that is, the drain 101a region and the like. In the region (region D) where the P + type polysilicon gate 105 overlaps, a thermal electron trap occurs in the trap nitride film 103. As such, the reason why a thermal electron trap is possible in a very local area is because a positive voltage and a negative voltage are applied to the gate 105 and the drain 101, respectively, to form a high electric field between the two. By forming a hot electron trap in this localized region, electrons trapped in the trap nitride film 103 at the time of erasing can be easily taken out to the drain 101a side.

8 is a schematic diagram illustrating a method of erasing a flash memory device having a SONOS structure of the present invention.

As shown in FIG. 8, the erasing method of the flash memory device of the SONOS structure of the present invention applies the following bias condition.

That is, a predetermined negative voltage is applied to the gate 105, the drain 101a is grounded (GND), and the source 101b is floating or grounded (GND), and the substrate (Body, 100) Floating. In this case, an electric field is formed from the drain 101a to the gate 105, and tunneling of electrons or holes is performed in the overlap region of the drain 101a and the gate 105.

Under such bias conditions, a high electric field is formed in a region where the drain 101a portion and the P + polysilicon gate 105 overlap. Electrons trapped in the trap nitride film 103 by the high electric field are tunneled in the F region to escape to the drain 101a (the P + type impurity region) in the substrate 100 or the Erasing operation is performed in which holes existing in the drain 101a are tunneled and trapped at the trap level existing in the trap nitride film 103 to increase the threshold voltage. This erase method is called a tunneling method.

Since the flash memory device of the SONOS structure of the present invention uses a P + type polysilicon gate 105, electrons are injected from the gate 105 into the trap nitride film 103 even when the gate is erased by a tunneling method. Since the erase threshold voltage is not saturated, the erasing speed can be increased, and the threshold voltage window can be greatly widened.

9 is a schematic diagram illustrating a reading method of a flash memory device having a SONOS structure of the present invention.

As shown in FIG. 9, when reading a SONOS device of the present invention, a bias condition is as follows. That is, a negative reference voltage is applied to the gate 105, a negative voltage is applied to the source 101b, and the drain 101a and the substrate 100 are grounded (GND). Let's do it.

Under the bias condition, current flows or not flows according to the programming / erase state near the drain 101a, and the current flow is sensed to read whether the current state is programmed or erased. This reading method is called a reverse reading method.

Meanwhile, in the program / erase / reading method of the present invention, the bias conditions between the source 101b / drain 101a are interchanged with each other in the program / erase / reading method of the present invention, and programming is performed in each of the drain 101a region and the source 101a region. By over erasing (Erasing) operation, a single sono transistor can be operated by two bits. That is, in the case of the present invention, as in the conventional sonos structure, it is possible to operate with one or two bits with one sonos transistor.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The flash memory device and its programming / erasing method of the present invention as described above have the following effects.

The source / drain regions formed on the substrate corresponding to both the gate and the gate are formed by injecting P + type impurities, and a high region is formed in the overlap region between the gate and the drain during programming. Applies a thermal electron scanning method to generate a thermal electron trap to a trap nitride film in the case of a trap, and during erasing, an electric field is formed between the drain region and the gate again so that the trapped hot electrons escape to the substrate side or heat generated when the electric field is formed. By tunneling the holes toward the trap nitride film side, the program and the erasing region are precisely matched so that the electrons accumulate at the impurity region edges of the source / drain any longer.

Therefore, even if the flash memory device of the SONOS structure is programmed or erased repeatedly, the endurance of the device can be improved by suppressing the threshold voltage variation.

In addition, even when the PMOS type SONOS structure flash memory device (i.e., P + type poly gate, P + type source / drain region) is erased by the tunneling method, no electrons are injected into the trap nitride film from the gate. As a result, the erasing of the erase threshold voltage does not occur, thereby increasing the erasing speed and greatly widening the threshold voltage window.

1 is a cross-sectional view showing a conventional flash memory device of the SONOS structure

2 is a schematic diagram illustrating a programming method of a flash memory device having a conventional SONOS structure;

3 is a schematic diagram illustrating a method of erasing a flash memory device having a conventional SONOS structure;

4 is a schematic diagram showing a reading method of a flash memory device having a conventional SONOS structure.

FIG. 5 is a diagram illustrating energy levels of each layer and movement of electrons and holes during erasing of a flash memory device having a conventional SONOS structure. FIG.

6 is a cross-sectional view illustrating a flash memory device having a SONOS structure according to the present invention;

7 is a schematic diagram showing a method of programming a flash memory device of the SONOS structure of the present invention;

8 is a schematic diagram illustrating a method of erasing a flash memory device having a SONOS structure of the present invention;

9 is a schematic diagram showing a reading method of a flash memory device having a SONOS structure according to the present invention;

* Description of symbols on the main parts of the drawings *

100: substrate 101: source / drain

102 tunnel oxide film 103 nitride film

104: block oxide film 105: gate

Claims (6)

Semiconductor substrates; An ONO film formed on a surface of the semiconductor substrate; A P + type poly gate formed on the ONO film; And And source / drain regions defined by implanting P + type impurities into the surface of the semiconductor substrate at both sides of the poly gate. The method of claim 1, And the ONO film is a tunnel oxide film, a trap nitride film, and a block oxide film in order from the bottom. A semiconductor substrate, an ONO film formed on the surface of the semiconductor substrate, a P + type poly gate formed on the ONO film, and source / drain regions defined by doping P + type impurities on the surface of the semiconductor substrate on both sides of the poly gate; In the programming method of a flash memory device, And applying a positive voltage to the gate and a negative voltage to the drain region to form a high electric field in an overlap region between the gate and the drain to trap hot electrons in the ONO layer. The method of claim 3, wherein And the source region and the substrate are grounded or floated. A semiconductor substrate, an ONO film formed on the surface of the semiconductor substrate, a P + type poly gate formed on the ONO film, and source / drain regions defined by doping P + type impurities on the surface of the semiconductor substrate on both sides of the poly gate; In the erase method of a flash memory device, A negative voltage is applied to the gate and a ground is formed in the drain region to form a high electric field in an overlap region between the drain and the gate to draw hot electrons trapped in the ONO film to the drain region or to extract thermal holes in the drain region. A method of erasing a flash memory device, characterized by tunneling in an ONO film. The method of claim 5, And the source region and the substrate are grounded or floated.