US7002849B2 - Method for programming and erasing non-volatile memory with nitride tunneling layer - Google Patents

Method for programming and erasing non-volatile memory with nitride tunneling layer Download PDF

Info

Publication number
US7002849B2
US7002849B2 US10/983,019 US98301904A US7002849B2 US 7002849 B2 US7002849 B2 US 7002849B2 US 98301904 A US98301904 A US 98301904A US 7002849 B2 US7002849 B2 US 7002849B2
Authority
US
United States
Prior art keywords
volatile memory
tunneling layer
layer
nitride
nitride tunneling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/983,019
Other versions
US20050082597A1 (en
Inventor
Tso-Hung Fan
Yen-hung Yeh
Kwang-Yang Chan
Mu-Yi Liu
Tao-Cheng Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Priority to US10/983,019 priority Critical patent/US7002849B2/en
Publication of US20050082597A1 publication Critical patent/US20050082597A1/en
Application granted granted Critical
Publication of US7002849B2 publication Critical patent/US7002849B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits

Definitions

  • the present invention relates to a method for programming and erasing a non-volatile memory. More particularly, the present invention relates to a method for programming and erasing a non-volatile memory with a nitride tunneling layer.
  • the family of the non-volatile memory includes the erasable programmable read-only memory (EPROM) and the electrically erasable programmable read-only memory (E 2 PROM). Particularly, the E 2 PROM can be erased and programmed electrically and is capable of retaining data even if the power is turned off, and therefore is widely used in personal computers and in electronic apparatuses.
  • EPROM erasable programmable read-only memory
  • E 2 PROM electrically erasable programmable read-only memory
  • the E 2 PROM with a silicon oxide/silicon nitride/silicon oxide (ONO) stacked structure is recently developed, which includes the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory and the nitride read-only memory (NROM).
  • SONOS Silicon-Oxide-Nitride-Oxide-Silicon
  • NROM nitride read-only memory
  • a typical NROM is capable of preventing a leakage is because the injected electrons are localized in certain regions in the silicon nitride charge trapping layer. These injected electrons are less likely to locate on the defects in the tunnel oxide layer that would otherwise cause a leakage.
  • silicon oxide has a high energy barrier for an electron and an electron hole, the efficiency of hot carrier (electron or electron hole) injection through the tunnel oxide layer is low when the channel hot carrier injection mechanism is used to program or to erase the SONOS or NROM device. Thus the rates of the programming operation and the erasing operation of the memory device are lowered.
  • this invention provides a method for programming and erasing a non-volatile memory with a nitride tunneling layer, which can promote the efficiency of a programming operation or an erasing operation of a memory device.
  • the method for programming a non-volatile memory with a nitride tunneling layer of this invention comprises the following steps.
  • the gate of the non-volatile memory is applied with a first voltage and the substrate is grounded to turn on the channel between the source and the drain.
  • the drain is applied with a second voltage and the source is grounded to induce a current in a channel and thereby generate hot electrons therein.
  • the hot electrons are injected into a charge-trapping layer of the non-volatile memory and trapped therein through the nitride tunneling layer.
  • the method for erasing a non-volatile memory with a nitride tunneling layer of this invention comprises the following steps.
  • the drain is applied with a first positive bias
  • the gate is applied with a second positive bias
  • the substrate and the source are both grounded to generate hot electron holes in the channel region.
  • the hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer and are recombined with the electrons therein to complete the erasing operation.
  • the first voltage, the second voltage, the first positive bias, and the second positive bias mentioned above are all lower than those used in the operation of the SONOS memory of the same size.
  • the tunneling layer in this invention is made from silicon nitride that has a energy barrier lower than that of silicon oxide used in the prior art, the efficiency of the channel hot carrier injection can be promoted and the operating rates of the memory device are thus increased.
  • the dielectric constant of silicon nitride is higher than that of silicon oxide, lower operating voltages can be used to program or to erase the non-volatile memory with a nitride tunneling layer. Therefore, the critical dimension and the size of a memory cell can be further reduced for a higher integration.
  • FIG. 1 schematically illustrates a non-volatile memory with a nitride tunneling layer according to a preferred embodiment of this invention in a cross-sectional view;
  • FIG. 2 schematically illustrates the method for programming a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
  • FIG. 3 schematically illustrates the method for erasing a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
  • FIG. 1 schematically illustrates a non-volatile memory with a nitride tunneling layer according to a preferred embodiment of this invention in a cross-sectional view.
  • the non-volatile memory with a nitride tunneling layer comprises a substrate 100 , a nitride tunneling layer 102 , a charge-trapping layer 104 , a dielectric layer 106 , a gate conductive layer 108 , a source region 112 , a drain region 114 , and a channel region 116 .
  • the substrate 100 comprises, for example, silicon.
  • the substrate 100 is of n-type (p-type) when the non-volatile memory to be formed is a p-channel (n-channel) memory.
  • the nitride tunneling layer 102 is disposed on the substrate 100 .
  • the nitride tunneling layer 102 is formed by, for example, chemical vapor deposition (CVD).
  • the charge-trapping layer 104 is disposed on the nitride tunneling layer 102 .
  • the material of the charge-trapping layer 104 a is, for example, silicon nitride and the method for forming the charge-trapping layer 104 a is, for example, chemical vapor deposition (CVD).
  • the dielectric layer 106 is formed on the charge-trapping layer 104 .
  • the dielectric layer 106 is formed from, for example, silicon oxide and is formed by, for example, chemical vapor deposition (CVD).
  • the gate conductive layer 108 is disposed on the dielectric layer 106 .
  • the gate conductive layer 108 comprises, for example, polysilicon and is formed by a method such as chemical vapor deposition. Besides, the gate conductive layer 108 , the nitride tunneling layer 102 , the charge-trapping layer 104 , and the dielectric layer 106 together construct a stacked gate structure 110 .
  • the source region 112 and the drain region 114 are formed in the substrate 100 beside the gate structure 110 .
  • the source/drain region 112 / 114 has a conductive type different from that of the substrate 100 , i.e., the source/drain region 112 / 114 is of p-type (n-type) when the substrate 100 is of n-type (p-type).
  • the channel region 116 is located in the substrate 100 under the gate structure 110 and between the source region 112 and the drain region 114 .
  • FIG. 2 schematically illustrates the method for programming a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
  • the gate 110 is applied with a first voltage V 1 and the substrate 100 is grounded to turn on the channel 116 between the source 112 and the drain 114 , wherein the first voltage V 1 ranges from about 6V to about 12V.
  • the drain region 114 is applied with a second voltage V 2 ranging from about 2.5V to about 5V and the source region 112 is grounded to induce a current 118 in the channel region 116 and thereby generate hot electrons.
  • the hot electrons are injected into the charge-trapping layer 104 through the nitride tunneling layer 102 because of the attraction of the gate conductive layer 108 at a higher voltage level.
  • FIG. 3 schematically illustrates the method for erasing a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
  • the drain region 114 is applied with a first positive bias V B1
  • the gate conductive layer 108 is applied with a second positive bias V B2
  • the source region 112 and the substrate 100 are both grounded to generate hot electron holes in the channel region 116 , wherein the first positive bias V B1 ranges from about 2V to about 5V and the second positive bias V B2 ranges from about 2.5V to about 5V.
  • the hot electron holes are injected into the charge-trapping layer 104 through the nitride tunneling layer 102 .
  • the first voltage V 1 , the second voltage V 2 , the first positive bias V B1 , and the second positive bias V B2 mentioned above are all lower than those used in the operation of the SONOS memory of the same size.
  • the dielectric constant of silicon nitride is higher than that of silicon oxide, lower operating voltages can be used to program or erase the non-volatile memory with a nitride tunneling layer. Therefore, the critical dimension and the size of a memory cell can be further reduced for a higher integration.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional application of, and claims the priority benefit of, U.S. application Ser. No. 10/015,414 filed on Dec. 12, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for programming and erasing a non-volatile memory. More particularly, the present invention relates to a method for programming and erasing a non-volatile memory with a nitride tunneling layer.
2. Description of Related Art
The family of the non-volatile memory includes the erasable programmable read-only memory (EPROM) and the electrically erasable programmable read-only memory (E2PROM). Particularly, the E2PROM can be erased and programmed electrically and is capable of retaining data even if the power is turned off, and therefore is widely used in personal computers and in electronic apparatuses.
The E2PROM with a silicon oxide/silicon nitride/silicon oxide (ONO) stacked structure is recently developed, which includes the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory and the nitride read-only memory (NROM). By comparing with the conventional non-volatile memory having a doped polysilicon floating gate, the SONOS memory uses lower voltages for its operation and therefore can be easily scaled down for a higher integration. On the other hand, the NROM is able to prevent a leakage and to store two bits in one memory cell, and therefore has a better performance. A typical NROM is capable of preventing a leakage is because the injected electrons are localized in certain regions in the silicon nitride charge trapping layer. These injected electrons are less likely to locate on the defects in the tunnel oxide layer that would otherwise cause a leakage.
However, since the SONOS memory and the NROM both use silicon oxide as the material of the tunneling layer, the following problems are encountered.
Since silicon oxide has a high energy barrier for an electron and an electron hole, the efficiency of hot carrier (electron or electron hole) injection through the tunnel oxide layer is low when the channel hot carrier injection mechanism is used to program or to erase the SONOS or NROM device. Thus the rates of the programming operation and the erasing operation of the memory device are lowered.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a method for programming and erasing a non-volatile memory with a nitride tunneling layer, which can promote the efficiency of a programming operation or an erasing operation of a memory device.
The method for programming a non-volatile memory with a nitride tunneling layer of this invention comprises the following steps. The gate of the non-volatile memory is applied with a first voltage and the substrate is grounded to turn on the channel between the source and the drain. The drain is applied with a second voltage and the source is grounded to induce a current in a channel and thereby generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile memory and trapped therein through the nitride tunneling layer.
The method for erasing a non-volatile memory with a nitride tunneling layer of this invention comprises the following steps. The drain is applied with a first positive bias, the gate is applied with a second positive bias, and the substrate and the source are both grounded to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer and are recombined with the electrons therein to complete the erasing operation.
Moreover, in the method for programming and erasing a non-volatile memory with a nitride tunneling layer of this invention, the first voltage, the second voltage, the first positive bias, and the second positive bias mentioned above are all lower than those used in the operation of the SONOS memory of the same size.
Since the tunneling layer in this invention is made from silicon nitride that has a energy barrier lower than that of silicon oxide used in the prior art, the efficiency of the channel hot carrier injection can be promoted and the operating rates of the memory device are thus increased.
Besides, since the dielectric constant of silicon nitride is higher than that of silicon oxide, lower operating voltages can be used to program or to erase the non-volatile memory with a nitride tunneling layer. Therefore, the critical dimension and the size of a memory cell can be further reduced for a higher integration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIG. 1 schematically illustrates a non-volatile memory with a nitride tunneling layer according to a preferred embodiment of this invention in a cross-sectional view;
FIG. 2 schematically illustrates the method for programming a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention; and
FIG. 3 schematically illustrates the method for erasing a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 schematically illustrates a non-volatile memory with a nitride tunneling layer according to a preferred embodiment of this invention in a cross-sectional view.
Refer to FIG. 1, the non-volatile memory with a nitride tunneling layer comprises a substrate 100, a nitride tunneling layer 102, a charge-trapping layer 104, a dielectric layer 106, a gate conductive layer 108, a source region 112, a drain region 114, and a channel region 116.
The substrate 100 comprises, for example, silicon. The substrate 100 is of n-type (p-type) when the non-volatile memory to be formed is a p-channel (n-channel) memory.
The nitride tunneling layer 102 is disposed on the substrate 100. The nitride tunneling layer 102 is formed by, for example, chemical vapor deposition (CVD).
The charge-trapping layer 104 is disposed on the nitride tunneling layer 102. The material of the charge-trapping layer 104 a is, for example, silicon nitride and the method for forming the charge-trapping layer 104 a is, for example, chemical vapor deposition (CVD).
The dielectric layer 106 is formed on the charge-trapping layer 104. The dielectric layer 106 is formed from, for example, silicon oxide and is formed by, for example, chemical vapor deposition (CVD).
The gate conductive layer 108 is disposed on the dielectric layer 106. The gate conductive layer 108 comprises, for example, polysilicon and is formed by a method such as chemical vapor deposition. Besides, the gate conductive layer 108, the nitride tunneling layer 102, the charge-trapping layer 104, and the dielectric layer 106 together construct a stacked gate structure 110.
The source region 112 and the drain region 114 are formed in the substrate 100 beside the gate structure 110. The source/drain region 112/114 has a conductive type different from that of the substrate 100, i.e., the source/drain region 112/114 is of p-type (n-type) when the substrate 100 is of n-type (p-type).
The channel region 116 is located in the substrate 100 under the gate structure 110 and between the source region 112 and the drain region 114.
FIG. 2 schematically illustrates the method for programming a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
Refer to FIG. 2, when the non-volatile memory with a nitride tunneling layer is to be programmed, the gate 110 is applied with a first voltage V1 and the substrate 100 is grounded to turn on the channel 116 between the source 112 and the drain 114, wherein the first voltage V1 ranges from about 6V to about 12V. Meanwhile, the drain region 114 is applied with a second voltage V2 ranging from about 2.5V to about 5V and the source region 112 is grounded to induce a current 118 in the channel region 116 and thereby generate hot electrons. The hot electrons are injected into the charge-trapping layer 104 through the nitride tunneling layer 102 because of the attraction of the gate conductive layer 108 at a higher voltage level.
FIG. 3 schematically illustrates the method for erasing a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention.
Refer to FIG. 3, when the non-volatile memory with a nitride tunneling layer is to be erased, the drain region 114 is applied with a first positive bias VB1, the gate conductive layer 108 is applied with a second positive bias VB2, and the source region 112 and the substrate 100 are both grounded to generate hot electron holes in the channel region 116, wherein the first positive bias VB1 ranges from about 2V to about 5V and the second positive bias VB2 ranges from about 2.5V to about 5V. The hot electron holes are injected into the charge-trapping layer 104 through the nitride tunneling layer 102.
Moreover, in the method for programming and erasing a non-volatile memory with a nitride tunneling layer according to the preferred embodiment of this invention, the first voltage V1, the second voltage V2, the first positive bias VB1, and the second positive bias VB2 mentioned above are all lower than those used in the operation of the SONOS memory of the same size.
Besides, since the dielectric constant of silicon nitride is higher than that of silicon oxide, lower operating voltages can be used to program or erase the non-volatile memory with a nitride tunneling layer. Therefore, the critical dimension and the size of a memory cell can be further reduced for a higher integration.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (4)

1. A method of programming a non-volatile memory cell with a nitride tunneling layer, comprising:
providing a non-volatile memory cell comprising:
a substrate
a nitride tunneling layer disposed on the substrate;
a charge-trapping layer disposed on the nitride tunneling layer;
a dielectric layer disposed on the charge trapping layer;
a gate conductive layer disposed on the dielectric layer; and
a source region and a drain region disposed in the substrate adjacent to the nitride tunneling layer;
applying a first voltage to the gate conductive layer and grounding the substrate to turn on a channel between the source region and the drain region; and
applying a second voltage to the drain region and ground the source region to induce a current in the channel and thereby to generate hot electrons in the channel,
wherein the hot electrons are injected into the charge-trapping layer through the nitride tunneling layer to program the nonvolatile memory cell.
2. The method of claim 1, wherein the first voltage ranges from about 6V to about 12V.
3. The method of claim 1, wherein the second voltage ranges from about 2.5V to about 5V.
4. The method of claim 1, wherein the first voltage and the second voltage are both lower than those adopted for programming a substrate-oxide-nitride-oxide-silicon (SONOS) memory having a same size as the non-volatile memory with the nitride tunneling layer.
US10/983,019 2001-12-04 2004-11-05 Method for programming and erasing non-volatile memory with nitride tunneling layer Expired - Lifetime US7002849B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/983,019 US7002849B2 (en) 2001-12-04 2004-11-05 Method for programming and erasing non-volatile memory with nitride tunneling layer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW90129931 2001-12-04
TW090129931A TW519734B (en) 2001-12-04 2001-12-04 Programming and erasing methods of non-volatile memory having nitride tunneling layer
US10/015,414 US6834013B2 (en) 2001-12-04 2001-12-12 Method for programming and erasing non-volatile memory with nitride tunneling layer
US10/983,019 US7002849B2 (en) 2001-12-04 2004-11-05 Method for programming and erasing non-volatile memory with nitride tunneling layer

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US10/015,414 Division US6834013B2 (en) 2001-12-04 2001-12-12 Method for programming and erasing non-volatile memory with nitride tunneling layer
US10/015,414 Continuation US6834013B2 (en) 2001-12-04 2001-12-12 Method for programming and erasing non-volatile memory with nitride tunneling layer

Publications (2)

Publication Number Publication Date
US20050082597A1 US20050082597A1 (en) 2005-04-21
US7002849B2 true US7002849B2 (en) 2006-02-21

Family

ID=21679858

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/015,414 Expired - Lifetime US6834013B2 (en) 2001-12-04 2001-12-12 Method for programming and erasing non-volatile memory with nitride tunneling layer
US10/983,019 Expired - Lifetime US7002849B2 (en) 2001-12-04 2004-11-05 Method for programming and erasing non-volatile memory with nitride tunneling layer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/015,414 Expired - Lifetime US6834013B2 (en) 2001-12-04 2001-12-12 Method for programming and erasing non-volatile memory with nitride tunneling layer

Country Status (2)

Country Link
US (2) US6834013B2 (en)
TW (1) TW519734B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394703B2 (en) * 2002-10-15 2008-07-01 Halo Lsi, Inc. Twin insulator charge storage device operation and its fabrication method
JP2004179387A (en) * 2002-11-27 2004-06-24 Renesas Technology Corp Nonvolatile semiconductor memory and its manufacturing method
US6780708B1 (en) * 2003-03-05 2004-08-24 Advanced Micro Devices, Inc. Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography
US6873550B2 (en) * 2003-08-07 2005-03-29 Micron Technology, Inc. Method for programming and erasing an NROM cell
US20060171200A1 (en) 2004-02-06 2006-08-03 Unity Semiconductor Corporation Memory using mixed valence conductive oxides
US7082052B2 (en) 2004-02-06 2006-07-25 Unity Semiconductor Corporation Multi-resistive state element with reactive metal
US7538338B2 (en) * 2004-09-03 2009-05-26 Unity Semiconductor Corporation Memory using variable tunnel barrier widths
US20130082232A1 (en) 2011-09-30 2013-04-04 Unity Semiconductor Corporation Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells
US8426906B2 (en) * 2008-04-18 2013-04-23 Macronix International Co., Ltd. Method and structure for a semiconductor charge storage device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500816A (en) * 1993-07-30 1996-03-19 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device and manufacturing method thereof
US6172907B1 (en) * 1999-10-22 2001-01-09 Cypress Semiconductor Corporation Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same
US6566680B1 (en) * 2001-01-30 2003-05-20 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) tunneling junction transistor
US6724661B2 (en) * 2001-06-21 2004-04-20 Samsung Electronics Co., Ltd. Erasing method in non-volatile memory device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4353083A (en) * 1978-11-27 1982-10-05 Ncr Corporation Low voltage nonvolatile memory device
JPS60151898A (en) * 1984-01-18 1985-08-09 Nec Corp Non-volatile random access memory cell
US5739569A (en) * 1991-05-15 1998-04-14 Texas Instruments Incorporated Non-volatile memory cell with oxide and nitride tunneling layers
DE69323484T2 (en) * 1993-04-22 1999-08-26 Stmicroelectronics S.R.L. Method and circuit for programming the tunnel effect of a floating gate MOSFET
US6005809A (en) * 1998-06-19 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Program and erase method for a split gate flash EEPROM
US6208557B1 (en) * 1999-05-21 2001-03-27 National Semiconductor Corporation EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming
KR100308192B1 (en) * 1999-07-28 2001-11-01 윤종용 Flash memory devcie capable of preventing an over-erase of flash memory cells and an erasure method thereof
KR100383766B1 (en) * 1999-12-28 2003-05-14 주식회사 하이닉스반도체 Method of erasing a flash memory device
US6941505B2 (en) * 2000-09-12 2005-09-06 Hitachi, Ltd. Data processing system and data processing method
US6465306B1 (en) * 2000-11-28 2002-10-15 Advanced Micro Devices, Inc. Simultaneous formation of charge storage and bitline to wordline isolation
US6563741B2 (en) * 2001-01-30 2003-05-13 Micron Technology, Inc. Flash memory device and method of erasing
US6445030B1 (en) * 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. Flash memory erase speed by fluorine implant or fluorination
US6418040B1 (en) * 2001-04-09 2002-07-09 Cypress Semiconductor Corp. Bi-directional architecture for a high-voltage cross-coupled charge pump
US6436768B1 (en) * 2001-06-27 2002-08-20 Advanced Micro Devices, Inc. Source drain implant during ONO formation for improved isolation of SONOS devices
TW495977B (en) * 2001-09-28 2002-07-21 Macronix Int Co Ltd Erasing method for p-channel silicon nitride read only memory
US7061810B2 (en) * 2001-10-09 2006-06-13 Micron Technology, Inc. Erasing flash memory without pre-programming the flash memory before erasing
US6448137B1 (en) * 2001-11-02 2002-09-10 Macronix International Co. Ltd. Method of forming an NROM embedded with mixed-signal circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500816A (en) * 1993-07-30 1996-03-19 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device and manufacturing method thereof
US6172907B1 (en) * 1999-10-22 2001-01-09 Cypress Semiconductor Corporation Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same
US6566680B1 (en) * 2001-01-30 2003-05-20 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) tunneling junction transistor
US6724661B2 (en) * 2001-06-21 2004-04-20 Samsung Electronics Co., Ltd. Erasing method in non-volatile memory device

Also Published As

Publication number Publication date
US20050082597A1 (en) 2005-04-21
TW519734B (en) 2003-02-01
US6834013B2 (en) 2004-12-21
US20030103383A1 (en) 2003-06-05

Similar Documents

Publication Publication Date Title
US6671209B2 (en) Erasing method for p-channel NROM
US7576386B2 (en) Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
US8481388B2 (en) Non-volatile memory device having a nitride-oxide dielectric layer
US6545309B1 (en) Nitride read-only memory with protective diode and operating method thereof
US6580135B2 (en) Silicon nitride read only memory structure and method of programming and erasure
US6498377B1 (en) SONOS component having high dielectric property
KR101308692B1 (en) Method for erasing and programming memory device
US20060203562A1 (en) Twin insulator charge storage device operation and its fabrication method
US20050285184A1 (en) Flash memory device and method for programming/erasing the same
US7483309B2 (en) Programming and erasing method for charge-trapping memory devices
US8264884B2 (en) Methods, circuits and systems for reading non-volatile memory cells
US6801456B1 (en) Method for programming, erasing and reading a flash memory cell
US7682908B2 (en) Non-volatile memory and operating method thereof
US20050162925A1 (en) Non-volatile memory cell array having common drain lines and method of operating the same
US7092298B2 (en) Methods of erasing a non-volatile memory device having discrete charge trap sites
US7002849B2 (en) Method for programming and erasing non-volatile memory with nitride tunneling layer
JP2004134799A (en) Single-bit non-volatile memory cell, its programming method, and its erasing method
US7599229B2 (en) Methods and structures for expanding a memory operation window and reducing a second bit effect
US7200040B2 (en) Method of operating p-channel memory
US7088623B2 (en) Non-volatile memory technology suitable for flash and byte operation application
US7512013B2 (en) Memory structures for expanding a second bit operation window

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12