CN1612350A - Nonvolatile storage technique of byte operation for flash memory - Google Patents
Nonvolatile storage technique of byte operation for flash memory Download PDFInfo
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- CN1612350A CN1612350A CN 200310104651 CN200310104651A CN1612350A CN 1612350 A CN1612350 A CN 1612350A CN 200310104651 CN200310104651 CN 200310104651 CN 200310104651 A CN200310104651 A CN 200310104651A CN 1612350 A CN1612350 A CN 1612350A
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Abstract
The disclosed structure of nonvolatile memory unit is suitable to EEPROM unit in order to carry out operations of programming byte word and erasing byte word. In operation of programming byte, a higher negative voltage is applied to drain region. Thus, hot holes are generated in order to reduce thermions, which pass through oxidizing layer of inner tunnel in transverse electric field. Grid voltage is about threshold voltage, which is dependent on design of IC circuit device. Using Fowler-Nordheim tunnel effect, nonvolatile memory unit carries out erasing operation. Drain electrode junction is in use as a disable switch in order to execute erasing operation. Drain electrode being biased to ground, unselected units on same byte word line are forbidden. In the invention, byte word lines of unselected units are connected to ground.
Description
Technical field
The present invention relates generally to the non-volatile memory cells that is suitable for operating, and relate more particularly to the non-volatile memory cells that is applicable to that quickflashing and byte manipulation are used.
Prior art is described
Semiconductor based on storage device comprises widely: random asccess memory (RAM) and read-only memory (ROM).RAM is referred to as volatile memory, and when the loss of voltage that applies, disappearance has in time destroyed data.The ROM device comprises programming ROM (PROM), can wipe PROM (EPROM), and electricity is wiped EPROM (EEPROM).Can wipe simultaneously by a stacked gate structure, and characterize numerous EEPROM unit and flash memory cells.
The programming operation of conventional P raceway groove stacked gate flash cells is to utilize the raceway groove hot hole to induce hot electron, makes electronics enter floating grid.In addition, erase operation is to utilize by pass through tunnel FN (Fowler-Nordheim) tunnel effect (FN tunneling) of oxide of FN tunnel, and electronics is attracted to substrate from floating grid.Therefore programming operation is a byte manipulation, rather than erase operation.
Fig. 1 illustrates a traditional E EPROM unit 100, in this unit 100, by unit 100 threshold voltages being programmed in a plurality of predetermined levels, can represent the binary condition more than two.When reading EEPROM unit 100, Chuan Dao current level depends on its threshold voltage there.
By with an erasing voltage V between 16 to 20 volts
EBe applied to control grid 120,16 to 20 volts of voltages be added to select 122,0 volts of electricity of grid to be applied to bit line, and allow source area suspend.Thus, the 20 electronics tunnels to floating grid 116 have increased the threshold voltage V of memory transistor 104 from the drain region
t
By program voltage V with a 13-20 volt
PpBe applied to bit line and select grid 122, will control grid 120 ground connection simultaneously and allow source area 108 be in high-impedance state, can programme EEPROM unit 100.Synthetic electric field makes the electronics of tunnel oxide move to drain region 112 from floating grid 116.Thus, the threshold voltage V of floating grid 116 discharges and minimizing EEPROM unit 100
tLike this by adjusting program voltage V
Pp, can control the synthetic V of memory transistor 104 during the read operation
tAnd the electric current that produces by EEPROM unit 100.
By from the floating grid to the source electrode (source erase) or to the electronics F-N tunnel effect of passage (passage is wiped), can carry out electricity and wipe.Electricity wipe remove during, produce the zoneofoxidation of every centimetre of 10MV level on the thin-oxide between floating grid and n+ source diffusion (or passage).This can be realized by three kinds of method for deleting.The degree of cell erasure is controlled by circuit, and is undertaken by a series of wiping with erase check operative algorithmization ground.Each erasing pulse width typically is 10 milliseconds, and subsequently by the sampling unit electric current, carries out an erase threshold checked operation.
A kind of method for deleting is that grid source ground connection is wiped, be by with source-biased to high potential, about 12V, and will control that grid and substrate ground connection realizes.Drain node allows to float, and this causes that electronics is tunneling to source electrode from floating grid, makes floating grid discharge or " wiping ".Under the grounding requirement of grid source, source-biased produces important (band-to-band) tunnel current that takes to.On substrate, collect this electric current.Because the source knot is biased in nearly snowslide situation, taking belt current to has some multiplication.This electric current plays the voltage clamp effect, thus, because further limit the increase of junction voltage in the sheet by the voltage drop of transistor (pass transistor).If substrate current is enough big, the hot hole cave that is caused by puncture can begin eraseable memory unit.The hot hole cave is wiped to handle and is difficult to control, and is avoided in the memory cell of design well.
In addition, be absorbed in the gate oxide by some hot hole cave of taking the tunnel effect generation to.This can cause erase threshold inhomogeneous, periodically quickens the pf erasing time, reduces charge retention, or accelerating grid electrode is upset.Keep balance can simplify memory cell structure with these passive points.This has caused the suitable effort in engineering junction, so that this influence reduces to minimum.
Another kind method is that wipe in the negative grid source, be by source node being biased in VCC (5V), and will make an appointment with-10V is added on the control grid and realizes.At the A of grounded circuit, electronics from floating grid through the diffusion region, source.As a result, wiped memory cell.Take tunnelling to and produce the hole, yet, because reduced transverse electric field (only being 5V) between source and the substrate, be not heated to ground connection and wipe same degree at source node.Like this, can reduce by taking the reaction that tunnelling produces the hot hole cave to.
When wiping, typical operation will be carried out positive charge with respect to ground to floating grid, and when programming, floating grid be carried out the negative sense charging with respect to ground.In order to read memory transistor.Make the control grounded-grid, forward ground biasing control grid, the low impedance path that drains and contact with drain electrode and the memory transistor that it is provided.The drain electrode contact is provided to the connection of metal bit line.Bit line is biased in suitable forward voltage (for example 2V) and the common source polar curve is biased to ground.If wipe floating grid, electric current can flow to source area from bit line.If the grid programming, memory transistor is in nonconducting state, and does not have electric current to flow through.The existence of sample rate current or do not exist is with the state of determining to be stored by memory transistor.
Oxide thickness in the tunneling window typically is 10 nanometers.For memory cell is programmed, the grid of suspension must be capacitively coupled to respect to drain electrode has enough positive potentials, has the electric field of every centimetre of 10MV on the tunnel oxidation spy.This will select gate bias on sufficiently high current potential by to the about 20V of polyethylene 2 control grid bias simultaneously, the earthy bit line of selection transistor AND gate be conducted electricity realize.Under these conditions, the drain region provides an electron source at the tunnel oxide cathode side.The electric field that has every centimetre of 10MV on the tunnel oxide causes the Fowler-Nordheim tunnel effect, and suspended grid is carried out the negative sense charging.
In order to wipe memory transistor, the biasing on the tunnel oxide must be oppositely.This is by drain electrode applies a high bias voltage to memory transistor, and making polyethylene 2 control grid bias simultaneously is earth potential, is coupled to a low-voltage with the retentive control grid capacitance.By desired voltage is applied to bit line, will select transistor gate to be biased in some current potentials simultaneously, drain electrode applies a high pressure to memory transistor, and described a certain current potential is than the transistorized threshold voltage of the high at least selection of desired voltage.
Abstract of invention
An object of the present invention is to provide a kind of cellular construction, can be compatible with flash memory cell and EEPROM unit (electric erasable read only programmable storage) and use, to reduce the die size.
Another object of the present invention is that flash memory cell and EEPROM unit (automatically controlled except that read-only programmable storage) are combined in the cellular construction, to carry out the operation of byte writing and byte-erase.
Another object of the present invention provides a cellular construction that has single transistor, to carry out byte manipulation, reduces the complexity of handling and has reduced cost effectively with activation.
According to above-mentioned purpose, the invention provides a kind of nonvolatile storage technologies structure, be suitable for flash memory cell and EEPROM unit (electric erasable read only programmable memory cell), to carry out byte programming and byte-erase operation.Cellular construction comprises grid pile (gate stack) and its insulation system on the substrate.Grid pile comprises floating grid and the control grid on the substrate.Below the channel region external oxidation thing on the scene, and LDD district (lightly doped drain) is in substrate tonequality outside the venue below the oxidation special zone.Spacer on the grid pile side wall (liner spacer) and source/drain region are below tunnel oxidation layer, and adjacent to the LDD district.
During programming operation, negative voltage is applied to the drain region, produces the hot hole cave like this, makes hot electron enter floating grid by tunnel oxidation layer.In addition, grid voltage is about threshold voltage V
t, this voltage necktie designs in integrated voltage.
In addition, non-volatile memory cells utilizes raceway groove Fowler-Nordheim tunnel effect, is used for erase operation.In order to carry out the byte-erase operation, drain node is as a disable switch.Like this, by drain bias is forbidden unchecked unit on the same word line for ground.Therefore, the word line ground connection of not selecting.
From following together with will more understanding the present invention other purposes, advantage and notable feature the detailed description of accompanying drawing.These accompanying drawings have disclosed preferred embodiment of the present invention.
The accompanying drawing summary
The aforementioned aspect of the present invention and follow the advantage will easier appreciation: when together with accompanying drawing, will similarly can understand better by the following detailed description of reference.
Fig. 1 is the cross-sectional view of EEPROM unit (electro erasible programmable read-only memory unit), and with traditional, prior art is to a progressive programming and the erase operation in the multistage threshold voltage;
Fig. 2 is the cross-sectional view that has a transistorized non-volatile memory cells, carries out suitable byte programming and byte-erase operation according to a kind of structure that discloses here.
Fig. 3 is the top view of non-volatile memory cells, to describe according to the programming operation that discloses structure here.
Fig. 4 is the top view of non-volatile memory cells array, describes the foundation erase operation of description scheme here.
Preferable enforcement is described
To go through some sample embodiment of the present invention now.Yet will be appreciated that: except clearly describing the embodiment, can in other embodiment broad range, carry out the present invention, in accessory claim, describing in detail, clearly not limit category of the present invention.
The invention provides a kind of P raceway groove non-volatile memory cells, be suitable for the interior byte manipulation and the quickflashing operation (flash operation) of identical chips of chip-scale (SOC) epoch system.Therefore, the invention provides a kind of flash memory cell, utilize a transistor, carry out byte manipulation, reduce the space of memory cell with activation, and can simplify complicated processing procedure, and greatly reduce cost by using P raceway groove non-volatile memory cells.
With reference to figure 2, the invention provides a kind of transistor flash memory cell 10 that has, the N type well 14 that this memory cell comprises P type substrate 12 and forms on substrate, wherein, the conductivity of P type is opposite with the N type.Form a P channel MOS (metal-oxide semiconductor (MOS)) stacked gate transistor 18 on the P substrate 12.In N-type well 14, form the drain electrode 24 of the P-type conduction rate of P channel MOS stacked gate memory transistor 18.Similarly, form the source electrode 22 of the P-type conduction rate of P-channel MOS stacked gate memory transistor 18 in N-type well 14, it and drain region 24 separate.In addition, source area 22 is separated by isolation structure (not shown among Fig. 2), Controlling Source pole tension so respectively, and wherein, isolation structure can be LOCOS (field oxide region) or STI (shallow ridges trench isolations) 14.
P channel MOS stacked gate storage crystal 18 contains floating grid 18a, typically is polysilicon, be positioned at tunnel oxide 16 above.The floating grid 18a and the source area 22 of P-channel MOS stacked gate memory transistor 18 separate.Control grid 18c is positioned above the floating grid 18a.In addition, first insulating barrier 16 as tunnel oxidation layer is placed between floating grid 18a and the N-type well 14, and be placed between floating grid 18a and the control grid 18c as the second insulating barrier 18b of interpretation medium (IPD) layer, wherein, the material of IPD layer 18b can be ONO layer (oxide/chloride/oxide).
In order to carry out byte programming and byte-erase operation in non-volatile memory cells, preferred embodiment of the present invention provides a kind of transistorized memory cell that has, and with the size of minimizing cellular construction, and strengthens the property.In addition, programming operation utilizes the raceway groove hot hole, hold electronics with minimizing and inject, and erase operation utilizes FN (Fowler-Nordeim) tunnel effect.Like this, the voltage of programming or erase operation is low, and its power consumption is little.
As shown in Figure 3, the programming operation that has a transistorized nonvolatile storage is similar to the programming operation of traditional flash cell.By making an appointment with-4 to-6 volts negative voltage to be applied to the drain region, to produce hot electron, wherein hot electron has high-energy, and near the raceway groove the drain region.Hot electron quickens to stride across tunnel oxidation layer, and enters floating grid.Hot electron carries out the floating grid that centered on by insulating barrier.When grid was between control grid and N-type well, this grid was " floating grid ", is free of attachment to word line, bit line, or other lines.Insulating barrier can comprise interpretation dielectric layer and tunnel oxidation layer.Floating grid will increase the threshold voltage V of non-volatile memory cells
tPassing threshold voltage V
tThis change non-volatile memory cells is programmed, set up the channel conduction of non-volatile memory cells by floating grid.Even after turning off the power supply of memory cell, floating grid can almost keep electric charge indefinitely.
During programming operation, with reverse drain voltage V
DdBe applied to the drain region, and grid voltage V
gBe about threshold voltage V
t, this threshold voltage depends on design, wherein the threshold voltage V in preferred embodiment
tBe about-4 volts.By drain voltage V
DdBe higher than threshold voltage V
t, produce the hot electron that injects floating grid from raceway groove process of passing through tunnel oxide layer, like this, electronics is kept in the floating grid.In addition, during programming operation, biasing only allows sub-threshold current to flow in flash cells, and like this, the notes of this flash cells are put efficient than higher, and have reduced the power consumption of integrated circuit (IC) apparatus.
On the other hand, in cell array not the word line 0 of menu element apparatus be applied with a threshold voltage V
t, and word line 1 ground connection (0 volt) of menu element apparatus not.Bit line 0 is applied with a negative drain voltage V
Dd, bit line 1 ground connection.
In addition, in order during programming, to prevent diffusion, word line 1 ground connection, the voltage of word line 0 is near negative threshold voltage, V
g=-V
tBut, bit line 1 ground connection, transistor presents off-state like this.Because do not produce thermionic transverse electric field, so that can not produce hot electron.Thereby, can not programme.Thereby gridistor is in off-state, and the threshold voltage that imposes on word line 0 is higher than drain voltage V
Dd
With reference to figure 4, preferred embodiment of the present invention provides the flash memory cell of being wiped by raceway groove Fowler-Nordheim (FN) tunnel effect.In order to carry out the byte-erase operation, with erasing voltage V
EBe applied to bit line 0, with N-type well and bit line 1 ground connection, word line 0 is applied with a negative voltage V
Pp, and with word line 1 and bit line 1 ground connection.In addition, the voltage of source electrode line 0 and source electrode line 1, therefore, source voltage shows suspended state, and with erasing voltage V
EBe applied to the N-wellblock.Come automatic biasing+V
PpWith-V
EHigh electric field move the floating grid electronics to N-type well by the F-N tunnel effect.
For P-type channel flash unit, control gate pole tension V
CGThan higher (negative less), electronics is retained in floating grid simultaneously, and on the contrary, when electronics leaves from floating grid, the process of passing through tunnel oxide layer enters N-type well and advances, control gate pole tension V
CGReduce (more negative).
If control voltage V
CGBe higher than threshold voltage V
t, P channel flash transistor will " be opened ", to carry out erase operation.On the other hand, when voltage being applied to grid PMOS is opened, the N-type advances lip-deep raceway groove to be increased.If bit line is biased to positive V
E, high electric field Electronic Control grid (V
Pp) and raceway groove (+V
E) electronics is pulled out from floating grid, through the F-N tunnel effect, the oxide that passes through tunnel arrives raceway groove.If bit line biasing ground connection, control grid (V
PpOr ground) and the electric field between the raceway groove (ground connection) do not have sufficient intensity help FN tunnel effect (F-N tunneling) that electronics is pulled out from floating grid.Therefore, by selecting WL and BL line, can reach word and wipe.
In addition, divide source electrode line (source electrode line 0 and source electrode line 1) by isolation structure along the bit line direction, this isolation structure comprises and stops on the same word line isolation structure of leakage current between the different units.In order to exempt the constraint of peripheral unit inner high voltage, negative voltage is applied to grid, and positive voltage is applied to drain region and n wellblock.Like this, thin gate oxide and lower V
BDSSCan keep this non-volatile higher operating voltage operation, to simplify processing procedure and to reduce cost.
According to top description, advantage of the present invention is as follows: at first, non-volatile memory cells only utilizes a transistor to carry out byte programming operation and byte-erase operation, like this, can reduce this device area, to reduce the size of integrated voltage.It is suitable for having the quickflashing and the EEPROM application of a transistor technology.
The second, operating voltage is littler than EEPROM or traditional flash memory cell, can reduce cost like this and power consumption, also simplifies manufacture process.
The 3rd, during erase operation, channel potential is trusted the state in bit line, so that the transistor electric field does not have sufficient intensity to carry out erase operation, pull down to N-type well from floating grid, or prevention is wiped to reduce electric field strength.
Though illustrated and described specific embodiment, clearly; Those persons skilled in the art can make various modifications, do not deviate from the category that only tends to by the accessory claim restriction.
Claims (11)
1, a kind of non-volatile memory cell structure is characterized in that, described structure comprises:
N-type wellblock is in substrate; Channel region, between P type source area and P type drain region, the conductivity type of wherein said P type is opposite with described N type;
First insulating barrier, the described surface in described N type wellblock;
Floating grid is on described first insulating barrier;
Second insulating barrier is on described floating gate; And
The control grid on described second insulating barrier, wherein, by erasing voltage being applied to described P type drain region, is applied to described control grid with supply voltage, and described erasing voltage is applied to described N type wellblock, wipes described non-volatile memory cells.
According to the described structure of claim 1, it is characterized in that 2, described erasing voltage is in about 12 volts.
3, according to the described structure of claim 1, it is characterized in that, further comprise a source electrode line, be coupled to described P type source area, described source electrode line presents suspended state.
4, according to the described structure of claim 3, it is characterized in that, divide described source electrode line along a bit line direction by a kind of isolation structure line.
5, a kind of semiconductor storage unit structure is characterized in that, described structure comprises:
N type wellblock is in substrate; Channel region, between P type drain region and P type source area, wherein, described N type conductivity type is opposite with described P type;
Insulating barrier is on N type wellblock; And
A gridistor, on described insulating barrier, described gridistor comprises a control grid, be coupled to a word line, a bit line is coupled in described P type drain region, wherein, and by an erasing voltage in 12 volts being applied to described P type drain region, and supply voltage is applied to described control grid, wipe described unit.
6, according to the described structure of claim 5, it is characterized in that,
Described P type source area is coupled to a source electrode line.
7, according to the described structure of claim 6, it is characterized in that, divide described source electrode line along a bit line direction by using a kind of isolation structure.
According to the described structure of claim 5, it is characterized in that 8, the supply voltage that is applied to described N type wellblock is an erasing voltage.
9, according to the described structure of claim 5, it is characterized in that, apply P type drain region with the minimizing hot electron, and an about negative threshold voltage of 2 volts is applied to described word line, programmed in described unit by the negative supply voltage between a 6-10 is lied prostrate.
10, a kind of method that is used for the erasable nonvolatile memory cell, described non-volatile memory cells contain the N type wellblock on a P type substrate and the P type substrate, the channel region between P type drain region and P type source area, and described method comprises step:
Erasing voltage is applied to described P type drain region, and to cause the tunnel effect of electronics from the unsteady utmost point to described N type wellblock, a bit line is coupled in wherein said P-type drain region;
Supply voltage is applied to the control grid, and wherein said control grid is coupled to a word line; And
With the bit line ground connection of the word line of described not menu unit and described not menu unit, so that P type drain region is as a disable switch.
11, in accordance with the method for claim 10, it is characterized in that described erasing voltage is about 12 volts.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101046517A CN100367504C (en) | 2003-10-28 | 2003-10-28 | Nonvolatile storage technique of byte operation for flash memory |
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|---|---|---|---|
| CNB2003101046517A CN100367504C (en) | 2003-10-28 | 2003-10-28 | Nonvolatile storage technique of byte operation for flash memory |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881592B (en) * | 2005-05-12 | 2010-05-12 | 三星电子株式会社 | Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices |
| CN101067970B (en) * | 2006-05-05 | 2010-12-01 | 旺宏电子股份有限公司 | Method of operating a P-channel be-sonos NAND flash memory |
| CN102117835A (en) * | 2011-01-19 | 2011-07-06 | 北京大学 | Resistance-variable field effect transistor with ultra-steep sub-threshold slope and production method thereof |
| CN101859775B (en) * | 2009-04-07 | 2012-10-03 | 北京兆易创新科技有限公司 | Non-volatile memorizer and manufacturing, programming and reading method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293328A (en) * | 1992-01-15 | 1994-03-08 | National Semiconductor Corporation | Electrically reprogrammable EPROM cell with merged transistor and optiumum area |
| JP3328463B2 (en) * | 1995-04-06 | 2002-09-24 | 株式会社日立製作所 | Parallel nonvolatile semiconductor memory device and method of using the same |
| JPH1083689A (en) * | 1996-09-10 | 1998-03-31 | Mitsubishi Electric Corp | Semiconductor non-volatile memory |
| CN1226782C (en) * | 2002-01-14 | 2005-11-09 | 联华电子股份有限公司 | Operation process of non-volatile memory element |
-
2003
- 2003-10-28 CN CNB2003101046517A patent/CN100367504C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881592B (en) * | 2005-05-12 | 2010-05-12 | 三星电子株式会社 | Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices |
| CN101067970B (en) * | 2006-05-05 | 2010-12-01 | 旺宏电子股份有限公司 | Method of operating a P-channel be-sonos NAND flash memory |
| CN101859775B (en) * | 2009-04-07 | 2012-10-03 | 北京兆易创新科技有限公司 | Non-volatile memorizer and manufacturing, programming and reading method thereof |
| CN102117835A (en) * | 2011-01-19 | 2011-07-06 | 北京大学 | Resistance-variable field effect transistor with ultra-steep sub-threshold slope and production method thereof |
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