JPH09252059A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor device which can be micronized in size and enhanced in reliability, dispensing with a selection transistor. SOLUTION: A nonvolatile semiconductor memory device is composed of a second conductivity-type first diffusion layer 20, a second conductivity-type second diffusion layer 21, and a gate electrode formed on a part of a channel region located between the diffusion layers 20, 21 and on a part of the first diffusion layer through of a first insulating film, wherein a part of a second insulating film of at least two-layered structure formed on the channel region between the gate electrode and the second diffusion layer 21 of 30nm or less in thickness is made to serve as a charge storage layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device that performs data write, erase and read operations.

[0002]

2. Description of the Related Art In recent years, MONOS (Metal-Oxide-Nit) has been used as a memory cell of an electrically writable / erasable nonvolatile memory (flash EEPROM).
A memory cell having a Ride-Oxide-Silicon structure has been proposed. FIG. 16 is a diagram for explaining a memory cell having a MONOS structure. In FIG. 16, 1 is a substrate or well (P-type impurity region), 2 is a drain (dense N-type impurity region), 3 is a source (dense N-type impurity region), 4 is a silicon oxide film, 5 is a SiN film, 6
Is a silicon oxide film, 7 is a control gate, and 9 is an oxide film formed after processing the laminated gate. In this type of memory cell, charges are injected into the SiN film (5) of the gate insulating film so that the charges are trapped in the charge trap centers in the SiN film (5), or the trapped charges are injected into the SiN film (5). Control the cell threshold by pulling out from the inside,
It has a memory function. In a nonvolatile memory having MONOS type memory cells, the following writing method,
Erasing and reading methods have been proposed. (Here, “writing” is defined as injection of charges into the SiN film, and erasing is defined as extraction of charges from the SiN film.) As a writing method, a channel region (8) near the drain (2) is used as a channel. A method of generating hot electrons (CHE) and injecting electrons into the SiN film (5), applying a high electric field between the control gate (7) and the drain (2), or the channel region (8) or the source (3). By FN (Fowler-Nordhei) in the SiN film (5)
m) The injection method is typical. Further, as an erasing method, high electrolysis is applied between the control gate (7) and the source (3) or the drain (2) or the channel region (8) so that electrons in the SiN film are FN to the substrate side.
A typical method is to emit as (Fowler-Nordheim) tunnel current.

[0003]

[Problems to be Solved by the Invention] With an FN tunnel,
MONO for programming / erasing with source or drain
In the S-type cell, it is necessary to apply a high electric field in the charge injection region of the gate insulating film. In this case, if the surface impurity concentration of the source or drain region under the gate insulating film is low, depletion occurs in the region under the gate insulating film to which a high electric field is applied, and a sufficient electric field cannot be generated. Further, even when the distance between the source or drain region serving as an electrode and the gate electrode is large, a sufficient electric field is not generated. When a high electric field is not applied in this way, sufficient FN tunnels do not occur, and the write / erase characteristics deteriorate. Therefore, when writing or erasing, the F
In the method using the N tunnel, it is necessary to provide a sufficient overlap region between the source or drain diffusion layer and the gate electrode and keep the impurity concentration of the source or drain under the gate electrode at a high concentration. is there. Even when writing with CHE from the drain, since the injection efficiency of hot electrons is not lowered, the concentration of drain impurities under the gate electrode cannot be lowered like FN writing / erasing. For the above reasons, the impurity concentration of the source or drain cannot be lowered, so that a shallow junction cannot be formed, which poses a serious problem for miniaturization of the cell transistor. When FN implantation is used, a high electric field is applied, so that the energy of charges passing through the insulating film becomes high, which causes deterioration of the insulating characteristics of the insulating film and an increase in the amount of charge traps generated in the insulating film. This causes deterioration of the rewriting characteristic and the data retention characteristic of the nonvolatile memory.

In the MONOS cell, in the NOR type cell in which the selection transistor is not formed, when writing / erasing is performed, data is destroyed in the non-selected cell sharing the same bit line or word line as the selected cell. The disturb phenomenon becomes a problem. For example, when writing is performed by injecting electrons into the ONO (Oxide-Nitride-Oxide) insulating film by CHE on the drain side, the drain of the first written cell is written until the writing of the cell sharing the same bit line is completed. Is continuously under high potential stress.
Since this stress electric field tends to cause electrons to escape from the ONO insulating film to the drain side, when the loss of electrons due to this stress is large at the time when writing of cells on the same bit line is completed, data is inverted and data is destroyed. The problem that occurs occurs.

In the MONOS type cell in which writing / erasing is performed by FN tunnel in the channel region, when a matrix type cell array is formed by word lines and bit lines, a selection transistor is required to prevent erroneous writing. When forming a NOR type cell array, there is a disadvantage that it is not suitable for miniaturization because a selection transistor is required for each cell. In the NAND type, the number of select transistors is two for one NAND connection, which is smaller than in the case of NOR type connection, but since the cells are connected in series, the write amount at the time of writing and erroneous writing at the time of writing are prevented. Therefore, there is a problem in that the control of the potential applied to the non-written cells becomes complicated and the number of control circuits increases.

[0006]

According to the present invention, an offset region between a gate and a diffusion layer is formed in a channel region below a side surface of a gate of a memory cell, and an insulating film having an ONO structure is formed in this region. In the present invention, charges are injected into the SiN film in the ONO insulating film and trapped in the charge trap centers in the SiN film, thereby writing is performed and the trapped charges are extracted from the SiN film or trapped. Erasing is performed by injecting a charge having a pole opposite to the generated charge. Since the resistance of the channel is modulated by the presence / absence of charges in the ONO insulating film and the polarity (positive / negative), the current flowing through the cell changes. The present invention is characterized by utilizing this phenomenon as a memory function. Another method of the present invention is to use a polysilicon electrode doped with impurities, for example, on the gate side wall, and control the potential under the polysilicon electrode by capacitive coupling with the gate electrode to improve the efficiency of charge injection. Controllability can be improved.
The use of the cell of the present invention eliminates the need for a select transistor unlike the MONOS cell which performs writing and erasing in the channel region. Further, in the cell of the present invention, it is not necessary to form a source or drain diffusion layer high-concentration diffusion layer to be an electrode on the injection side, so that a shallow diffusion layer can be formed and the cell transistor can be miniaturized. In the present invention, the method of injecting charges into the insulating film uses hot carriers or avalanche hot carriers by band-to-band tunneling at the drain or the source to be the injection electrode. At this time, the charge injected into the insulating film can be selected as an electron or a hole by controlling the potential of the gate. The energy of the hot carriers generated here is lower than that of the hot carriers generated by the FN current, and the damage to the insulating film is reduced, so that the reliability of the cell can be improved. Further, in the disturb for the non-selected cells on the same bit line, the gate potential of the non-selected cells is shown in FIG.
As in Va of 4, the disturb can be almost eliminated by bringing the potential close to a potential under which neither electron nor hole is injected.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Next, the best mode for carrying out the present invention will be described with reference to FIGS. 1 is a sectional view of a nonvolatile semiconductor memory cell according to a first embodiment of the present invention. Subsequently, a method of manufacturing the nonvolatile semiconductor memory cell according to the first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 2, after a predetermined element isolation region (10) is formed on the substrate (1) by a well-known technique, a silicon oxide film as a first insulating film layer is formed on the silicon substrate in the memory cell region. (11) is formed, and polysilicon (12) is formed on the first silicon oxide film, for example, 100 to 200.
Then, n-type impurities such as arsenic and phosphorus are doped to a concentration of, for example, 2 to 4e20 cm −3 by a well-known technique. The first insulating film (11) is formed by oxidizing a silicon substrate or depositing a silicon oxide film. Here, in order to reduce the resistance of the gate electrode, a refractory metal silicide layer such as WSi or MoSi is deposited on the polysilicon (12) to form a polycide structure, or a refractory metal such as W is deposited. It has a polymetal structure.

Subsequently, as shown in FIG. 3, the gate of the memory cell is patterned to form a gate electrode (13), and an oxide film or a silicon oxide film is deposited to form an oxide film (14). The thickness of the oxide film (14) is set so that the electric field in the charge injection region becomes sufficiently strong, and tunnels to the charge storage layer easily occur.
The film thickness is 0 nm or less. The lower limit of the film is preferably 2 nm or more in order to suppress the back tunnel from the charge injection layer. At this time, in order to adjust the threshold value of the channel in the charge injection region, predetermined impurities can be introduced into the substrate by a well-known technique such as ion implantation before oxidation or oxide film deposition.

Next, when the offset region side of the cell transistor is formed on the source side as shown in FIG. 4, the source region is masked with, for example, a photoresist (15) or the like, and N is formed by a well-known technique such as ion implantation. A type impurity is introduced to form an N type diffusion layer (16) on the drain side. At this time, the amount of ions implanted into the drain side is set to, for example, 5e12 to 5e14 cm −2, and an LDD (Lightly Doped Drain) structure can be formed by the N-type diffusion layer having a low impurity concentration.

Next, as shown in FIG. 5, a SiN layer (17) serving as a charge storage layer is deposited and a silicon oxide film (18) is deposited.
Are deposited on the SiN film (17) by a well-known technique such as a CVD method.

As shown in FIG. 6, a gate sidewall (19) is formed by a method such as etch back, N-type impurities are introduced by a well-known technique such as ion implantation, and a drain (20) and a source (21) are introduced. Forming an N-type diffusion layer. The width of the side wall (19) of the gate defines the width of the charge injection region. Here, the thickness of the SiN layer (17) is set to 7 nm or less in order to strengthen the electric field in the charge injection region. The lower limit of the film thickness of the SiN serving as the charge storage layer can be determined by the charge trap density, but it is preferably at least 0.5 nm. In this embodiment,
Although SiN is used as the charge storage layer, it is a film having a sufficient amount of charge traps, such as a tantalum oxide film, strontium titanate, and PZT, and has a sufficiently high relative permittivity and insulation resistance and does not deteriorate due to a thermal process in the manufacturing process Any film may be used as long as it is a film. Further, since the oxide film (18) deposited on the SiN film can prevent outward diffusion of the charges stored in the SiN film, the data retention characteristic of the cell can be improved. The ion implantation amount for forming the N-type diffusion layers of the drain (20) and the source (21) is, for example, 5e14 to 1e16 cm-2, and the concentration of N is relatively high.
A mold diffusion layer is formed. Here, control gate (1
The distance between 3) and the end of the source diffusion layer (21) is determined so that an electric field that allows the generated hot carriers to reach the charge storage layer sufficiently during the charge injection operation. For example, the distance is 25 nm or less. This distance can be adjusted by the width of the gate sidewall and the thermal diffusion process after ion implantation of the source. It can also be adjusted by the dielectric constant of the film used for the gate sidewall (19). After this, FIG.
As shown in FIG. 2, an interlayer insulating film (22) is formed according to a usual MOS integrated circuit manufacturing method, a part of the interlayer insulating film on the source / drain regions is opened, and then a contact hole (23) is formed. After the barrier layer (24) is formed in the contact hole by a well-known technique, the W plug (25) is embedded and the A1 electrode (26) is formed to complete the memory cell.

FIG. 7 shows a circuit block diagram of the non-volatile semiconductor device of the present invention in FIG. 8 showing an arrangement method in the case of providing an injection region on the source side as in this embodiment. FIG. 15 shows an arrangement method in the case where an injection region is provided on the drain side, writing is performed by channel hot electrons, and erasing is performed by a drain avalanche hot hole. In addition, although the present embodiment has described the case of forming on a P-type substrate, this structure shows that when a memory cell is formed on a P-well formed on an N-type semiconductor substrate, it is formed on an SOI (Silicon on Insulator) substrate. The same applies when formed in the P-type region. In this embodiment, it is possible to provide a charge injection region on the source side,
It is possible to provide a charge injection region on the drain side as in the case of this embodiment. Although the present embodiment shows the structure in which the ONO insulating film is used for the gate side wall portion and under the gate side wall, as shown in FIG. 17, the ONO insulating film is used as the gate insulating film of the cell transistor to form the gate side wall. It is also possible.

Next, the operation of this embodiment will be described with reference to FIGS. 12 (a) and 12 (b). Writing when the charge injection region is provided on the source side is performed as follows.
When a positive potential is applied to the source and the drain is opened and the electric field is 7 MV / cm or more in the substrate region at the end of the source diffusion layer, avalanche hot carriers are significantly generated.
At this time, as shown in FIG. 14, when the gate potential is moved in a positive direction from a certain potential (Va), the charges injected into the charge injection region become hot electron rich, and electrons are stored in the charge storage layer. . (N. Matsukawa et a
l. 1995 IRPS) In this state, the channel under the charge storage layer on the source side is turned off in the read operation, so that even if 5V is applied to the gate, 1V to the drain, and 0V to the source, almost no current flows. Therefore, it can be determined that the data has been written. There are two methods of erasing: using avalanche hot carriers and using an FN tunnel. When an avalanche hot hole is used, if the gate potential is moved in the negative direction from a certain potential, as in writing, the charge injected into the charge injection region becomes hot hole rich and the charge storage layer has holes. Will be accumulated. In this state, since the channel under the charge storage layer is turned on, it can be determined that the data has been erased because a current flows during the read operation. When the FN tunnel is used, the gate potential at the time of injecting avalanche hot holes is further moved in the negative direction and made stronger than the electric field between the gate and the source, so that electrons in the storage layer can be extracted. Figure 1 shows the gate potential of non-selected cells during programming and erasing.
The disturb phenomenon does not occur under the condition (Va) such that neither electrons nor holes are injected in No. 4.

Next, when the charge storage layer is provided on the drain side, writing and erasing can be performed in the same manner as when the charge storage layer is provided on the source side, but when the source is grounded without being opened. Since a large amount of current flows in the channel of the cell, the injection efficiency of hot electrons and hot holes can be improved. (S. Yamada et al. 1991I
During EDM writing, there is also a method in which a current is caused to flow between the source and drain to generate channel hot electrons on the drain side and inject electrons.

Next, a non-volatile semiconductor memory cell according to a second embodiment of the present invention will be described with reference to FIGS. 9 to 11. The process from the patterning of the gate to the deposition of SiN (17) to be the charge storage layer is the same as the process of the first embodiment. In FIG. 10, after the SiN film (17) is deposited, the silicon oxide film (27) is deposited and the polysilicon (2
After 8) is deposited to a thickness of 20 to 200 nm, N-type impurities such as arsenic and phosphorus are adjusted to a concentration of 2 to 4e20 cm-3, for example. Doping to metallize. Here, the film thickness of the oxide film (27) on the SiN film (17) is
The film thickness is set to 2.5 nm or more in order to prevent outward diffusion of charges stored in the SiN film or injection of holes from the polysilicon sidewall (29). In FIG. 11, a polysilicon sidewall (29) is formed by a method such as etch back, N-type impurities are introduced by a known technique such as ion implantation, and N-type diffusion of the drain (20) and the source (21) is performed. Form the layers. The ion implantation amount at this time is, for example, 5e14 to 1e16 cm-2 to form an N-type diffusion layer having a relatively high concentration. Thereafter, in FIG. 9, the memory cell is completed through the same steps as those in the first embodiment.

Next, the operation of this embodiment will be described with reference to FIG. Writing when the charge injection region is provided on the source side is performed in the same manner as in the first embodiment. A positive potential is applied to the source and the drain is opened. Here, when a potential is applied to the gate, the polysilicon electrode on the side wall is
Since the gate, the source, and the substrate are capacitively coupled, the potential of the sidewall polysilicon electrode depends on the capacitive coupling ratio with each electrode. When the cell of this embodiment is used as a cell array, for example, if the height of the gate is 200 nm, the width of the polysilicon side wall is 100 nm, the gate width of the cell transistor is 0.4 μm, and the pitch in the word line direction is 0.8 μm, the side wall is obtained. The capacitance between polysilicon and gate is about 8% of the total capacitance.
When the substrate potential is grounded, the sidewall polysilicon potential is about 80% of the gate potential. Thus, the potential of the sidewall polysilicon electrode can be controlled by the gate potential. When the gate potential is applied so as to bring the potential of the sidewall polysilicon in a positive direction from a certain potential, the charges injected into the charge injection region among the hot carriers generated at the edge of the source diffusion layer become hot electron rich. Electrons are stored in the charge storage layer. In this case, during the read operation, the channel under the side wall may be turned on by the rise of the side wall potential, but the flowing current is extremely smaller than that in the case where no writing is performed, and therefore it can be determined that the channel has been written. Similarly to writing, erasing can be performed by controlling the sidewall polysilicon potential with the gate potential. Even when the charge storage layer is provided on the drain side, writing / erasing can be performed as in the first embodiment.

Similar to the first embodiment, the structure of this embodiment is also formed in the P-type region on the SOI (Silicon on Insulator) substrate when the memory cell is formed on the P-well formed on the N-type semiconductor substrate. It can also be applied in cases. The charge injection region can be provided on either the source side or the drain side. Further, in this embodiment, the structure in which the ONO insulating film is used for the gate side wall portion and under the gate side wall is shown. However, in the structure of the cell transistor shown in FIG. 17, the gate side wall (19) is made of polysilicon, for example, arsenic. ,
It is also possible to use an ONO insulating film as a gate insulating film of a cell transistor by adopting a structure in which N-type impurities such as phosphorus are doped and metallized.

[0019]

According to the present invention, since the cell is formed by the series connection of the transistor and the offset region under the charge injection layer, the selection transistor is not required unlike the MONOS cell which injects the charge in the channel region. Further, since a shallow diffusion layer can be formed in the source / drain of the cell transistor, the gate length of the cell transistor can be miniaturized. As a method for injecting charges into the insulating film, hot carriers or avalanche hot carriers are generated by a band-to-band tunnel at a drain or a source that serves as an injection electrode, and the energy is comparatively lower than that of hot carriers generated by an FN current. Therefore, the damage to the insulating film is reduced, and the reliability of the cell can be improved. Further, with respect to the disturb for the non-selected cells on the same bit line, it is possible to prevent almost no disturb by adjusting the gate potential of the non-selected cells.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor memory device of the first embodiment of the present invention.

FIG. 7 is a memory cell array of a semiconductor memory device using the memory cell of the present invention.

FIG. 8 is a circuit configuration diagram of a semiconductor memory device of the present invention.

FIG. 9 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor memory device of the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 12 is a diagram showing an operating method of the semiconductor memory device of the present invention.

FIG. 13 is a diagram showing an operating method of the semiconductor memory device of the present invention.

FIG. 14 is a diagram showing characteristics of the memory cell of the present invention.

FIG. 15 is still another configuration diagram of the memorial array of the semiconductor memory device using the memory cell of the present invention.

FIG. 16 is a cross-sectional view of a conventional semiconductor memory device.

FIG. 17 is still another configuration diagram of the memorial array of the semiconductor memory device using the memory cell of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate or well (P-type impurity region), 2 ... Drain (dense N-type impurity region), 3 ... Source (dense N-type impurity region), 4 ... Silicon oxide film, 5 ... SiN film, 6 ... Silicon oxide film , 7 ... Control gate, 9 ... Oxide film formed after laminated gate processing, 10 ... Element isolation region, 11 ... Gate insulating film, 12 ... Polysilicon layer to be a gate electrode, 13 ... Gate electrode, 14 ... Silicon oxide film, Reference numeral 15 ... Photoresist, 16 ... N-type diffusion layer, 17 ... SiN layer serving as charge storage layer, 18 ... Silicon oxide film, 19 ... Gate sidewall, 20 ... Drain N-type diffusion layer, 21 ... Source N-type diffusion layer, 22 ... interlayer insulating film, 23 ... contact hole, 24 ... barrier layer, 25 ... W plug, 26 ... A1 electrode, 27 ... silicon oxide film, 28 ... polysilicon layer, 29 ... Li silicon side wall,

Claims (17)

[Claims] 1. A second conductivity type first and second diffusion layers formed in a first conductivity type semiconductor substrate, and a part on a channel region existing between the first and second diffusion layers. A channel region formed between a first gate electrode formed on a part of the first diffusion layer via a first insulating film and existing between the first gate electrode and the second diffusion layer. A semiconductor having a second insulating film having a structure of at least two layers having different film types and having a film thickness of 30 nm or less, and a part of the second insulating film serves as a charge storage layer. apparatus. 2. The semiconductor device according to claim 1, wherein the second insulating film serves as a sidewall of the first gate electrode. 3. The second insulating film according to claim 1, wherein the second insulating film has a two-layer structure of a silicon oxide film having a thickness of 2 nm to 10 nm and a silicon nitride film having a thickness of 0.5 nm to 7 nm from the semiconductor substrate. A semiconductor device characterized by the above. 4. The semiconductor device according to claim 3, wherein the second insulating film also serves as the first insulating film which is a gate insulating film. 5. The semiconductor device according to claim 1, wherein a silicon oxide film is present on the second insulating film at least 1 nm or more. 6. The semiconductor device according to claim 1, wherein the structure of the second insulating film is a two-layer structure of a silicon oxide film and a tantalum oxide film on the semiconductor substrate. 7. The semiconductor according to claim 1, wherein the structure of the second insulating film is a two-layer structure of a silicon oxide film, strontium titanate, or barium strontium titanate from above the semiconductor substrate. apparatus. 8. The semiconductor device according to claim 1, wherein the first diffusion layer has a double diffusion layer structure having a region having a low impurity concentration outside and a region having a high impurity concentration inside. 9. A second conductivity type first and second diffusion layers formed in a first conductivity type semiconductor substrate, and a part on a channel region existing between the first and second diffusion layers. A channel region that is formed of a first gate electrode formed on a part of the first diffusion layer via a first insulating film, and exists between the first gate electrode and the second diffusion layer. It has a floating gate that is capacitively coupled to the gate electrode, and has at least a three-layer structure between the floating gate and the channel region and has a film thickness of 30 nm.
A semiconductor device having the following second insulating film, wherein a part of this second insulating film serves as a charge storage layer. 10. A semiconductor device according to claim 9, wherein the first insulating film, which is a gate insulating film, has at least a three-layer structure and also serves as a second insulating film. 11. The structure of the second insulating film according to claim 9, wherein a silicon oxide film having a thickness of 2 nm or more and 10 nm or less, a silicon nitride film having a thickness of 0.5 nm or more and 7 nm or less from the semiconductor substrate, A semiconductor device having a three-layer structure of a silicon oxide film. 12. The semiconductor device according to claim 9, wherein the second insulating film serves as an insulating film between the first gate electrode and the floating gate. 13. The semiconductor device according to claim 9, wherein the second insulating film has a three-layer structure of a silicon oxide film, a tantalum oxide film, and a silicon oxide film on the semiconductor substrate. 14. The structure according to claim 9, wherein the second insulating film has a three-layer structure of a silicon oxide film, strontium titanate or barium strontium titanate, and a silicon oxide film on the semiconductor substrate. Semiconductor device. 15. The first diffusion layer according to claim 1, wherein the first diffusion layer is in an open state, a potential is applied to the second diffusion layer to generate avalanche hot carriers, and a first potential is applied to the first gate electrode. A semiconductor device, wherein electrons or holes are selectively injected into the charge storage layer of the second insulating film. 16. The method according to claim 1 or 9, wherein a potential is applied to the second diffusion layer to generate hot carriers in a depletion layer region at an end of the second diffusion layer, and the potential is applied to the gate electrode. A semiconductor device, wherein electrons or holes are selectively injected into the charge storage layer of the second insulating film. 17. The second diffusion layer according to claim 1 or 9, when a potential is applied to the second diffusion layer to generate hot carriers in a depletion layer region at an end of the second diffusion layer. A semiconductor device, wherein a potential applied to a gate electrode of a non-selected cell sharing the applied potential is set to a condition that electrons and holes are not injected at the end of the second diffusion layer.