CN102446918A - Structure for preventing etch stop layer from cracking and method for forming structure - Google Patents
Structure for preventing etch stop layer from cracking and method for forming structure Download PDFInfo
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- CN102446918A CN102446918A CN2011102352586A CN201110235258A CN102446918A CN 102446918 A CN102446918 A CN 102446918A CN 2011102352586 A CN2011102352586 A CN 2011102352586A CN 201110235258 A CN201110235258 A CN 201110235258A CN 102446918 A CN102446918 A CN 102446918A
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Abstract
The invention provides a structure for preventing an etch stop layer from cracking. The structure comprises a semiconductor substrate, a groove, a silicon oxide buffer layer and a silicon nitride contact etch stop layer, wherein the semiconductor substrate is provided with a grid, and a side wall is coated on the side wall of the grid and partial semiconductor substrate close to the grid; the groove is formed through an STI (Shallow Trench Isolation) process and arranged in the semiconductor substrate, and a filler is arranged in the groove; the silicon oxide buffer layer is covered on the semiconductor substrate, the side wall and the grid; and the silicon nitride contact etch stop layer is covered on the silicon oxide buffer layer. In the structure provided by the invention, the characteristics that silicon oxide, which is prepared by SACVD (sub-atmospheric chemical vapor deposition), has a certain tension stress and corresponding silicon nitride is softer are utilized, and a layer of silicon oxide prepared by the SACVD is added between a high-tension-stress contact stop layer and a semiconductor device to serve as a buffer layer, thereby effectively reducing the cracking possibility in the etch stop layer due to the existence of local high tension stress.
Description
Technical field
The present invention relates to the structure of etching barrier layer in a kind of field of semiconductor manufacture, relate in particular to and a kind ofly can prevent the structure of etching barrier layer cracking and the method that forms this structure.
Background technology
Along with the integrated circuit characteristic line breadth narrows down to below the 90nm, people have introduced the electromobility that heavily stressed silicon nitride improves charge carrier gradually.
Silicon nitride is because high, good photoelectric properties of its chemical stability and the strong Na that stops
+Advantages such as diffusion, and be widely used among semiconductor device and the integrated circuit.Through Metal-oxide-semicondutor (N-Mental-Oxide-Semiconductor, NMOS) above deposit high tensile stress silicon nitride as via etch stop the layer (Contact Etch Stop Layer, CESL).
In Chinese patent CN102044492A, disclose a kind of method that is used for producing the semiconductor devices, comprised the following steps: to provide a substrate; On said substrate, form grid oxic horizon and gate electrode; On the sidewall of said grid oxic horizon and said gate electrode, form the clearance wall insulating barrier, the dorsal part at said substrate forms first insulating barrier simultaneously; On the sidewall of said clearance wall insulating barrier, form clearance wall, the dorsal part at said first insulating barrier forms second insulating barrier simultaneously; On said substrate, form source electrode and drain electrode; On said clearance wall, form etching stopping layer; On said etching stopping layer, form heavily stressed induced layer; The said heavily stressed induced layer of etching is so that with its thinning; Utilize dry etching to remove the heavily stressed induced layer and the etching stopping layer of said thinning.
In Chinese patent CN102044437A, disclose a kind of method that is used for producing the semiconductor devices, comprised the following steps: to provide a substrate; On said substrate, form grid oxic horizon and gate electrode; On the sidewall of said grid oxic horizon and said gate electrode, form the clearance wall insulating barrier, the dorsal part at said substrate forms first insulating barrier simultaneously; On the sidewall of said clearance wall insulating barrier, form clearance wall, the dorsal part at said first insulating barrier forms second insulating barrier simultaneously; On said substrate, form source electrode and drain electrode; On said clearance wall, form etching stopping layer; On said etching stopping layer, form heavily stressed induced layer, said heavily stressed induced layer is 40: 1 ~ 60: 1 with respect to the dry etching selection rate of said etching stopping layer; The said heavily stressed induced layer of etching is so that with its thinning; The heavily stressed induced layer of the said thinning of etching and etching stopping layer are so that remove it.
In Chinese patent CN102117773A, disclosed a kind of applied stress memory technique technology and made the method for semiconductor device, method comprises: on the Semiconductor substrate with PMOS zone and nmos area territory, form gate oxide and grid; On said gate oxide and grid, deposit side wall oxide layer and side wall nitride silicon layer successively, and the side wall silicon nitride layer is carried out the directed etching perpendicular to the semiconductor substrate surface direction; On the PMOS zone, form photoresist layer, N is carried out in the nmos area territory
+Ion implantation technology; With said photoresist layer is mask, removes the side wall oxide layer on the nmos area territory; Remove the photoresist layer on the PMOS zone; On the nmos area territory, form photoresist layer, P is carried out in the PMOS zone
+Ion implantation technology; Remove the photoresist layer in nmos area territory; On PMOS zone and nmos area territory, form buffer oxide layer and heavily stressed silicon nitride layer; Remove the heavily stressed silicon nitride layer on the PMOS zone; Carry out spike annealing technology; Remove the heavily stressed silicon nitride layer on the nmos area territory.
In preparation method who mentions in the above and the common manufacturing approach, owing to the production technology reason can make silicon nitride film inside have higher tension stress.And silicon nitride film layer meeting in uneven thickness makes that local pulling force is bigger, if control badly, in zone such as the gate bottom that some stress are concentrated, the cracking of silicon nitride film may occur.Thereby produce discontinuous film, finally can not reach the effect that improves carrier mobility.
Summary of the invention
The present invention provides a kind of structure of preventing the etching barrier layer cracking; Utilization has certain tension stress characteristic softer with corresponding silicon nitride by the silicon dioxide of SACVD preparation; The certain thickness SACVD of deposit one deck (Sub-atmospheric Chemical Vapor Deposition in advance; Inferior atmospheric pressure chemical vapor deposition) silicon dioxide of processing procedure is as resilient coating, thereby reduced the possibility that etching barrier layer ftractures owing to higher tension stress to a certain extent.
For realizing above-mentioned purpose, the present invention provides a kind of structure of preventing the etching barrier layer cracking, comprising:
One is provided with the semiconductor-based end of grid, is coated with side wall in the part semiconductor substrate of said gate lateral wall and adjacent gate;
One groove that formed by STI technology was arranged in this semiconductor-based end, was provided with filler in the said groove;
One silicon dioxide resilient coating is covered on the semiconductor-based end, side wall and the grid; And
One deck silicon nitride via etch barrier layer is covered on the silicon dioxide resilient coating.
In above-mentioned structure, the thickness of said silicon dioxide resilient coating is between 30 ~ 300A.
Another one purpose of the present invention is to provide the method that forms above-mentioned prevention etching barrier layer cracking structure, may further comprise the steps:
In the active area that shallow trench was separated out that STI technology forms, carry out CMOS technology; Thereby on semiconductor substrate, form groove and grid; Fill silicon dioxide in the said groove, saidly in the part semiconductor substrate of gate lateral wall and adjacent gate, be coated with side wall;
Jet deposition one silicon dioxide resilient coating on the said semiconductor-based end, side wall and grid, deposition one silicon nitride via etch barrier layer on said silicon dioxide resilient coating.
In the above-mentioned step that provides, wherein the temperature of silicon dioxide buffer layer deposition is between 300 ~ 500 ℃.
In the above-mentioned step that provides, wherein the pressure of silicon dioxide buffer layer deposition is between 100 ~ 700 torr.
In the above-mentioned step that provides, wherein through Semiconductor substrate being sprayed the deposition that tetraethoxysilance and ozone are realized the silicon dioxide resilient coating.
In the above-mentioned step that provides, wherein the distance of nozzle material outlet between the semiconductor-based end is at 0.1 ~ 0.5 inch.
In the above-mentioned step that provides, wherein the emitted dose of tetraethoxysilane is controlled between 1000 ~ 3000 milligrams/minute.
In the above-mentioned step that provides, wherein the injection flow of ozone is controlled between 10000 ~ 30000 mark condition ml/min.
In the structure of prevention etching barrier layer cracking provided by the invention; Utilization has certain tension stress characteristic softer with corresponding silicon nitride by the silicon dioxide of SACVD preparation; The silicon dioxide that between high tensile stress etching barrier layer and semiconductor device, increases one deck SACVD processing procedure effectively reduces the possibility that has local high tensile stress in the etching barrier layer and ftracture as resilient coating.
Description of drawings
Fig. 1 is a kind of structural representation that prevents the etching barrier layer cracking provided by the invention.
Embodiment
The structure of prevention etching barrier layer cracking provided by the invention comprises that one is provided with the semiconductor-based end of grid, is coated with side wall in the part semiconductor substrate of said gate lateral wall and adjacent gate; The groove that is formed by STI technology was arranged in this semiconductor-based end, was provided with filler in the said groove; One silicon dioxide resilient coating is covered on the semiconductor-based end, side wall and the grid; And one deck silicon nitride via etch barrier layer is covered on the silicon dioxide resilient coating.
Utilization is by SACVD (Sub-atmospheric Chemical Vapor Deposition; Inferior atmospheric pressure chemical vapor deposition) silicon dioxide of preparation has certain tension stress and the relative softer characteristic of silicon nitride; Before deposit high tensile stress etch stop layer; The silicon dioxide of the certain thickness SACVD processing procedure of deposit one deck is as resilient coating in advance, thereby reduced the possibility that etch stop layer ftractures owing to higher tension stress to a certain extent.
SACVD imports to two or more gaseous state raw material in the reaction chamber, and chemical reaction takes place raw material each other then, thereby forms a kind of new material, and the new material of formation deposits on the surface of wafer.Though the SACVD processing procedure is simple, the actual reaction that takes place is extremely complicated in reaction chamber, and receives the restriction of many conditions.The flow, gas that for example reacts intracavity gas through the path of wafer, the chemical analysis of gas, a kind of gas with respect to the ratio of another kind of gas, in the reaction chamber pressure, wafer temperature, reaction the intermediate products role and whether need the outer external energy source of other reative cell to quicken or bring out conceivable reaction etc.
As shown in Figure 1, in prevention etching barrier layer cracking structure provided by the invention, the silicon dioxide resilient coating 4 of first deposit one deck SACVD processing procedure has groove 1 on the semiconductor substrate 3 on the semiconductor substrate that forms grid 23.The silicon nitride via etch barrier layer 5 of deposit high tensile stress above that more afterwards, form prevention etching barrier layer cracking structure after, again it is carried out in the follow-up formation metal interconnection structure operation.
Silicon dioxide resilient coating in the SACVD processing procedure is by TEOS (Tetraethyl Orthosilicate, tetraethoxysilane or tetraethoxysilane, molecular formula: Si (OC
2H
5)
4) and ozone (Ozone, molecular formula: O
3) carrying out hybrid reaction, the silica deposit of generation must be gone up deposit silicon nitride via etch barrier layer at the silicon dioxide resilient coating afterwards again on the surface at the semiconductor-based end.SACVD TEOS/ozone can obtain perfect ladder and cover and the little film of stress under low temperature environment, make SiO
2Can be utilized in widely on MEMS (Micro Electro Mechanical Systems, the microelectromechanical systems) processing procedure.
In the face of doing, the present invention is described in detail down, so that better understand the invention, but following description does not limit the scope of the invention.
Embodiment 1
The semiconductor substrate that forms grid and side wall is put into cvd reactive chamber, in reative cell, feed ultra-high purity (99.99%) TEOS steam and ozone, remain in the reative cell under 400 ℃, the pressure environment of 500 torr.The TEOS of ultra-high purity directly through 90 ℃ heating tube, directly can avoid TEOS liquefaction through heating tube then via evaporator evaporation.The TEOS steam is the O of 30000 mark condition ml/min (sccm, Standard cubic centimeter per minute) with the amount and the flow of 3000 milligrams/minute (mgm, milligram per minute)
3, before getting into nozzle, just mixing earlier, the gaseous mixture fluid of formation sprays to substrate through nozzle, and slowly deposit forms the fine and close continuously resilient coating of one deck on semiconductor substrate, and nozzle remains on 0.4 inch to the distance at the semiconductor-based end.Deposit silicon nitride via etch barrier layer on silicon dioxide layer, back has promptly formed the structure that the prevention etching barrier layer ftractures.Ozone in the reaction can produce through the pure oxygen discharge, can have a certain amount of oxygen in the ozone gas of generation.
Embodiment 2
The semiconductor substrate that forms grid and side wall is put into cvd reactive chamber, in reative cell, feed ultra-high purity (99.99%) TEOS steam and ozone, remain in the reative cell under 300 ℃, the pressure environment of 600 torr.The TEOS of ultra-high purity directly through 90 ℃ heating tube, directly can avoid TEOS liquefaction through heating tube then via evaporator evaporation.The TEOS steam is the O of 20000 mark condition ml/min (sccm, Standard cubic centimeter per minute) with the amount and the flow of 2000 milligrams/minute (mgm, milligram per minute)
3, before getting into nozzle, just mixing earlier, the gaseous mixture fluid of formation sprays to substrate through nozzle, and slowly deposit forms the fine and close continuously resilient coating of one deck on semiconductor substrate, and nozzle remains on 0.35 inch to the distance at the semiconductor-based end.Deposit silicon nitride via etch barrier layer on silicon dioxide layer, back has promptly formed the structure that the prevention etching barrier layer ftractures.
Embodiment 3
The semiconductor substrate that forms grid and side wall is put into cvd reactive chamber, in reative cell, feed ultra-high purity (99.99%) TEOS steam and ozone, remain in the reative cell under 300 ℃, the pressure environment of 200 torr.The TEOS of ultra-high purity directly through 90 ℃ heating tube, directly can avoid TEOS liquefaction through heating tube then via evaporator evaporation.The TEOS steam is the O of 20000 mark condition ml/min (sccm, Standard cubic centimeter per minute) with the amount and the flow of 1000 milligrams/minute (mgm, milligram per minute)
3, before getting into nozzle, just mixing earlier, the gaseous mixture fluid of formation sprays to substrate through nozzle, and slowly deposit forms the fine and close continuously resilient coating of one deck on semiconductor substrate, and nozzle remains on 0.1 inch to the distance at the semiconductor-based end.Deposit silicon nitride via etch barrier layer on silicon dioxide layer, back has promptly formed the structure that the prevention etching barrier layer ftractures.
The structure of prevention etching barrier layer cracking provided by the invention is before deposit high tensile stress etching barrier layer; The silicon dioxide of the certain thickness SACVD processing procedure of deposit one deck is as resilient coating in advance, thereby reduced the possibility that etching barrier layer ftractures owing to higher tension stress to a certain extent.The prevention etching barrier layer cracking structure that forms can directly be used for follow-up formation metal interconnection structure operation.Whole implementing process is simple, can be easy to integrate with conventional interconnect.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (9)
1. a structure of preventing the etching barrier layer cracking is characterized in that, comprising:
One is provided with the semiconductor-based end of grid, is coated with side wall in the part semiconductor substrate of said gate lateral wall and adjacent gate;
One groove that formed by STI technology was arranged in this semiconductor-based end, was provided with filler in the said groove;
One silicon dioxide resilient coating is covered on the semiconductor-based end, side wall and the grid; And
One deck silicon nitride via etch barrier layer is covered on the silicon dioxide resilient coating.
2. structure according to claim 1 is characterized in that the thickness of said silicon dioxide resilient coating is between 30 ~ 300A.
3. a method that forms the said prevention etching barrier layer cracking of claim 1 structure is characterized in that, may further comprise the steps:
In the active area that shallow trench was separated out that STI technology forms, carry out CMOS technology; Thereby on semiconductor substrate, form groove and grid; Fill silicon dioxide in the said groove, saidly in the part semiconductor substrate of gate lateral wall and adjacent gate, be coated with side wall;
Jet deposition one silicon dioxide resilient coating on the said semiconductor-based end, side wall and grid, deposition one silicon nitride via etch barrier layer on said silicon dioxide resilient coating.
4. method according to claim 3 is characterized in that the temperature of silicon dioxide buffer layer deposition is between 300 ~ 500 ℃.
5. method according to claim 3 is characterized in that the pressure of silicon dioxide buffer layer deposition is between 100 ~ 700 torr.
6. method according to claim 3 is characterized in that, through Semiconductor substrate being sprayed the deposition that tetraethoxysilance and ozone are realized the silicon dioxide resilient coating.
7. method according to claim 6 is characterized in that, the distance of nozzle material outlet between the semiconductor-based end is at 0.1 ~ 0.5 inch.
8. method according to claim 6 is characterized in that the emitted dose of tetraethoxysilane is controlled between 1000 ~ 3000 milligrams/minute.
9. method according to claim 6 is characterized in that, the injection flow of ozone is controlled between 10000 ~ 30000 mark condition ml/min.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102352586A CN102446918A (en) | 2011-08-17 | 2011-08-17 | Structure for preventing etch stop layer from cracking and method for forming structure |
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|---|---|---|---|
| CN2011102352586A CN102446918A (en) | 2011-08-17 | 2011-08-17 | Structure for preventing etch stop layer from cracking and method for forming structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449362A (en) * | 2016-10-10 | 2017-02-22 | 上海华力微电子有限公司 | Method for improving stress memory technology effect |
| CN114122133A (en) * | 2020-09-01 | 2022-03-01 | 无锡华润上华科技有限公司 | Laterally diffused metal oxide semiconductor device, preparation method thereof and electronic device |
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| CN101320711A (en) * | 2007-06-05 | 2008-12-10 | 联华电子股份有限公司 | Metal-oxide-semiconductor transistor and preparation thereof |
| CN102054776A (en) * | 2009-10-28 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing stress memorization effect semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449362A (en) * | 2016-10-10 | 2017-02-22 | 上海华力微电子有限公司 | Method for improving stress memory technology effect |
| CN106449362B (en) * | 2016-10-10 | 2019-02-01 | 上海华力微电子有限公司 | A method of improving stress memory technological effect |
| CN114122133A (en) * | 2020-09-01 | 2022-03-01 | 无锡华润上华科技有限公司 | Laterally diffused metal oxide semiconductor device, preparation method thereof and electronic device |
| WO2022048163A1 (en) * | 2020-09-01 | 2022-03-10 | 无锡华润上华科技有限公司 | Laterally-diffused metal-oxide semiconductor apparatus and preparation method therefor, and electronic device |
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Application publication date: 20120509 |