CN114122133A - Laterally diffused metal oxide semiconductor device, preparation method thereof and electronic device - Google Patents

Laterally diffused metal oxide semiconductor device, preparation method thereof and electronic device Download PDF

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Publication number
CN114122133A
CN114122133A CN202010902338.1A CN202010902338A CN114122133A CN 114122133 A CN114122133 A CN 114122133A CN 202010902338 A CN202010902338 A CN 202010902338A CN 114122133 A CN114122133 A CN 114122133A
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layer
contact hole
metal silicide
barrier layer
region
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Inventor
金宏峰
曹瑞彬
朱文明
张文文
林峰
金华俊
李春旭
陈淑娴
黄宇
杨斌
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202010902338.1A priority Critical patent/CN114122133A/en
Priority to PCT/CN2021/088838 priority patent/WO2022048163A1/en
Publication of CN114122133A publication Critical patent/CN114122133A/en
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Abstract

The invention relates to a lateral diffusion metal oxide semiconductor device and a preparation method thereof, wherein the method comprises the steps of obtaining a substrate which is provided with a drift region, a grid structure, a source region and a drain region; forming a metal silicide barrier layer on the substrate; forming a hole etching barrier layer film comprising a second oxide layer film and a second etching barrier layer film on the substrate; performing an etching process to form a first contact hole on the metal silicide barrier layer, wherein the bottom of the first contact hole stays on the surface of the metal silicide barrier layer; forming a second contact hole on the lead-out area, wherein the bottom of the second contact hole stays on the surface of the lead-out area; wherein forming the second contact hole over the extraction region includes at least one of forming a drain contact hole over the drain region, forming a source contact hole over the source region, and forming a gate contact hole over the gate structure not covered by the metal silicide blocking layer. The influence of fluctuation of the process on the suspension height position of the hole-type metal field plate is avoided.

Description

Laterally diffused metal oxide semiconductor device, preparation method thereof and electronic device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a lateral diffusion metal oxide semiconductor device and a method for manufacturing the same.
Background
For a medium-voltage (16-80V) NLDMOS (N-lateral-diffused metal-oxide semiconductor) device, a metal field plate (metal plate), a floating source contact (floating source contact), a gate field plate (gate plate), or the like is usually used to further Reduce a surface electric field (resurf, Reduce surface field) and improve BVoff under the same Rsp capability. However, Metal plate and gate plate need to increase the number of non-lithographic layers in the manufacturing process, which increases the manufacturing cost of the LDMOS.
A typical fabrication process of a lithographic mask is to form a suspended metal field plate in a metal silicide blocking layer above an LDMOS drift region to further reduce a surface electric field, but due to the influence of the thickness and etching rate of an interlayer dielectric layer on the metal silicide blocking layer, the suspended metal field plate has a hovering position at the center of a wafer different from the hovering position at the edge of the wafer, which is greatly influenced by a process, and the suspended position of the suspended metal field plate may be below the metal silicide blocking layer, thereby generating a short circuit between a source electrode and a gate electrode.
Disclosure of Invention
Therefore, it is necessary to provide a lateral diffusion metal oxide semiconductor device and a method for fabricating the same, which is directed to the problem of unstable floating position of a floating metal field plate in the conventional technology.
A laterally diffused metal oxide semiconductor device, comprising:
a substrate;
a drift region in the substrate;
the gate structure is positioned on the substrate and covers part of the surface of the drift region;
a drain region in the drift region on one side of the gate structure;
the source region is positioned in the substrate at the other side of the grid structure;
the metal silicide blocking layer covers the surface, between the gate structure and the drain region, of the drift region and extends to part of the surface of the gate structure;
the hole etching barrier layer comprises a second oxide layer and a second etching barrier layer positioned on the surface of the second oxide layer, and the second oxide layer and the second etching barrier layer are positioned on the grid structure, the metal silicide barrier layer, the source region and the drain region;
the first contact hole is formed in the metal silicide barrier layer and penetrates through the hole etching barrier layer above the metal silicide barrier layer, and the bottom of the first contact hole stays on the surface of the metal silicide barrier layer;
the second contact hole is formed in the lead-out area, penetrates through the hole etching barrier layer above the lead-out area, and the bottom of the second contact hole stays on the surface of the lead-out area;
the lead-out region at least comprises one of a drain region, a source region and the grid structure which is not covered by the metal silicide barrier layer, and the second contact hole corresponds to the lead-out region and at least comprises one of a drain contact hole arranged on the drain region, a source contact hole arranged on the source region and a grid contact hole arranged on the grid structure which is not covered by the metal silicide barrier layer.
In one embodiment, the second etching barrier layer comprises a second silicon oxynitride layer and a second silicon nitride layer from bottom to top; or the second etching barrier layer comprises a second silicon oxynitride layer; or the second etch stop layer comprises a second silicon nitride layer.
In one embodiment, the metal silicide blocking layer comprises a first oxidation layer and a first silicon nitride layer which are sequentially stacked from bottom to top; or the metal silicide barrier layer comprises a first oxidation layer, a first silicon nitride layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top; or the metal silicide barrier layer comprises a first oxidation layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top.
In one embodiment, the width of the first contact hole is greater than the width of the second contact hole.
In one embodiment, the ldmos device further includes:
and the metal silicide is positioned on the surface of the gate structure which is not covered by the metal silicide barrier layer, the surface of the source region and the surface of the drain region.
In one embodiment, the semiconductor device further comprises an interlayer dielectric layer located on the hole etching barrier layer, the first contact hole penetrates through the interlayer dielectric layer above the metal silicide barrier layer, and the second contact hole penetrates through the interlayer dielectric layer above the leading-out region.
The lateral diffusion metal oxide semiconductor device comprises a metal silicide blocking layer, a metal silicide blocking layer and a metal silicide layer, wherein the metal silicide blocking layer covers the surface of the drift region, which is positioned between the grid structure and the drain region, and extends to part of the surface of the grid structure; and the hole etching barrier layer comprises a second oxidation layer and a second etching barrier layer positioned on the surface of the second oxidation layer, the second oxidation layer and the second etching barrier layer are positioned on the grid structure, the metal silicide barrier layer, the source region and the drain region, and when a first contact hole is formed on the metal silicide barrier layer and a second contact hole is formed in the lead-out region through the hole etching barrier layer by the same etching process, the purpose that the bottom of the second contact hole stays on the surface of the lead-out region while the bottom of the first contact hole, namely the bottom of a filling hole of the metal field plate stays on the surface of the metal silicide barrier layer is realized, so that the hole type metal field plate with the same suspension position is obtained, and the influence of the fluctuation of the process procedure on the suspension height position of the hole type metal field plate is avoided.
A method for preparing a lateral diffusion metal oxide semiconductor device comprises the following steps:
the method comprises the steps of obtaining a substrate, wherein a drift region is formed in the substrate, a gate structure covering part of the surface of the drift region is formed on the substrate, a drain region is formed in the drift region on one side of the gate structure, and a source region is formed in the substrate on the other side of the gate structure;
forming a metal silicide blocking layer on the substrate, wherein the metal silicide blocking layer covers the surface of the drift region between the gate structure and the drain region and extends to part of the surface of the gate structure;
forming a hole etching barrier layer film on the substrate, wherein the hole etching barrier layer film comprises a second oxide layer film and a second etching barrier layer film positioned on the surface of the second oxide layer film;
performing an etching process, forming a first contact hole on the metal silicide barrier layer, wherein the bottom of the first contact hole stays on the surface of the metal silicide barrier layer; forming a second contact hole on the lead-out area, wherein the bottom of the second contact hole stays on the surface of the lead-out area;
the lead-out region at least comprises one of a drain region, a source region and the grid structure which is not covered by the metal silicide barrier layer, the second contact hole corresponds to the lead-out region, and the step of forming the second contact hole on the lead-out region at least comprises one of forming a drain contact hole on the drain region, forming a source contact hole on the source region and forming a grid contact hole on the grid structure which is not covered by the metal silicide barrier layer.
In one embodiment, the second etching barrier layer film comprises a second silicon oxynitride layer film and a second silicon nitride layer film from bottom to top; or the second etching barrier layer film comprises a second silicon oxynitride layer film; or the second etching barrier layer comprises a second silicon nitride layer film.
In one embodiment, before the performing the etching process, the method further includes: and forming an interlayer dielectric layer film on the substrate.
In one embodiment, the step of performing the etching process includes:
forming a first photoresist pattern on the substrate, wherein the first photoresist pattern exposes the interlayer dielectric layer film of a first preset area of the first contact hole and the interlayer dielectric layer film of a second preset area of the second contact hole;
performing a first etching process to remove the interlayer dielectric layer films in the first preset area and the second preset area;
performing a second etching process to remove the second etching barrier layer film in the first preset area and the second preset area;
performing a third etching process to remove the second oxide layer films in the first preset area and the second preset area;
the etching rate of the interlayer dielectric layer film etched by the first etching process is greater than that of the second etching barrier layer film etched by the second etching process, the etching rate of the second etching barrier layer film etched by the second etching process is greater than that of the second oxide layer film etched by the second etching process, and the etching rate of the second oxide layer film etched by the third etching process is greater than that of the metal silicide barrier layer etched by the third etching process.
In one embodiment, the metal silicide blocking layer comprises a first oxidation layer and a first silicon nitride layer which are sequentially stacked from bottom to top, or the metal silicide blocking layer comprises a first oxidation layer, a first silicon nitride layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top; or the metal silicide barrier layer comprises a first oxidation layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top.
In one embodiment, the width of the first contact hole is greater than the width of the second contact hole.
In one embodiment, before forming the hole etching barrier film on the substrate, the method further comprises:
and forming metal silicide on the substrate, wherein the metal silicide is positioned on the gate structure which is not covered by the metal silicide barrier layer, the surface of the source region and the surface of the drain region.
An electronic device comprising a laterally diffused metal oxide semiconductor device as in any one of the above.
The preparation method of the lateral diffusion metal oxide semiconductor device and the electronic device comprise the steps of forming a metal silicide blocking layer on the substrate, wherein the metal silicide blocking layer covers the surface, located between the grid structure and the drain region, of the drift region and extends to the surface of part of the grid structure; forming a hole etching barrier layer film on the substrate, wherein the hole etching barrier layer film comprises a second oxide layer film and a second etching barrier layer film positioned on the surface of the second oxide layer film; the barrier layer film is etched through the holes, so that when a first contact hole is formed in the metal silicide barrier layer and a second contact hole is formed in the lead-out area through the same etching process, the purpose that the bottom of the second contact hole stays on the surface of the lead-out area, the bottom of the first contact hole, namely the filling hole of the metal field plate, stays on the surface of the metal silicide barrier layer is achieved, the hole-type metal field plate with the same suspension position is obtained, and the influence of the fluctuation of the process procedure on the suspension position of the hole-type metal field plate is avoided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for fabricating a lateral diffused metal oxide semiconductor device in one embodiment;
FIG. 2 is a schematic cross-sectional view of an LDMOS device after step S104 in a method for manufacturing an LDMOS device according to an embodiment;
FIG. 3 is a schematic cross-sectional view of an LDMOS device according to an embodiment of the present invention before step S108 in the fabrication method of the LDMOS device;
FIG. 4 is a schematic cross-sectional view of an LDMOS device after step S108 in the method for manufacturing an LDMOS device according to an embodiment; fig. 4 is a schematic cross-sectional structure diagram of the ldmos device provided in the present application.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" other elements or layers, it can be directly on, adjacent to, connected to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In a traditional high-voltage device structure, polysilicon is expanded to a field plate oxide layer of a drift region to serve as a field plate by adjusting the length of the polysilicon, or a metal field plate is formed on the field plate oxide layer of the drift region, and the field plate depletes the drift region to form a depletion layer, so that the width of a lateral depletion layer is increased, and the withstand voltage (also referred to as breakdown voltage) is improved.
The suspended metal field plate is formed by forming a metal field plate filling hole on the metal oxide barrier layer while forming the active region through hole, and then filling a conductive material in the metal field plate filling hole to obtain a hole-type metal field plate, so that a photoetching plate for forming the metal field plate and corresponding process steps are saved. However, the preparation process has the following three disadvantages: first, the hovering stability of the filling hole of the metal field plate is difficult to guarantee, the influence of the process is large, certain deviation occurs in the film thickness and the etching rate between the center of the wafer and the edge of the wafer and between the flat area and the corner of the surface of the wafer, and certain fluctuation occurs in the hovering position of the filling hole in the metal oxide barrier layer. And secondly, the metal field plate filling hole cannot be formed on the side wall of the polysilicon gate, and the side wall is formed on the side wall of the polysilicon gate, so that a metal silicide barrier layer forms a slope region on the side wall, compared with a flat region, an interlayer dielectric layer film formed on the slope region is thinner (about 0.7-0.8 times of the thickness of the film in the flat region), when an active region through hole and a metal field plate filling hole are formed by etching, the metal field plate filling hole cannot realize etching stop in the slope region, namely the bottom of the metal field plate filling hole may expose the side wall at the bottom, and for a low-voltage LDMOS with a small drift region, a hole type metal field plate can not be formed in the slope region of the metal field plate filling hole on the drift region. Thirdly, in the process of etching the through hole of the active area and the filling hole of the metal field plate, the dielectric layers etched by the through hole and the filling hole are different, namely, the etching targets of the two are different, the through hole etching needs to etch through the dielectric layer and is contacted with the polysilicon gate or the active region to be used as a leading-out hole of the polysilicon gate or a leading-out hole of the active region, the metal field plate filling hole etching can not etch through the dielectric layer at the bottom of the metal silicide blocking layer, namely, the etching of the filling hole of the metal field plate needs to be suspended in the dielectric layer at the bottom of the metal silicide blocking layer, but can not contact with the silicon substrate or the polysilicon gate, and finally, the metal field plate filling hole is filled with a conductive medium to be used as a hole-type metal field plate of a lateral diffusion metal oxide semiconductor device (LDMOS), the method is used for improving the withstand voltage of the LDMOS drift region, and the metal field plate filling hole can not be over-etched and accurately hovers in a slope region while the through hole etching can not be finished in the etching process in the traditional technology.
As shown in fig. 1, fig. 2, fig. 3, and fig. 4, in one embodiment, a method for manufacturing a laterally diffused metal oxide semiconductor device is provided, including:
s102, a substrate formed with a drift region, a gate structure, a source region and a drain region is obtained.
As shown in fig. 2, a substrate 102 is obtained, a drift region 104 is formed in the substrate 102, a gate structure 106 covering a part of the surface of the drift region 104 is formed on the substrate 102, a drain region 108 is formed in the drift region 104 on one side of the gate structure 106, and an active region 110 is formed in the substrate 102 on the other side of the gate structure 108.
The substrate 102 may be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 102 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like; the substrate 102 may be a bulk material or may be a composite structure, such as silicon-on-insulator; the layer 102 may also be of other semiconductor materials, not to mention one example.
And S104, forming a metal silicide barrier layer on the substrate.
As shown in fig. 2, a metal silicide blocking layer 112 is formed on the substrate 102, and the metal silicide blocking layer 112 covers a surface of the drift region 104 between the gate structure 106 and the drain region 108 and extends to a portion of the surface of the gate structure 112.
S106, forming a hole etching barrier layer film comprising a second oxide layer film and a second etching barrier layer film on the substrate.
As shown in fig. 3, an etching stop layer film 114 is formed on the substrate 102, and includes a second oxide film 402 and a second etching stop layer film 404 on the surface of the second oxide film 402.
And S108, carrying out an etching process to form a first contact hole and a second contact hole on the substrate.
As shown in fig. 4, performing an etching process to form a first contact hole 116 on the metal silicide blocking layer 112, wherein the bottom of the first contact hole 116 stays on the surface of the metal silicide blocking layer 112; forming a second contact hole on the lead-out area, wherein the bottom of the second contact hole stays on the surface of the lead-out area; wherein the lead-out region comprises at least one of a drain region, a source region, and the gate structure not covered by the metal silicide blocking layer, the second contact hole corresponds to the lead-out region, and forming the second contact hole on the lead-out region comprises at least one of forming a drain contact hole 118 on the drain region 108, forming a source contact hole 120 on the source region 110, and forming a gate contact hole 122 on the gate structure 106 not covered by the metal silicide blocking layer 112. That is, the second contact hole at least comprises one of the drain contact hole 118, the source contact hole 120 and the gate contact hole 122, the lead-out region at least comprises the drain region 108, the source region 110 and one of the gate structures 106 not covered by the metal silicide blocking layer 112, and the lead-out region corresponds to the second contact hole, that is, when the second contact hole comprises the drain contact hole 118, the lead-out region comprises the drain region 108; when the second contact hole includes the source contact hole 120, the lead-out region includes the source region 110, and when the second contact hole includes the gate contact hole 122, the lead-out region includes the source region 110.
In one embodiment, the gate structure 106 includes a gate oxide layer 202 and a polysilicon layer 204, and a channel region is formed in the substrate 102 under the gate oxide layer 202.
In one embodiment, the substrate 102 has a first conductivity type and the drift region 104, the drain region 108, and the source region 110 have a second conductivity type, the first and second conductivity types being of opposite conductivity types.
In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type may also be N-type and the second conductivity type may be P-type.
In one embodiment, a first conductive-type body region 124 is further formed in the substrate 102, the first conductive-type body region 104 and the substrate 102 together form a channel region, the source region 110 is formed in the first conductive-type body region 124, and the doping concentration of the first conductive-type body region 124 is higher than that of the substrate 102.
In one embodiment, the sidewalls 126 are formed on the sidewalls of the gate structure 106, that is, the sidewalls 126 are formed on both the sidewalls of the gate oxide layer 202 and the sidewalls of the polysilicon layer 204, and the sidewalls 126 include a dielectric material, so as to further isolate the gate structure 106 from the structures on both sides of the gate structure 106.
In one embodiment, the metal silicide blocking layer 112 includes a first oxide layer and a first silicon nitride layer stacked in sequence from bottom to top.
In one embodiment, the metal silicide blocking layer 112 includes a first oxide layer and a first silicon oxynitride layer stacked in sequence from bottom to top.
In one embodiment, the metal silicide blocking layer 112 includes, from bottom to top, a first oxide layer 302, a first silicon nitride layer 304, and a first silicon oxynitride layer 306, which are stacked in this order.
In one embodiment, the thickness of the first oxide layer 302 ranges from 500 a to 2000 a, the thickness of the first silicon nitride layer 304 ranges from 100 a to 500 a, the thickness of the first silicon oxynitride layer 306 ranges from 200 a to 400 a, the first silicon nitride layer 304 serves as an etching stop layer to protect a thin film below the first silicon nitride layer 304, and the first silicon oxynitride layer 306 serves as a photolithography anti-reflection layer of the metal silicide barrier layer to optimize the feature size of the metal silicide barrier layer and improve the photolithography uniformity.
In one embodiment, the second etch stop layer film 404 includes, from bottom to top, a second silicon oxynitride film 502 and a second silicon nitride layer film 504.
In one embodiment, the thickness of the second silicon oxynitride layer film 502 ranges from 300 angstroms to 600 angstroms, and the thickness of the second silicon nitride layer film 504 ranges from 500 angstroms to 1500 angstroms. The second silicon nitride layer film 504 serves as an etching stopper layer to protect the film below the second silicon nitride layer film.
In one embodiment, the second etch stop layer film 404 comprises a silicon oxynitride film.
In one embodiment, the second etch stop layer film 404 comprises a second silicon nitride layer film.
In one embodiment, the second etch stop layer film 404 comprises at least one of a silicon oxycarbide film, a silicon carbonitride film, and a silicon oxycarbonitride film.
In one embodiment, before the performing the etching process, the method further includes: and a step of forming an interlayer dielectric film (not shown) on the substrate 102, that is, forming an interlayer dielectric film on the second etching barrier film 404.
In one embodiment, the interlayer dielectric film comprises a silicon oxide film.
As shown in fig. 3 and 4, in one embodiment, the step of performing the etching process includes:
first, a first photoresist pattern 117 is formed on the substrate 102, and the first photoresist pattern 117 exposes the interlayer dielectric layer film of the first preset region of the first contact hole 116 and the interlayer dielectric layer film of the second preset region of the second contact hole.
And secondly, performing a first etching process to remove the interlayer dielectric layer films in the first preset area and the second preset area, wherein the first etching process takes the second etching barrier layer film 404 as an etching barrier layer, the etching rate of the interlayer dielectric layer film etched by the first etching process is greater than that of the second etching barrier layer film 404, and the etching of the first preset area and the second preset area is stopped on the second etching barrier layer film 404 through the second etching barrier layer film 404 positioned below the interlayer dielectric layer film.
Thirdly, performing a second etching process to remove the second etching barrier layer films in the first preset area and the second preset area; in the second etching process, the second oxide layer film 402 is used as an etching barrier layer and an etching buffer layer to obtain a second etching barrier layer 406 formed by the residual second etching barrier layer film 404; the etching rate of the second etching process for etching the second etching barrier film 404 is greater than the etching rate for etching the second oxide film 402, and the etching of the first preset area and the etching of the second preset area are both stopped at the second oxide film 402 through the second oxide film 402 located below the second etching barrier film 404.
In one embodiment, the second etching stop layer film 404 includes a second silicon oxynitride layer film 502 and a second silicon nitride layer film 504 from bottom to top, and a second silicon oxynitride layer 506 formed by the remaining second silicon oxynitride layer film 502 and a second silicon nitride layer 508 formed by the remaining second silicon nitride layer film 504 are obtained by the second etching process, and the second silicon oxynitride layer 506 and the second silicon nitride layer 508 together form the second etching stop layer 406.
Finally, carrying out a third etching process to remove the second oxide layer films in the first preset area and the second preset area; in the third etching process, the metal silicide blocking layer 112 is used as an etching blocking layer to obtain a second oxide layer 408 formed by the remaining second oxide layer film 402, and the second etching blocking layer 406 and the second oxide layer 408 jointly form a hole etching blocking layer 115 positioned on the gate structure 106, the metal silicide blocking layer 112, the drain region 108 and the source region 110; the etching rate of the third etching process for etching the second oxide layer thin film 402 is greater than the etching rate for etching the metal silicide blocking layer 112, and when the etching of the second preset region is stopped on the surface of the lead-out region through the metal silicide blocking layer 112 located below the second oxide layer thin film 402, the etching of the first preset region is stopped on the metal silicide blocking layer 112, so that the bottom of the first contact hole 116 stably hovers on the surface of the metal silicide blocking layer 112. And ohmic contact with the lead-out region is realized through the conductive material filled in the second contact hole of the lead-out region.
In one embodiment, the third etching process is followed by a step of removing the first photoresist pattern 117 from the surface of the substrate 102.
In one embodiment, the method further comprises: a step of filling the first contact hole 116 and the second contact hole with a conductive material, wherein the conductive material may be any suitable conductive material known to those skilled in the art, including but not limited to a metal material; wherein, the metal material can comprise one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.
In one embodiment, the first contact hole and the second contact hole may be filled with the same conductive material, such as tungsten metal, or may be filled with different conductive materials.
In one embodiment, before forming the hole etching barrier film on the substrate, the method further comprises:
forming a metal silicide 128 on the substrate 102, wherein the metal silicide 128 is located on the surface of the gate structure 106, the surface of the source region 110, and the surface of the drain region 108, which are not covered by the metal silicide blocking layer 112, and the contact resistance can be reduced by disposing the metal silicide.
In one embodiment, the metal silicide 128 may be CoSix, NiSix, PtSix, or a combination thereof.
In one embodiment, the etching of the third etching process in the second predetermined area is stopped on the metal silicide 128 on the surface of the lead-out area.
In one embodiment, the width of the first contact hole is greater than the width of the second contact hole.
In one embodiment, the first contact hole 116 may be partially located on the surface of the metal silicide blocking layer 112 above the gate structure 106, partially located on the surface of the metal silicide blocking layer 112 above the sidewall spacer 126, and partially located on the surface of the metal silicide blocking layer 112 on the surface of the substrate 102 between the sidewall spacer 126 and the drain region 108.
In one embodiment, the first contact hole 116 may be located only on the surface of the metal silicide blocking layer 112 on the surface of the substrate 102 between the sidewall spacer 126 and the drain region 108.
In one embodiment, the first contact hole 116 may be partially located on the surface of the metal silicide blocking layer 112 above the sidewall spacer 126 and partially located on the surface of the metal silicide blocking layer 112 on the surface of the substrate 102 between the sidewall spacer 126 and the drain region 108.
The preparation method of the lateral diffusion metal oxide semiconductor device comprises the steps of forming a metal silicide blocking layer on the substrate, wherein the metal silicide blocking layer covers the surface, located between the grid structure and the drain electrode region, of the drift region and extends to the surface of part of the grid structure; forming a hole etching barrier layer film on the substrate, wherein the hole etching barrier layer film comprises a second oxide layer film and a second etching barrier layer film positioned on the surface of the second oxide layer film; the barrier layer film is etched through the holes, so that when a first contact hole is formed in the metal silicide barrier layer and a second contact hole is formed in the lead-out area through the same etching process, the purpose that the bottom of the second contact hole stays on the surface of the lead-out area, the bottom of the first contact hole, namely the filling hole of the metal field plate, stays on the surface of the metal silicide barrier layer is achieved, the hole-type metal field plate with the same suspension position is obtained, and the influence of the fluctuation of the process procedure on the suspension position of the hole-type metal field plate is avoided.
As shown in fig. 4, in one embodiment, a lateral diffusion metal oxide semiconductor device is provided, comprising:
a substrate 102;
a drift region 104 in the substrate 102;
a gate structure 106 located on the substrate 102 and covering a part of the surface of the drift region 104;
a drain region 108 in the drift region 104 on one side of the gate structure 106;
a source region 110 in the substrate 102 on the other side of the gate structure 106;
a metal silicide blocking layer 112 covering the surface of the drift region 104 between the gate structure 106 and the drain region 108 and extending to a portion of the surface of the gate structure 106;
a hole-etching blocking layer 115 comprising a second oxide layer 408 and a second etching blocking layer 406 on the surface of the second oxide layer 408, wherein the second oxide layer 408 and the second etching blocking layer 406 are located on the gate structure 106, the metal silicide blocking layer 112, the drain region 108 and the source region 110;
a first contact hole 116 opened on the metal silicide blocking layer 112 and penetrating through the hole etching blocking layer 115 above the metal silicide blocking layer 112, wherein the bottom of the first contact hole 116 stays on the surface of the metal silicide blocking layer 112;
the second contact hole is formed in the lead-out area, penetrates through the hole etching barrier layer 115 above the lead-out area, and the bottom of the second contact hole stays on the surface of the lead-out area;
the lead-out region at least comprises one of a drain region, a source region and the gate structure uncovered by the metal silicide blocking layer, and the second contact hole corresponds to the lead-out region and at least comprises one of a drain contact hole 118 opened on the drain region 108, a source contact hole 120 opened on the source region 110 and a gate contact hole 122 opened on the gate structure 106 uncovered by the metal silicide blocking layer 112. That is, the second contact hole at least comprises one of the drain contact hole 118, the source contact hole 120 and the gate contact hole 122, the lead-out region at least comprises the drain region 108, the source region 110 and one of the gate structures 106 not covered by the metal silicide blocking layer 112, and the lead-out region corresponds to the second contact hole, that is, when the second contact hole comprises the drain contact hole 118, the lead-out region comprises the drain region 108; when the second contact hole includes the source contact hole 120, the lead-out region includes the source region 110, and when the second contact hole includes the gate contact hole 122, the lead-out region includes the source region 110.
In one embodiment, the second etch stop layer 406 includes, from bottom to top, a second silicon oxynitride layer 506 and a second silicon nitride layer 508.
In one embodiment, the second etch stop layer 406 comprises a second silicon oxynitride layer.
In one embodiment, the second etch stop layer 406 comprises a second silicon nitride layer.
In one embodiment, the metal silicide blocking layer 112 includes a first oxide layer and a first silicon nitride layer stacked in sequence from bottom to top.
In one embodiment, the metal silicide blocking layer 112 includes a first oxide layer and a first silicon oxynitride layer stacked in sequence from bottom to top.
In one embodiment, the metal silicide blocking layer 112 includes, from bottom to top, a first oxide layer 302, a first silicon nitride layer 304, and a first silicon oxynitride layer 306, which are stacked in this order.
In one embodiment, the width of the first contact hole 116 is greater than the width of the second contact hole.
In one embodiment, the ldmos device further includes:
a metal silicide 128 on the surface of the gate structure 106, the surface of the source region 110, and the surface of the drain region 108 not covered by the metal silicide blocking layer 112, wherein the contact resistance can be reduced by disposing a metal silicide, and the bottom of the second contact hole exposes the metal silicide 128.
In one embodiment, the metal silicide 128 may be CoSix, NiSix, PtSix, or a combination thereof.
In one embodiment, the device further includes an interlayer dielectric layer on the hole etching blocking layer 115, the first contact hole 116 penetrates through the interlayer dielectric layer above the metal silicide blocking layer 112, and the second contact hole penetrates through the interlayer dielectric layer above the lead-out region.
In one embodiment, the ldmos device further includes: a conductive material in the first contact hole 116 and the second contact hole, wherein the conductive material may be any suitable conductive material known to those skilled in the art, including but not limited to a metal material; wherein, the metal material can comprise one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.
In one embodiment, the first contact hole and the second contact hole are filled with the same conductive material, such as tungsten metal, or may be filled with different conductive materials.
In one embodiment, an electronic device is provided, which comprises the laterally diffused metal oxide semiconductor device of any one of the above.
The transverse diffusion metal oxide semiconductor device and the electronic device comprise a metal silicide blocking layer, wherein the metal silicide blocking layer covers the surface of the drift region, which is positioned between the grid structure and the drain region, and extends to the surface of part of the grid structure; and the hole etching barrier layer comprises a second oxidation layer and a second etching barrier layer positioned on the surface of the second oxidation layer, the second oxidation layer and the second etching barrier layer are positioned on the grid structure, the metal silicide barrier layer, the source region and the drain region, and when a first contact hole is formed on the metal silicide barrier layer and a second contact hole is formed in the lead-out region through the hole etching barrier layer by the same etching process, the purpose that the bottom of the second contact hole stays on the surface of the lead-out region while the bottom of the first contact hole, namely the bottom of a filling hole of the metal field plate stays on the surface of the metal silicide barrier layer is realized, so that the hole type metal field plate with the same suspension position is obtained, and the influence of the fluctuation of the process procedure on the suspension height position of the hole type metal field plate is avoided.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (14)

1. A laterally diffused metal oxide semiconductor device, comprising:
a substrate;
a drift region in the substrate;
the gate structure is positioned on the substrate and covers part of the surface of the drift region;
a drain region in the drift region on one side of the gate structure;
the source region is positioned in the substrate at the other side of the grid structure;
the metal silicide blocking layer covers the surface, between the gate structure and the drain region, of the drift region and extends to part of the surface of the gate structure;
the hole etching barrier layer comprises a second oxide layer and a second etching barrier layer positioned on the surface of the second oxide layer, and the second oxide layer and the second etching barrier layer are positioned on the grid structure, the metal silicide barrier layer, the source region and the drain region;
the first contact hole is formed in the metal silicide barrier layer and penetrates through the hole etching barrier layer above the metal silicide barrier layer, and the bottom of the first contact hole stays on the surface of the metal silicide barrier layer;
the second contact hole is formed in the lead-out area, penetrates through the hole etching barrier layer above the lead-out area, and the bottom of the second contact hole stays on the surface of the lead-out area;
the lead-out region at least comprises one of a drain region, a source region and the grid structure which is not covered by the metal silicide barrier layer, and the second contact hole corresponds to the lead-out region and at least comprises one of a drain contact hole arranged on the drain region, a source contact hole arranged on the source region and a grid contact hole arranged on the grid structure which is not covered by the metal silicide barrier layer.
2. The ldmos device set forth in claim 1 wherein said second etch stop layer comprises, from bottom to top, a second silicon oxynitride layer and a second silicon nitride layer; or the second etching barrier layer comprises a second silicon oxynitride layer; or the second etch stop layer comprises a second silicon nitride layer.
3. The laterally diffused metal oxide semiconductor device of claim 1, wherein the metal silicide blocking layer comprises, from bottom to top, a first oxide layer, a first silicon nitride layer, stacked in that order; or the metal silicide barrier layer comprises a first oxidation layer, a first silicon nitride layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top; or the metal silicide barrier layer comprises a first oxidation layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top.
4. The ldmos device set forth in claim 1 wherein said first contact hole has a width greater than a width of said second contact hole.
5. The laterally diffused metal oxide semiconductor device of claim 1, further comprising:
and the metal silicide is positioned on the surface of the gate structure which is not covered by the metal silicide barrier layer, the surface of the source region and the surface of the drain region.
6. The ldmos device set forth in claim 1 further including an interlevel dielectric layer overlying said hole etch stop layer, said first contact hole passing through said interlevel dielectric layer above said metal silicide stop layer, said second contact hole passing through said interlevel dielectric layer above said pull-out region.
7. A method for manufacturing a laterally diffused metal oxide semiconductor device, comprising:
the method comprises the steps of obtaining a substrate, wherein a drift region is formed in the substrate, a gate structure covering part of the surface of the drift region is formed on the substrate, a drain region is formed in the drift region on one side of the gate structure, and a source region is formed in the substrate on the other side of the gate structure;
forming a metal silicide blocking layer on the substrate, wherein the metal silicide blocking layer covers the surface of the drift region between the gate structure and the drain region and extends to part of the surface of the gate structure;
forming a hole etching barrier layer film on the substrate, wherein the hole etching barrier layer film comprises a second oxide layer film and a second etching barrier layer film positioned on the surface of the second oxide layer film;
performing an etching process, forming a first contact hole on the metal silicide barrier layer, wherein the bottom of the first contact hole stays on the surface of the metal silicide barrier layer; forming a second contact hole on the lead-out area, wherein the bottom of the second contact hole stays on the surface of the lead-out area;
the lead-out region at least comprises one of a drain region, a source region and the grid structure which is not covered by the metal silicide barrier layer, the second contact hole corresponds to the lead-out region, and the step of forming the second contact hole on the lead-out region at least comprises one of forming a drain contact hole on the drain region, forming a source contact hole on the source region and forming a grid contact hole on the grid structure which is not covered by the metal silicide barrier layer.
8. The production method according to claim 7, wherein the second etching stopper film includes, from bottom to top, a second silicon oxynitride layer film and a second silicon nitride layer film; or the second etching barrier layer film comprises a second silicon oxynitride layer film; or the second etching barrier layer comprises a second silicon nitride layer film.
9. The method according to claim 7, wherein the etching process is performed before the etching process, and further comprising: and forming an interlayer dielectric layer film on the substrate.
10. The method of claim 9, wherein the step of performing an etching process comprises:
forming a first photoresist pattern on the substrate, wherein the first photoresist pattern exposes the interlayer dielectric layer film of a first preset area of the first contact hole and the interlayer dielectric layer film of a second preset area of the second contact hole;
performing a first etching process to remove the interlayer dielectric layer films in the first preset area and the second preset area;
performing a second etching process to remove the second etching barrier layer film in the first preset area and the second preset area;
performing a third etching process to remove the second oxide layer films in the first preset area and the second preset area;
the etching rate of the interlayer dielectric layer film etched by the first etching process is greater than that of the second etching barrier layer film etched by the second etching process, the etching rate of the second etching barrier layer film etched by the second etching process is greater than that of the second oxide layer film etched by the second etching process, and the etching rate of the second oxide layer film etched by the third etching process is greater than that of the metal silicide barrier layer etched by the third etching process.
11. The preparation method according to claim 7, wherein the metal silicide blocking layer comprises a first oxide layer and a first silicon nitride layer which are sequentially stacked from bottom to top, or the metal silicide blocking layer comprises a first oxide layer, a first silicon nitride layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top; or the metal silicide barrier layer comprises a first oxidation layer and a first silicon oxynitride layer which are sequentially stacked from bottom to top.
12. The method of claim 7, wherein a width of the first contact hole is greater than a width of the second contact hole.
13. The method of claim 7, wherein forming the aperture etch stop layer film on the substrate further comprises:
and forming metal silicide on the substrate, wherein the metal silicide is positioned on the gate structure which is not covered by the metal silicide barrier layer, the surface of the source region and the surface of the drain region.
14. An electronic device, characterized in that it comprises a laterally diffused metal oxide semiconductor device according to any one of claims 1-6.
CN202010902338.1A 2020-09-01 2020-09-01 Laterally diffused metal oxide semiconductor device, preparation method thereof and electronic device Pending CN114122133A (en)

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