CN102386138B - Through hole etching method, integrated circuit manufacturing method and integrated circuit - Google Patents
Through hole etching method, integrated circuit manufacturing method and integrated circuit Download PDFInfo
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Abstract
The invention provides a through hole etching method, an integrated circuit manufacturing method and an integrated circuit. According to the through hole etching method provided by the invention, a deposition step of a silicon dioxide film is used for depositing a layer of the silicon dioxide film; a deposition step of a first silicon nitride film is used for depositing a layer of the first silicon nitride film after a silicon carbide film is deposited; a removal step of the first silicon nitride film is used for etching the first silicon nitride film in a PMOS (P-channel metal oxide semiconductor) device region by utilizing silicon dioxide as an etching stopping layer; a deposition step of the silicon carbide film is used for depositing the silicon carbide film; a deposition step of a second silicon nitride film is used for depositing a layer of the second silicon nitride film; and a removal step of the second silicon nitride film is used for removing the second silicon nitride film in an NMOS (N-channel metal oxide semiconductor) region by utilizing a dry etching method.
Description
Technical field
The present invention relates to semiconductor preparing technical field, the integrated circuit that more precisely, the present invention relates to a kind of etching method for forming through hole, adopted the method for manufacturing integrated circuit of this etching method for forming through hole and made according to this method for manufacturing integrated circuit.
Background technology
Along with development and the integrated circuit (IC) chip trend that proportionally size is dwindled of semiconductor related manufacturing process, stress engineering role aspect semiconductor technology and performance of semiconductor device is more and more obvious, stress engineering is extensively adapted to improve on the semiconductor device of transistor carrier mobility, especially on some special chip types, as complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal-Oxide-Semiconductor) device.
Conventionally, in complicated preparation technology's flow process of cmos device, have various stress, due to progressively dwindling of device size, and the stress of finally staying in device channel region has larger impact to the performance of device.A lot of stress is improved the performance of device, and different types of stress has different influence to the charge carrier in device (being electronics and hole) mobility.For example, on cmos device channel direction, tensile stress is useful to NMOS electron mobility, and compression is useful to PMOS hole mobility.
Via etch stop-layer (Contact-Etch-Stop-Layer, be CESL) stress engineering, in via etch stop-layer film deposition process, by adjusting sedimentary condition, adding stress in film inside (can be compression, also can be tensile stress), this stress is transmitted in cmos device raceway groove, can exert an influence to the mobility of charge carrier.For example, for nmos device (as shown in Figure 1), in the time of deposition via etch stop-layer ST film, by adjusting sedimentary condition, in the inner compression that produces of film, this stress is transmitted in nmos device raceway groove, and raceway groove is formed to tensile stress, because the tensile stress on channel direction contributes to improve the electron mobility of nmos device, so the inner via etch stop-layer ST that keeps compression is useful to the electron mobility of raising nmos device.
Because the stress in raceway groove can cause different impacts to NMOS and PMOS, for example, on cmos device channel direction, tensile stress is useful to NMOS electron mobility, and compression is useful to PMOS hole mobility.So when the stress engineering of utilizing single via etch stop-layer is improved the performance of a kind of device (such as NMOS), always will sacrifice the performance of another kind of device (such as PMOS).
In order to improve this negative impact, can adopt dual via etch stop layer process.The flow process of dual via etch stop layer process as shown in Figures 2 to 5.First deposit ground floor silica membrane 10 (the first silica membrane 10); as the protective film of removing via etch stop-layer; then deposit the first silicon nitride film 20 that one deck can form tensile stress in raceway groove as via etch stop-layer (as Fig. 2); this electron mobility to nmos device is improved effect, but the hole mobility of PMOS device is had to reducing effect.Then adopt dry method of carving to remove the silicon nitride film 20 of PMOS device area.Can stop (as Fig. 3) dry quarter in etching into the first silicon dioxide protective film.Deposit again afterwards second layer silicon dioxide protective film (the second silica membrane 11); so that after dry quarter in process, first silicon nitride film 20 in territory, nmos area is protected; next be the second silicon nitride film 22 (as Fig. 4) that deposition one deck can form compression in raceway groove; this is conducive to improve the hole mobility of PMOS device, but can reduce the electron mobility of nmos device.Finally, utilize dry method of carving to remove second silicon nitride film 22 (as Fig. 5) in territory, nmos area.In the final device architecture forming, in NMOS raceway groove, form tensile stress, in PMOS raceway groove, form compression.Dual via etch stop-layer stress engineering, can improve the electron mobility in nmos device, can improve again the hole mobility in PMOS device.
In dual via etch stop layer process, can bring the problem in follow-up via etch process in the overlapping part of (compression and tensile stress) etching stop layers of two kinds of stress, as Fig. 7 and Fig. 8 describe.In Fig. 7, completed dual via etch stop layer process, follow-up layer insulation medium 30 (generally adopting phosphorosilicate glass, i.e. PSG) deposition and chemico-mechanical polishing also complete.Above the polysilicon 40 of the silicon nitride film (the first silicon nitride film 20 and the second silicon nitride film 22) of two kinds of different stress on a shallow trench, have overlapping.Next can carry out via etch process.As shown in Figure 8, through hole A drops on active area, and through hole B drops on the overlapping region of silicon nitride film (the first silicon nitride film 20 and the second silicon nitride film 22).
For the etching of through hole A; first the first step; adopt dielectric between high level/silicon nitride to select the lithographic method of ratio; first through hole can be parked on the first silicon nitride film 20 (via etch stop-layer); then carry out second step; adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve and wear the first silicon nitride film 20; and be parked on silicon dioxide protective film; last the 3rd step; adopt high silicon dioxide/silicon to select the lithographic method of ratio that through hole is opened completely; and be parked on active area silicon and polysilicon 40, complete via etch.
But; for through hole B; because it is positioned at the crossover region of two kinds of different stress nitride silicon thin films (the first silicon nitride film 20 and the second silicon nitride film 22); carrying out after second step via etch process; through hole only can be parked on crossover region the second silicon dioxide protective film 11; this can cause the 3rd step etching to carve completely and wear the first silicon nitride film 20, and final through hole B cannot open completely.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of etching method for forming through hole that normal areas and overlapping region through hole can both open completely, integrated circuit that has adopted the method for manufacturing integrated circuit of this etching method for forming through hole and made according to this method for manufacturing integrated circuit realized is provided.
According to a first aspect of the invention, provide a kind of etching method for forming through hole, it comprises: silica membrane deposition step, for depositing layer of silicon dioxide film; The first silicon nitride film deposition step, for depositing one deck the first silicon nitride film after having deposited described silica membrane; The first silicon nitride film part is removed step, for utilizing first silicon nitride film of silicon dioxide as etching stop layer etching PMOS device area; Carborundum films deposition step, for depositing silicon carbide film; The second silicon nitride film deposition step, for depositing one deck the second silicon nitride film; The second silicon nitride film part is removed step, for utilizing dry method of carving to remove second silicon nitride film in nmos device region.
Preferably, described etching method for forming through hole further comprises: the first etch step, be used for utilizing silicon dioxide/silicon nitride to select than carrying out etching, so that the through hole in nmos device region is parked on described carborundum films, the through hole that is positioned at the overlapping region of nmos device and PMOS device is parked on the second silicon nitride film, and the through hole that is positioned at PMOS device area is parked on the second silicon nitride film.
Preferably; described etching method for forming through hole further comprises: the second etch step; be used for utilizing silicon nitride/silicon carbide to select than carrying out etching; so that the through hole that is positioned at nmos device region is still parked on carborundum films; the through hole that is positioned at the overlapping region of nmos device and PMOS device is worn the second silicon nitride film and is parked on carborundum films quarter, and the through hole that is positioned at PMOS device area is worn the second silicon nitride film and is parked on carborundum protective film quarter.
Preferably; described etching method for forming through hole further comprises: the 3rd etch step; be used for utilizing silicon carbide/silicon dioxide to select than carrying out etching; to carve the carborundum protective film of reach through hole position; the through hole that is positioned at nmos device region is parked on the first silicon nitride film; the through hole that is positioned at the overlapping region of nmos device and PMOS device is parked in the first silicon nitride film, and the through hole that is positioned at PMOS device area can be parked on silica membrane.
Preferably, described etching method for forming through hole further comprises: the 4th etch step, be used for utilizing silicon nitride/silicon dioxide to select than carrying out etching, wear the first silicon nitride film and be parked on silica membrane quarter to make the through hole that is positioned at nmos device region, the through hole that is positioned at the overlapping region of nmos device and PMOS device is worn the first silicon nitride film and is parked on silica membrane quarter, and the through hole that is positioned at PMOS device area is still parked on silica membrane.
Preferably, described etching method for forming through hole further comprises: the 5th etch step, for utilizing silica/silicon to select than carrying out etching, to carve the silica membrane of wearing all lead to the hole site place, all through holes are parked on polysilicon gate or active area silicon, complete via etch.
Preferably, described etching method for forming through hole is for the following dual via etch process of 45nm.
By adopting according to the etching method for forming through hole described in first aspect present invention, can use carborundum protective film to substitute the second layer silicon dioxide protective film in original technique, realize normal areas and overlapping region through hole can both be opened completely.
According to a second aspect of the invention, provide a kind of method for manufacturing integrated circuit, it is characterized in that having adopted the etching method for forming through hole according to described in first aspect present invention.
According to third aspect present invention, provide a kind of employing integrated circuit that described according to a second aspect of the invention method for manufacturing integrated circuit is made.
Owing to having adopted according to the etching method for forming through hole described in first aspect present invention, therefore, it will be appreciated by persons skilled in the art that according to the method for manufacturing integrated circuit of second aspect present invention and according to the integrated circuit of third aspect present invention and can realize equally the achieved useful technique effect of etching method for forming through hole according to a first aspect of the invention.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the schematic diagram that utilizes the stress engineering of via etch stop-layer to improve nmos device electron mobility.
Fig. 2 to Fig. 5 schematically shows according to the flow chart of the dual via etch stop layer process of prior art.
Fig. 6 to Fig. 7 schematically shows the through hole that is positioned at the overlapping part of etching stop layer in the dual via etch stop layer process existing in prior art cannot open problem completely.
Fig. 8 to Figure 10 schematically show according to the embodiment of the present invention according to the etching method for forming through hole of the embodiment of the present invention.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
First, use carborundum protective film to substitute the second layer silicon dioxide protective film in original technique, as shown in Figure 8.
Specifically, first deposit layer of silicon dioxide film 12, as the protective film of removing via etch stop-layer.
Then, the first silicon nitride film 20 that deposition one deck can form tensile stress in raceway groove is as via etch stop-layer (as Fig. 2), this is improved effect to the electron mobility that improves nmos device, but the hole mobility of PMOS device is had to reducing effect.
Then, adopt dry method of carving to remove the silicon nitride film 20 of PMOS device area.Can stop (as Fig. 3) dry quarter in etching into ground floor silicon dioxide protective film.
Afterwards, then depositing silicon carbide protective film (, carborundum films 50), so as after dry quarter in process, first silicon nitride film 20 in territory, nmos area is protected.
Next, deposition one deck can form the second silicon nitride film 22 of compression in raceway groove, and this is conducive to improve the hole mobility of PMOS device, but the electron mobility of nmos device is had to reducing effect.
Finally, utilize dry method of carving to remove second silicon nitride film 22 (as Fig. 5) in territory, nmos area.
Wherein, unlike the prior art, carborundum films 50 replaces silica membrane 12.
After obtaining the structure shown in Fig. 8, adopt subsequently following etch step to carry out etching to through hole:
The first step, adopt dielectric between high level/silicon nitride to select to carry out etching than the lithographic method of (being that high silicon dioxide/silicon nitride is selected ratio), first the through hole that is now positioned at normal areas nmos device region can be parked on carborundum protective film (carborundum films 50), the through hole that is positioned at the overlapping region of nmos device and PMOS device can be parked on upper silicon nitride film (producing the second silicon nitride film 22 of compression), the through hole that is positioned at normal areas PMOS device area can be parked on upper silicon nitride film (producing the second silicon nitride film 22 of compression).
Second step, adopt high silicon nitride/silicon carbide to select the lithographic method of ratio to carve and wear silicon nitride film, the through hole that is now positioned at normal areas nmos device region is still parked on carborundum protective film (carborundum films 50), the through hole that is positioned at the overlapping region of nmos device and PMOS device can be carved and puts on a layer silicon nitride film (the second silicon nitride film 22) and be parked on carborundum protective film (carborundum films 50), the through hole that is positioned at normal areas PMOS device area can be carved and puts on a layer silicon nitride film (the second silicon nitride film 22) and be parked on carborundum protective film.
The 3rd step, adopt high silicon carbide/silicon dioxide to select the lithographic method of ratio to carve the carborundum protective film of reach through hole, cross section after etching as shown in Figure 9, the through hole that is now arranged in normal areas nmos device region can be parked on lower floor's silicon nitride film (producing the first silicon nitride film 20 of tensile stress) (Fig. 9 through hole C), the through hole that is arranged in the overlapping region of nmos device and PMOS device can be parked on lower floor's silicon nitride film (producing the first silicon nitride film 20 of tensile stress) (Fig. 9 through hole D), the through hole that is positioned at normal areas PMOS device area can be parked in (not shown) on ground floor silicon dioxide protective film (silica membrane 12).
The 4th step; adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve lower floor's silicon nitride film (the first silicon nitride film 20) of the through hole of wearing the overlapping region that is positioned at nmos device and PMOS device, be now positioned at the through hole in normal areas nmos device region, the through hole that is positioned at the overlapping region of nmos device and PMOS device, the through hole that is positioned at normal areas PMOS device area and all can be parked on ground floor silicon dioxide protective film (silica membrane 12).; the through hole that is positioned at nmos device region is worn the first silicon nitride film and is parked on silica membrane quarter; the through hole that is positioned at the overlapping region of nmos device and PMOS device is worn the first silicon nitride film and is parked on silica membrane quarter, and the through hole that is positioned at PMOS device area is still parked on silica membrane.
The 5th step, adopts silica/silicon to select the lithographic method of ratio through hole to be opened completely to (silica membrane of at once wearing all lead to the hole site place), and is parked on polysilicon and active area silicon, completes via etch.(as shown in figure 10).
As shown in figure 10, the through hole that is positioned at the through hole of crossover region and is positioned at normal areas carries out etching and is all fully opened.
Thus, the second layer silicon dioxide protective film in the alternative original technique of use carborundum protective film, realizes normal areas and overlapping region through hole can both be opened completely.Therefore, solved in dual via etch stop layer process, in the time that through hole drops on the overlapping part of etching stop layer of two kinds of stress, the problem that cannot open completely.Use carborundum protective film to substitute the second layer silicon dioxide protective film in original technique; adopt high silicon dioxide/silicon nitride to select ratio, high silicon carbide/silicon dioxide to select ratio, high silicon nitride/silicon dioxide to select the lithographic method of ratio; through hole is carried out to etching, reach the object that the through hole of normal areas and overlapping region can both perfect be opened.
For example, preferably, in the dual via etch stop layer process of 45nm process, can apply this method and realize the object of opening all through holes.
It should be noted that, for example, although principle of the present invention is shown to be formed with the semiconductor structure of shallow trench isolation STI, the present invention is not limited to this, but can on the semiconductor structure that is not formed with shallow trench isolation STI, carry out method of the present invention.
In another embodiment of the present invention, the present invention also provides and has adopted the method for manufacturing integrated circuit of above-mentioned etching method for forming through hole and according to this method for manufacturing integrated circuit.
In another embodiment of the present invention, the present invention also provides a kind of integrated circuit of being made up of this method for manufacturing integrated circuit, and for example this integrated circuit comprises MOS device or cmos device.
Be understandable that, although the present invention discloses as above with preferred embodiment, but above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (9)
1. an etching method for forming through hole, is characterized in that comprising:
Silica membrane deposition step, for depositing layer of silicon dioxide film;
The first silicon nitride film deposition step, for depositing one deck the first silicon nitride film after having deposited described silica membrane;
The first silicon nitride film part is removed step, for utilizing first silicon nitride film of silicon dioxide as etching stop layer etching PMOS device area;
Carborundum films deposition step, for depositing silicon carbide film;
The second silicon nitride film deposition step, for depositing one deck the second silicon nitride film;
The second silicon nitride film part is removed step, for utilizing dry method of carving to remove second silicon nitride film in nmos device region.
2. etching method for forming through hole according to claim 1, is characterized in that further comprising:
The first etch step, be used for utilizing silicon dioxide/silicon nitride to select than carrying out etching, so that the through hole in nmos device region is parked on described carborundum films, the through hole that is positioned at the overlapping region of nmos device and PMOS device is parked on the second silicon nitride film, and the through hole that is positioned at PMOS device area is parked on the second silicon nitride film.
3. etching method for forming through hole according to claim 2, is characterized in that further comprising:
The second etch step; be used for utilizing silicon nitride/silicon carbide to select than carrying out etching; so that the through hole that is positioned at nmos device region is still parked on carborundum films; the through hole that is positioned at the overlapping region of nmos device and PMOS device is worn the second silicon nitride film and is parked on carborundum films quarter, and the through hole that is positioned at PMOS device area is worn the second silicon nitride film and is parked on carborundum protective film quarter.
4. etching method for forming through hole according to claim 3, is characterized in that further comprising:
The 3rd etch step; be used for utilizing silicon carbide/silicon dioxide to select than carrying out etching; to carve the carborundum protective film of reach through hole position; the through hole that is positioned at nmos device region is parked on the first silicon nitride film; the through hole that is positioned at the overlapping region of nmos device and PMOS device is parked in the first silicon nitride film, and the through hole that is positioned at PMOS device area can be parked on silica membrane.
5. etching method for forming through hole according to claim 4, is characterized in that further comprising:
The 4th etch step, be used for utilizing silicon nitride/silicon dioxide to select than carrying out etching, wear the first silicon nitride film and be parked on silica membrane quarter to make the through hole that is positioned at nmos device region, the through hole that is positioned at the overlapping region of nmos device and PMOS device is worn the first silicon nitride film and is parked on silica membrane quarter, and the through hole that is positioned at PMOS device area is still parked on silica membrane.
6. etching method for forming through hole according to claim 5, is characterized in that further comprising:
The 5th etch step, for utilizing silica/silicon to select than carrying out etching, to carve the silica membrane of wearing all lead to the hole site place, is parked on polysilicon gate or active area silicon all through holes, completes via etch.
7. according to the etching method for forming through hole one of claim 1 to 6 Suo Shu, it is characterized in that described etching method for forming through hole is for the following dual via etch process of 45nm.
8. a method for manufacturing integrated circuit, is characterized in that having adopted the etching method for forming through hole according to one of claim 1 to 7 Suo Shu.
9. an integrated circuit that adopts method for manufacturing integrated circuit according to claim 8 to make.
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| US7052946B2 (en) * | 2004-03-10 | 2006-05-30 | Taiwan Semiconductor Manufacturing Co. Ltd. | Method for selectively stressing MOSFETs to improve charge carrier mobility |
| US20070257323A1 (en) * | 2006-05-05 | 2007-11-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stacked contact structure and method of fabricating the same |
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| US8614484B2 (en) * | 2009-12-24 | 2013-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage device with partial silicon germanium epi source/drain |
| US8048810B2 (en) * | 2010-01-29 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for metal gate N/P patterning |
| CN102437094B (en) * | 2011-08-17 | 2013-12-04 | 上海华力微电子有限公司 | Method for improving etching of through holes in double-through-hole etching stop layer crossover region |
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| US7238578B2 (en) * | 2004-08-31 | 2007-07-03 | Advanced Micro Devices, Inc. | Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions |
| CN1979807A (en) * | 2005-11-29 | 2007-06-13 | 联华电子股份有限公司 | Complementary metal oxide semiconductor element and for mation method |
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