CN102446819B - Method used for improving dual contact-etch-stop-layer crossover region contact etch - Google Patents
Method used for improving dual contact-etch-stop-layer crossover region contact etch Download PDFInfo
- Publication number
- CN102446819B CN102446819B CN201110235219.6A CN201110235219A CN102446819B CN 102446819 B CN102446819 B CN 102446819B CN 201110235219 A CN201110235219 A CN 201110235219A CN 102446819 B CN102446819 B CN 102446819B
- Authority
- CN
- China
- Prior art keywords
- protective film
- etching
- hole
- stress
- stress rete
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to a method for improving a dual contact-etch-stop-layer crossover region contact etch, and solves the problem that a contact formed on a crossover region in the prior art can not fully open. The method is characterized in that after a dual contact-etch-stop-layer process is finished, a dilute hydrofluoric acid is used and an ultrasonic cleaning method is adopted to remove an upper layer silica protective film and an upper layer silicon nitride stress film; and then an etching method with different selection ratios is adopted to realize the technical effect of simultaneously opening contacts of a common region and the crossover region.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to a kind of method of improving dual via etch stop-layer overlapping region via etch.
Background technology
Development and the integrated circuit (IC) chip trend that proportionally size is dwindled along with semiconductor related manufacturing process, stress engineering role aspect semiconductor technology and performance of semiconductor device is more and more obvious, and stress engineering is widely used in improving on the semiconductor device of transistor carrier mobility.Especially be applied on some special chip types, as complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal-Oxide-Semiconductor) device.
Conventionally, in complicated preparation technology's flow process of cmos device, have various stress, due to progressively dwindling of device size, and the stress of finally staying in device channel region has larger impact to the performance of device.A lot of stress is improved the performance of device, and different types of stress has different influence to the charge carrier in device (being electronics and hole) mobility.For example, on cmos device channel direction, tensile stress is useful to NMOS electron mobility, and compression is useful to PMOS hole mobility.
Via etch stop-layer (Contact-Etch-Stop-Layer, be CESL) stress engineering, in via etch stop-layer film deposition process, by adjusting sedimentary condition, in film inside, adding stress (can be compression, also can be tensile stress), this stress is transmitted in cmos device raceway groove, can exert an influence to the mobility of charge carrier.For example, for nmos device (as shown in Figure 1), when deposition via etch stop-layer film, by adjusting sedimentary condition, in the inner compression that produces of film, this stress is transmitted in nmos device raceway groove, and raceway groove is formed to tensile stress, because the tensile stress on channel direction contributes to improve the electron mobility of nmos device, so the inner via etch stop-layer that keeps compression is useful to the electron mobility of raising nmos device.
Because the stress in raceway groove can cause different impacts to NMOS and PMOS, for example, on cmos device channel direction, tensile stress is useful to NMOS electron mobility, and compression is useful to PMOS hole mobility.So when the stress engineering of utilizing single via etch stop-layer is improved the performance of a kind of device (such as NMOS), always will sacrifice the performance of another kind of device (such as PMOS).In order to improve this negative impact, can adopt dual via etch stop layer process.The flow process of dual via etch stop layer process is as shown in Fig. 2 A ~ 2D.First deposit layer of silicon dioxide film; as the protective film of removing via etch stop-layer; then deposit silicon nitride film that one deck can form tensile stress in raceway groove as via etch stop-layer (as Fig. 2 A); this is improved effect to improving the electron mobility of nmos device, but the hole mobility of PMOS device is had to reducing effect.Then adopt dry method of carving to remove the silicon nitride film of PMOS device area.Can stop (as Fig. 2 B) dry quarter when etching into silicon dioxide protective film.Deposit again afterwards layer of silicon dioxide protective film; so that after dry quarter in process, the silicon nitride film in territory, nmos area is protected; next be the silicon nitride film (as Fig. 2 C) that deposition one deck can form compression in raceway groove, this is conducive to improve the hole mobility of PMOS device.Finally, utilize dry method of carving to remove the compression silicon nitride film (as Fig. 2 D) in territory, nmos area.In the final device architecture forming, in NMOS raceway groove, form tensile stress, in PMOS raceway groove, form compression.Dual via etch stop-layer stress engineering, can improve the electron mobility in nmos device, can improve the hole mobility in PMOS device again.
In dual via etch stop layer process, in the overlapping part of (compression and tensile stress) etching stop layers of two kinds of stress, can bring the problem in follow-up via etch process, as Fig. 3 A ~ 3B describes.In Fig. 3 A, completed dual via etch stop layer process, follow-up layer insulation medium (generally adopting phosphorosilicate glass, i.e. PSG) deposition and chemico-mechanical polishing also complete.Above the polysilicon of the silicon nitride film of two kinds of different stress on a shallow trench, have overlapping.Next can carry out via etch process.As shown in Figure 3 B, through hole A drops on active area, and through hole B drops on the overlapping region of silicon nitride film.Etching for through hole A; first the first step; adopt dielectric between high level/silicon nitride to select the lithographic method of ratio; first through hole can be parked on silicon nitride film (via etch stop-layer); then carry out second step; adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve and wear silicon nitride film; and be parked on silicon dioxide protective film; last the 3rd step; adopt high silicon dioxide/silicon to select the lithographic method of ratio that through hole is opened completely; and be parked on active area silicon and polysilicon, complete via etch.But for through hole B; because it is positioned at the crossover region of two kinds of different stress nitride silicon thin films; there is upper and lower two-layer silicon dioxide protective film in this region; after carrying out second step via etch process; through hole only can be parked in above crossover region on layer of silicon dioxide protective film; this can cause the 3rd step etching to carve completely and wear a layer silicon nitride film, and final through hole B cannot open completely.
The present invention is directed to above problem; after dual via etch stop layer process completes; the hydrofluoric acid diluting by use also adopts ultrasonic cleaning method; remove upper strata silicon dioxide protective film and upper silicon nitride stress film, the technique effect that the through hole that adopts afterwards the lithographic method of different choice ratio to realize normal areas and overlapping region is opened simultaneously.
Summary of the invention
The invention discloses a kind of method of improving dual via etch stop-layer overlapping region via etch, in order to solve, in prior art, be formed on the problem that the through hole on overlapping region cannot be opened completely.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
A method of improving dual via etch stop-layer crossover region via etch forms at least one the first transistor and at least one transistor seconds on a substrate, and forms shallow trench area between the first transistor and transistor seconds; Deposit one deck the first protective film layer and one first stress rete successively on substrate, the first protection mould layer and the first stress rete cover the first transistor, transistor seconds, shallow trench area simultaneously; Etching is removed the first stress rete that covers top, transistor seconds region, and the stress rete that part is covered on shallow trench area retains; Deposit one second protective film layer and one second stress rete, make the second protective film and the second stress rete cover the top of the first protective film of exposing and the first stress rete not being etched away successively, wherein, comprises the following steps:
Etching is removed the second stress rete that covers top, the first transistor region, reserve part is positioned at shallow trench area top and is positioned at the part second stress rete of the first stress rete top, make the first stress rete and the second stress rete there is an overlapping region that is positioned at shallow trench area top, shallow trench area top is formed with polysilicon, makes overlapping region be positioned at the top of polysilicon region;
Adopt ultrasonic cleaning method to clean by cleaning fluid, remove the second stress rete that is positioned at overlap-add region, and the second protective film covering on the first stress rete is removed simultaneously;
Deposit one interlayer insulating medium layer, layer insulation dielectric layer covers the top of the first residual stress rete and residual the second stress rete;
Above shallow trench area, carry out etching, layer insulation dielectric layer, the first stress rete, the first protective film that the lithographic method of employing different choice ratio is opened respectively overlap-add region top form the first through hole that terminates in polysilicon.
The method of the dual via etch stop-layer of improvement as above crossover region via etch; wherein; on substrate, be also formed with one first active area; the first protective film, the first stress rete are covered the first active area, in the lithographic method etching that adopts different choice ratio forms the process of the first through hole, open successively respectively layer simultaneously
The dual via etch stop-layer of improvement as above crossover region etching method for forming through hole; wherein; on substrate, be also formed with one second active area; the first protective film, the second protective film, the second stress rete are covered the second active area, in the lithographic method etching that adopts different choice ratio forms the process of the first through hole, open successively respectively layer insulation dielectric layer, the second power rete, the second cuticular layer, the first protective film simultaneously and form the third through-hole that terminates in the second active area.
The dual via etch stop-layer of improvement as above crossover region etching method for forming through hole, wherein, the first protective film and the second protective film all form by deposit silicon dioxide protective film.
The dual via etch stop-layer of improvement as above crossover region etching method for forming through hole, wherein, the first transistor is NMOS pipe, transistor seconds is PMOS pipe.
The dual via etch stop-layer of improvement as above crossover region etching method for forming through hole, wherein, deposit produces the first stress rete of tensile stress, etching is removed after the first stress rete of part transistor seconds top, and the first stress rete that remains in the first transistor top provides tensile stress to the first transistor; Deposit produces the second stress rete of compression, and etching is removed after the second stress rete of part the first transistor top, and the second stress rete that remains in transistor seconds top provides compression to transistor seconds.
The dual via etch stop-layer of improvement as above crossover region etching method for forming through hole, wherein, the silicon nitride film that deposit produces tensile stress forms the first stress rete, and the silicon nitride film that deposit produces compression forms the second stress rete.
The dual via etch stop-layer of improvement as above crossover region etching method for forming through hole, wherein, adopts the hydrofluoric acid of dilution as cleaning fluid.
The dual via etch stop-layer of improvement as above overlapping region etching method for forming through hole; wherein; adopt ultrasonic cleaning method to clean specifically and comprise by cleaning fluid: to adopt cleaning fluid to clean removal and cover the second protective film on residual part the first stress rete; and make the second stress rete of overlap-add region form a cantilever beam structure; adopt ultrasonic method to make the second stress rete of cantilever beam structure part from fracture of root, so that the second stress rete of overlap-add region is all removed.
The dual via etch stop-layer of improvement as above overlapping region etching method for forming through hole, wherein, the width of overlapping region is greater than the diameter of through hole.
The dual via etch stop-layer of improvement as above overlapping region etching method for forming through hole, wherein, the etching formation method of the first through hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the first stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the first stress rete and terminate in the first protective film;
Step c: adopt high silicon dioxide/silicon to select the lithographic method etching of ratio to open the first protective film and terminate in polysilicon, form the first through hole.
The dual via etch stop-layer of improvement as above overlapping region etching method for forming through hole, wherein, the etching formation method of the second through hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the first stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the first stress rete and terminate in the first protective film;
Step c: adopt high silicon dioxide/silicon to select the lithographic method etching of ratio to open the first protective film and terminate in the first active area, form the second through hole.
The dual via etch stop-layer of improvement as above overlapping region etching method for forming through hole, wherein, the etching formation method of third through-hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the second stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the second power rete and terminate in the second protective film;
Step c: employing high silicon dioxide/silicon selects the lithographic method etching of ratio to open the second protective film and the first protective film terminates in the second active area, forms third through-hole.
In sum; the present invention improves dual via etch stop-layer crossover region etching method for forming through hole after dual via etch stop layer process completes; the hydrofluoric acid diluting by use also adopts ultrasonic cleaning method; remove upper strata silicon dioxide protective film and upper silicon nitride stress film, the technique effect that the through hole that adopts afterwards the lithographic method of different choice ratio to realize normal areas and overlapping region is opened simultaneously.
Accompanying drawing explanation
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the schematic diagram that utilizes the stress engineering raising nmos device electron mobility of via etch stop-layer in prior art;
Fig. 2 A is deposited in prior art in raceway groove, to form the schematic diagram after the first stress film;
Fig. 2 B is that the dry method of carving of available technology adopting is removed the schematic diagram after part the first stress rete that covers transistor seconds device area;
Fig. 2 C deposits the schematic diagram after second stress film that can form stress in raceway groove in prior art;
Fig. 2 D is the schematic diagram removing in prior art after second stress film in the first transistor region;
Fig. 3 A has overlapping schematic diagram above the silicon nitride film of two kinds of different stress in the prior art polysilicon on a shallow trench;
Fig. 3 B is the schematic diagram that in prior art, the through hole B on crossover region cannot open completely;
Fig. 4 A is the schematic diagram of widening the overlapping part of dual via etch stop-layer of the present invention;
Fig. 4 B is the schematic diagram after employing ultrasonic cleaning method of the present invention cleans by cleaning fluid
Fig. 4 C is the schematic diagram after the through hole that is positioned at crossover region of the present invention is fully opened with the through hole that is positioned at normal areas.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 2 A is deposited in prior art in raceway groove, to form the schematic diagram after the first stress film, refer to Fig. 2 A, a kind of method of improving dual via etch stop-layer crossover region via etch, on a substrate 10, form at least one the first transistor and at least one transistor seconds, and between the first transistor and transistor seconds, form shallow trench area 101; On substrate 10, deposit one deck the first protective film layer and one first stress rete 301, the first protection mould layers and the first stress rete 301 cover the first transistor, transistor seconds, shallow trench area 101 simultaneously successively; Fig. 2 B is the schematic diagram that the dry method of carving of available technology adopting is removed part the first stress rete that covers transistor seconds device area, refer to Fig. 2 B, etching is removed the first stress rete 301 that covers top, transistor seconds region, the stress rete that part is covered on shallow trench area 101 retains, the the first stress rete 301 that simultaneously covers the first transistor top also can be retained, thereby can provide stress for the first device, and then can exert an influence to the performance of the first device; Fig. 2 C deposits the schematic diagram after second stress film that can form stress in raceway groove in prior art; refer to Fig. 2 C; deposit one second protective film layer and one second stress rete 302 successively; make the second protective film 202 and the second stress rete 302 cover the top of the first protective film 201 of exposing and the first stress rete 301 not being etched away; wherein, comprise the following steps:
In conjunction with Fig. 2 C, refer to Fig. 4 A, etching is removed the second stress rete 302 that covers top, the first transistor region, reserve part is positioned at shallow trench area 101 tops and is positioned at the part second stress rete 302 of the first stress rete 301 tops, make the second stress rete 302 to provide stress for the second device, thereby the performance to the second device exerts an influence, and make the first stress rete 301 and the second stress rete 302 there is an overlapping region that is positioned at shallow trench area 101 tops, shallow trench area 101 tops are formed with polysilicon 102, before this polysilicon 102 is formed at the first protective film 201 formation, make overlapping region be positioned at the top in polysilicon 102 regions,
Referring to Fig. 4 A, Fig. 4 C, wherein, the width of overlapping region is greater than the diameter of the first through hole 401, than prior art the present invention overlapping region in the process of layout design, obviously widens, and makes to carry out in subsequent technique the technique effect that cleaning fluid ultrasonic cleaning method more easily reaches setting.
With ultrasonic cleaning method, by cleaning fluid, clean, removal is positioned at the second stress rete 302 of overlap-add region, and the second protective film 202 covering on residual part the first stress rete 301 is removed simultaneously, complete after this processing step, overlap-add region only exists part the first stress film 301 and the first protective film 201, the second protective film 302 to be completely removed;
Wherein, the present invention adopts the hydrofluoric acid of dilution as cleaning fluid.
Further, adopt ultrasonic cleaning method to clean specifically and comprise by cleaning fluid: to adopt cleaning fluid to clean removal and cover the second protective film 202 on residual part the first stress rete 301, and make the second stress rete 302 of overlap-add region form a cantilever beam structure, that is to say the removal that is etched of the second protective film 202 below the second stress rete 302 of overlap-add region in the process that cleaning fluid cleans, so the second stress rete 302 in overlap-add region forms a cantilever beam structure above overlap-add region, adopt ultrasonic method to make at cantilever beam structure the second stress rete 302 partly from fracture of root, so that the second stress rete 302 of overlap-add region is all removed, post-rift the second stress rete 302 and the first stress rete 301 be zero lap region in vertical direction, and there is a structure tilting to the first stress rete 301 in the part near the first stress rete 301.
Further, deposit one interlayer insulating medium layer 501, layer insulation dielectric layer 501 covers the top of the first residual stress rete 301 and residual the second stress rete 302;
Above shallow trench area 101, carry out etching, layer insulation dielectric layer 501, the first stress rete 301, the first protective film 201 that the lithographic method of employing different choice ratio is opened respectively overlap-add region top form the first through hole that terminates in polysilicon 102.
The first protective film 201 and the second protective film 202 in the present invention all form by deposit silicon dioxide protective film.
The first transistor in the present invention is NMOS pipe, transistor seconds is PMOS pipe, thereby the first stress rete 301 that can deposit produces tensile stress, etching is removed after the first stress rete 301 of part transistor seconds top, and the first stress rete 301 that remains in the first transistor top provides tensile stress to the first transistor; Deposit produces the second stress rete 302 of compression, etching is removed after the second stress rete 302 of part the first transistor top, the the second stress rete 302 that remains in transistor seconds top provides compression to transistor seconds, tensile stress film can effectively improve the performance of nmos device, and compressive stress film can effectively improve the performance of PMOS device.
Further, the silicon nitride film that deposit produces tensile stress forms the first stress rete 301, and the silicon nitride film that deposit produces compression forms the second stress rete 302.
Referring to Fig. 4 A ~ Fig. 4 C, the etching formation method of the first through hole 401 specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the first stress rete 301;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the first stress rete 301 and terminate in the first protective film 201;
Step c: adopt high silicon dioxide/silicon to select the lithographic method etching of ratio to open the first protective film 201 and terminate in polysilicon 102, form the first through hole 401.
In one embodiment of the invention; on substrate, be also formed with one first active area 103; the first protective film 301, the first stress rete 201 are covered the first active area 103, in the lithographic method etching that adopts different choice ratio forms the process of the first through hole 401, open successively respectively layer insulation dielectric layer 501, the first stress rete 301, the first protective film 201 simultaneously and form the second through hole 402 that terminates in the first active area 103.
Refer to Fig. 4 A ~ 4C, in etching the first through hole 401, etching forms the second through hole 402, the etching of the second through hole 402 is synchronizeed and is carried out with the etching of the first through hole 401, therefore the step of quoting in the second through hole 402 forming processes is the step adopting in the first through hole 401 forming processes, the etching formation method of the second through hole 402 specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the first stress rete 301, after that is to say completing steps a, the first through hole 401 of overlap-add region and the second through hole 402 of the first active area 103 all terminate in the first stress rete 301;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the first stress rete 301 and terminate in the first protective film 201, that is to say, after completing steps b, the first through hole 401 of overlap-add region and the second through hole 402 of the first active area 103 all terminate in the first protective film 301;
Step c: adopt high silicon dioxide/silicon to select the lithographic method etching of ratio to open the first protective film and terminate in the first active area 103, form the second through hole 402, after completing steps c, the first through hole 401 and the second through hole 402 complete simultaneously.
Further, in another embodiment of the present invention, because the formation technique of the second through hole on the formation technique of third through-hole on the second active area and the first active area is similar, those skilled in the art can make third through-hole according to the implementing process of the second through hole, therefore for mark not being carried out in the second active area and third through-hole in the accompanying drawings, on substrate, be also formed with one second active area, make the first protective film, the second protective film, the second stress rete covers the second active area, in forming the process of the first through hole, the lithographic method etching that adopts different choice ratio opens successively respectively layer insulation dielectric layer simultaneously, the second stress rete, the second protective film, the first protective film forms the third through-hole that terminates in the second active area.
When etching forms the first through hole, form third through-hole, therefore the step of quoting in third through-hole forming process is the step adopting in the first forming process of through hole, the etching formation method of third through-hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the second stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the second power rete and terminate in the second protective film;
Step c: employing high silicon dioxide/silicon selects the lithographic method etching of ratio to open the second protective film and the first protective film terminates in the second active area, forms third through-hole.
In sum; owing to having adopted technique scheme; the present invention improves dual via etch stop-layer crossover region etching method for forming through hole and has solved and in prior art, be formed on the problem that the through hole on overlapping region cannot be opened completely; the present invention is after dual via etch stop layer process completes; the hydrofluoric acid diluting by use also adopts ultrasonic cleaning method; remove upper strata silicon dioxide protective film and upper silicon nitride stress film, the technique effect that the through hole that adopts afterwards the lithographic method of different choice ratio to realize normal areas and overlapping region is opened simultaneously.
It should be appreciated by those skilled in the art that those skilled in the art can realize described variation example in conjunction with prior art and above-described embodiment, do not repeat them here.Such variation example does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (11)
1. improve a method for dual via etch stop-layer crossover region via etch, on a substrate, form at least one the first transistor and at least one transistor seconds, and form shallow trench area between the first transistor and transistor seconds; Deposit one deck the first protective film and one first stress rete successively on substrate, the first protective film and the first stress rete cover the first transistor, transistor seconds, shallow trench area simultaneously; Etching is removed the first stress rete that covers top, transistor seconds region, and the stress rete that part is covered on shallow trench area retains; Deposit one second protective film and one second stress rete, make the second protective film and the second stress rete cover the top of the first protective film of exposing and the first stress rete not being etched away successively, it is characterized in that, comprises the following steps:
Etching is removed the second stress rete that covers top, the first transistor region, reserve part is positioned at shallow trench area top and is positioned at the part second stress rete of the first stress rete top, make the first stress rete and the second stress rete there is a crossover region that is positioned at shallow trench area top, shallow trench area top is formed with polysilicon, makes overlapping region be positioned at the top of polysilicon region;
First use cleaning fluid to remove and cover the second protective film on residual part the first stress rete, then adopt ultrasonic cleaning method to remove the second stress rete of overlapping region;
Deposit one interlayer insulating medium layer, layer insulation dielectric layer covers the top of the first residual stress rete and residual the second stress rete;
Above shallow trench area, carry out etching, layer insulation dielectric layer, the first stress rete, the first protective film that the lithographic method of employing different choice ratio is opened respectively crossover region top form the first through hole that terminates in polysilicon;
Wherein, on substrate, be also formed with one first active area, the first protective film, the first stress rete are covered the first active area, in the lithographic method etching that adopts different choice ratio forms the process of the first through hole, open successively respectively layer insulation dielectric layer, the first stress rete, the first protective film simultaneously and form the second through hole that terminates in the first active area;
In addition; on substrate, be also formed with one second active area; the first protective film, the second protective film, the second stress rete are covered the second active area, in the lithographic method etching that adopts different choice ratio forms the process of the first through hole, open successively respectively layer insulation dielectric layer, the second stress rete, the second protective film, the first protective film simultaneously and form the third through-hole that terminates in the second active area.
2. the dual via etch stop-layer of improvement according to claim 1 crossover region etching method for forming through hole, is characterized in that, the first protective film and the second protective film all form by deposit silicon dioxide protective film.
3. the dual via etch stop-layer of improvement according to claim 1 crossover region etching method for forming through hole, is characterized in that, the first transistor is NMOS pipe, and transistor seconds is PMOS pipe.
4. the dual via etch stop-layer of improvement according to claim 3 crossover region etching method for forming through hole, it is characterized in that, deposit produces the first stress rete of tensile stress, etching is removed after the first stress rete of part transistor seconds top, and the first stress rete that remains in the first transistor top provides tensile stress to the first transistor; Deposit produces the second stress rete of compression, and etching is removed after the second stress rete of part the first transistor top, and the second stress rete that remains in transistor seconds top provides compression to transistor seconds.
5. the dual via etch stop-layer of improvement according to claim 4 crossover region etching method for forming through hole, it is characterized in that, the silicon nitride film that deposit produces tensile stress forms the first stress rete, and the silicon nitride film that deposit produces compression forms the second stress rete.
6. the dual via etch stop-layer of improvement according to claim 1 crossover region etching method for forming through hole, is characterized in that, adopts the hydrofluoric acid of dilution as cleaning fluid.
7. the dual via etch stop-layer of improvement according to claim 1 overlapping region etching method for forming through hole, is characterized in that, adopts ultrasonic cleaning method to clean by cleaning fluid.Specifically comprise: adopt cleaning fluid to clean removal and cover the second protective film on residual part the first stress rete; and make the second stress rete of crossover region form a cantilever beam structure; adopt ultrasonic method to make the second stress rete of cantilever beam structure part from fracture of root, so that the second stress rete of crossover region is all removed.
8. the dual via etch stop-layer of improvement according to claim 1 overlapping region etching method for forming through hole, is characterized in that, the width of overlapping region is greater than the diameter of through hole.
9. the dual via etch stop-layer of improvement according to claim 1 overlapping region etching method for forming through hole, is characterized in that, the etching formation method of the first through hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the first stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the first stress rete and terminate in the first protective film;
Step c: adopt high silicon dioxide/silicon to select the lithographic method etching of ratio to open the first protective film and terminate in polysilicon, form the first through hole.
10. the dual via etch stop-layer of improvement according to claim 1 overlapping region etching method for forming through hole, is characterized in that, the etching formation method of the second through hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the first stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the first stress rete and terminate in the first protective film;
Step c: adopt high silicon dioxide/silicon to select the lithographic method etching of ratio to open the first protective film and terminate in the first active area, form the second through hole.
The dual via etch stop-layer of 11. improvement according to claim 1 overlapping region etching method for forming through hole, is characterized in that, the etching formation method of third through-hole specifically comprises:
Step a: adopt dielectric between high level/silicon nitride to select the lithographic method etching of ratio to open layer insulation dielectric layer and terminate in the second stress rete;
Step b: adopt high silicon nitride/silicon dioxide to select the lithographic method etching of ratio to open the second power rete and terminate in the second protective film;
Step c: employing high silicon dioxide/silicon selects the lithographic method etching of ratio to open the second protective film and the first protective film terminates in the second active area, forms third through-hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110235219.6A CN102446819B (en) | 2011-08-17 | 2011-08-17 | Method used for improving dual contact-etch-stop-layer crossover region contact etch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110235219.6A CN102446819B (en) | 2011-08-17 | 2011-08-17 | Method used for improving dual contact-etch-stop-layer crossover region contact etch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102446819A CN102446819A (en) | 2012-05-09 |
| CN102446819B true CN102446819B (en) | 2014-03-12 |
Family
ID=46009200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110235219.6A Active CN102446819B (en) | 2011-08-17 | 2011-08-17 | Method used for improving dual contact-etch-stop-layer crossover region contact etch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102446819B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783585A (en) * | 2016-12-26 | 2017-05-31 | 苏州工业园区纳米产业技术研究院有限公司 | Lithographic method based on ledge structure |
| CN109904072B (en) * | 2017-12-07 | 2022-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521179A (en) * | 2008-02-26 | 2009-09-02 | 联发科技股份有限公司 | Dual contact etch stop layer process |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7816271B2 (en) * | 2007-07-14 | 2010-10-19 | Samsung Electronics Co., Ltd. | Methods for forming contacts for dual stress liner CMOS semiconductor devices |
| JP5521541B2 (en) * | 2009-12-25 | 2014-06-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
-
2011
- 2011-08-17 CN CN201110235219.6A patent/CN102446819B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101521179A (en) * | 2008-02-26 | 2009-09-02 | 联发科技股份有限公司 | Dual contact etch stop layer process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102446819A (en) | 2012-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102569050B (en) | Forming method of metal grid electrode | |
| CN103460358B (en) | Formed by replacement metal gate technique and be used for the boundless along contact of transistor | |
| US9130017B2 (en) | Methods for forming interconnect structures of integrated circuits | |
| CN102044426A (en) | Semiconductor device and manufacturing method thereof | |
| CN102468217B (en) | Method for forming contact hole | |
| CN105336688A (en) | Formation method of semiconductor structure | |
| CN101924110B (en) | SOI (Silicon On Insulator) transistor structure of body contact and preparation method thereof | |
| CN103227111B (en) | The manufacture method of semiconductor device | |
| CN102446819B (en) | Method used for improving dual contact-etch-stop-layer crossover region contact etch | |
| CN103545256B (en) | Form the method for cmos device | |
| CN102543840B (en) | Self-aligned contact etch method | |
| CN102110645A (en) | Cleaning method used after chemical mechanical polishing | |
| CN108878288A (en) | The manufacturing method of interlayer film | |
| CN104979173A (en) | Semiconductor structure and forming method thereof | |
| CN102437094B (en) | Method for improving etching of through holes in double-through-hole etching stop layer crossover region | |
| US20140353728A1 (en) | Method and apparatus for a reduced capacitance middle-of-the-line (mol) nitride stack | |
| CN102386138B (en) | Through hole etching method, integrated circuit manufacturing method and integrated circuit | |
| CN106229296A (en) | The forming method of metal level and tft array substrate in array base palte | |
| CN103137538B (en) | Si/NiSi2 backing material and preparation method thereof on a kind of pattern dielectric body | |
| CN202534635U (en) | Semiconductor device | |
| CN102437048B (en) | Method and device for improving etching of through holes in double-through-hole etching stop layer crossover region | |
| CN104124150A (en) | Method for forming semiconductor device | |
| CN111696867B (en) | Semiconductor structure and forming method | |
| CN103871857B (en) | The forming method of semiconductor devices | |
| CN102610569B (en) | Method for forming pre-metal dielectric layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |