CN102468217B - Method for forming contact hole - Google Patents
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- CN102468217B CN102468217B CN201010531245.9A CN201010531245A CN102468217B CN 102468217 B CN102468217 B CN 102468217B CN 201010531245 A CN201010531245 A CN 201010531245A CN 102468217 B CN102468217 B CN 102468217B
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Abstract
The invention discloses a method for forming a contact hole. The method comprises the following steps of: providing a semiconductor substrate, forming a metal oxide semiconductor (MOS) transistor on the semiconductor substrate, forming a first barrier layer and a dielectric layer sequentially, and covering the MOS transistor and the semiconductor substrate, wherein the etching selection ratio of the first barrier layer to the dielectric layer is more than or equal to 10; etching the dielectric layer, forming a first opening, a second opening and a third opening above a gate, a source and a drain of the MOS transistor respectively, wherein the first barrier layer is exposed out of the bottoms of the first opening, the second opening and the third opening; and removing the first barrier layer at the bottoms of the first opening, the second opening and the third opening. According to the method, the gate can be prevented from being damaged in the process of contact hole forming, and the performance of a device can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication, relate in particular to a kind of formation method of contact hole.
Background technology
In semiconductor fabrication, form MOS transistor on semiconductor base after, can form dielectric layer thereon to cover MOS transistor, and form opening by techniques such as etchings in dielectric layer above grid, source electrode and the drain electrode of MOS transistor, expose described grid, source electrode and drain electrode, described opening is called contact hole (Contact).In follow-up technique, in described contact hole, fill metal, as tungsten, form embolism (Plug), to realize the interconnection between MOS transistor and upper layer interconnects structure.
Fig. 1 to Fig. 3 shows the profile of intermediate structure corresponding to a kind of formation method of contact hole of prior art.
With reference to figure 1, semiconductor base 10 is provided, in described semiconductor base 10, be formed with MOS transistor, described MOS transistor comprises grid 11, source electrode 12 and drain electrode 13, be formed with barrier layer 14 and dielectric layer 15 successively on described semiconductor base 10.Described barrier layer 14 is different with the material of dielectric layer 15, general, and the material on described barrier layer 14 is silicon nitride, and the material of described dielectric layer 15 is silica.
With reference to figure 2, described dielectric layer 15 is carried out to etching, in the dielectric layer 15 above grid 11, source electrode 12 and drain electrode 13, form respectively the first opening 16, the second opening 17 and the 3rd opening 18.Described etching process can adopt dry etching, and main etching gas can be carbon hexa fluoride (C
4f
6), because dielectric layer 15 is different with the material on barrier layer 14, etching process stops on the surface on described barrier layer 14, makes the bottom-exposed of the first opening 16, the second opening 17 and the 3rd opening 18 go out described barrier layer 14.
With reference to figure 3, remove the barrier layer 14 of described the first opening 16, the second opening 17 and the 3rd opening 18 bottoms, expose described grid 11, source electrode 12 and drain electrode 13, thereby complete the forming process of contact hole.The removal method on described barrier layer 14 can be dry etching, and etching gas can mainly comprise carbon tetrafluoride (CF
4).
Still with reference to figure 2, because the grid 11 of MOS transistor is higher than source electrode 12 and drain electrode 13, make dielectric layer 15 after the planarization thickness above the thickness above grid 11 is less than source electrode 12 and drain electrode 13.Therefore, in to the etching process of dielectric layer 15, in order to carve the dielectric layer 15 of wearing source electrode 12 and drain electrode 13 tops, can cause quarter to the barrier layer 14 of grid 11 tops, make the thickness on the barrier layer 14 of the first opening 16 bottoms be less than the thickness on the barrier layer 14 of the second opening 17 and the 3rd opening 18 bottoms.
Continue with reference to figure 3, because the thickness on the barrier layer 14 of the first opening 16 bottoms is less, therefore, remove in the technical process on barrier layer 14 of each open bottom in etching, can produce quarter to grid 11, thus grid 11 is caused to damage, affect the contact resistance between the embolism of itself and follow-up formation.Especially, in prior art in order to reduce contact resistance, after forming MOS transistor, also form self aligned metal silicide (Silicide) at the top of grid 11, source electrode 12 and drain electrode 13, as nickle silicide (NiSi) etc., crossing of grid 11 carved and can be damaged its surperficial metal silicide, increase the contact resistance between grid 11 and embolism, affect device performance.
About more detailed contents of contact hole, refer to the patent No. and be 7,541,271 United States Patent (USP).
Summary of the invention
The problem that the present invention solves is in the forming process of contact hole, grid to be caused the problem of damage, to improve device performance.
For addressing the above problem, the invention provides a kind of formation method of contact hole, comprising:
Semiconductor base is provided, on described semiconductor base, is formed with MOS transistor;
Form successively the first barrier layer and dielectric layer, cover described MOS transistor and semiconductor base, the etching selection ratio of described the first barrier layer and described dielectric layer is more than or equal to 10;
Described dielectric layer is carried out to etching, form respectively the first opening, the second opening and the 3rd opening above grid, source electrode and the drain electrode of described MOS transistor, the bottom-exposed of described the first opening, the second opening and the 3rd opening goes out described the first barrier layer;
Remove the first barrier layer of described the first opening, the second opening and the 3rd open bottom.
Optionally, before forming described the first barrier layer, also comprise: form the second barrier layer, cover described MOS transistor and semiconductor base; After removing the first barrier layer of described the first opening, the second opening and the 3rd open bottom, also comprise: remove the second barrier layer of described the first opening, the second opening and the 3rd open bottom, expose respectively described grid, source electrode and drain electrode.
Optionally, the material on described the second barrier layer is silicon nitride.
Optionally, the material on described the first barrier layer is can ashing (ashable) material.
Optionally, the material on described the first barrier layer is amorphous carbon, and the material of described dielectric layer is silica.
Optionally, the first barrier layer that uses ashing method to remove described the first opening, the second opening and the 3rd open bottom.
Optionally, the plasma that the reacting gas of described ashing method use is oxygen or oxygen.
Optionally, use dry etching to carry out etching to described dielectric layer, etching gas comprises C
4f
6.
Optionally, the thickness on described the first barrier layer is 100
to 200
Compared with prior art, the present invention has the following advantages:
The technical program forms successively the first barrier layer and dielectric layer on semiconductor base, cover MOS transistor and semiconductor base, and the etching selection ratio of the first barrier layer and dielectric layer is more than or equal to 10, etching is carried out on dielectric layer and first barrier layer of the grid to MOS transistor, source electrode and drain electrode top respectively more afterwards, forms contact hole.Because the etching selection of the first barrier layer and dielectric layer is larger, thereby in the process of etching dielectric layer, the crossing of the first barrier layer having effectively reduced grid top carved, thereby while having effectively reduced etching the first barrier layer, crossing of grid carved and damage, be conducive to reduce the contact resistance between grid and embolism, improve the performance of device.
Further, the material on the first barrier layer that the technical program is selected, for can grey formed material, can be removed by ashing method, has further reduced crossing of grid carved and damage.
Brief description of the drawings
Fig. 1 to Fig. 3 is the profile of the intermediate structure of the formation method of prior art contact hole;
Fig. 4 is the schematic flow sheet of the formation method of the contact hole of the embodiment of the present invention;
Fig. 5 to Fig. 8 is the profile of the intermediate structure of the formation method of the contact hole of first embodiment of the invention;
Fig. 9 to Figure 13 is the profile of the intermediate structure of the formation method of the contact hole of second embodiment of the invention.
Embodiment
Prior art is in the process of formation contact hole, because the thickness of the dielectric layer above grid is less, be less than the thickness of the dielectric layer of source electrode and drain electrode top, the barrier layer of grid top is carved excessively, because the material on barrier layer of the prior art is generally silicon nitride, the material of dielectric layer is generally silica, its etching selection ratio is about 5, the barrier layer of grid top is carved excessively, thickness is obviously less than normal, and then remove in the process on barrier layer in etching, cause crossing of grid to carve and damage, increase the contact resistance between grid and embolism, affect device performance.
The technical program forms successively the first barrier layer and dielectric layer on semiconductor base, cover MOS transistor and semiconductor base, and the etching selection ratio of the first barrier layer and dielectric layer is more than or equal to 10, etching is carried out on dielectric layer and first barrier layer of the grid to MOS transistor, source electrode and drain electrode top respectively more afterwards, forms contact hole.Because the etching selection of the first barrier layer and dielectric layer is larger, thereby in the process of etching dielectric layer, the crossing of the first barrier layer having effectively reduced grid top carved, thereby while having effectively reduced etching the first barrier layer, crossing of grid carved and damage, be conducive to reduce the contact resistance between grid and embolism, improve the performance of device.
Further, the material on the first barrier layer that the technical program is selected, for can grey formed material, can be removed by ashing method, has further reduced crossing of grid carved and damage.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public embodiment.
Fig. 4 shows the schematic flow sheet of the formation method of the contact hole of the embodiment of the present invention, comprising:
Step S21, provides semiconductor base, on described semiconductor base, is formed with MOS transistor;
Step S22, forms the first barrier layer and dielectric layer successively, covers described MOS transistor and semiconductor base, and the etching selection ratio of described the first barrier layer and described dielectric layer is more than or equal to 10;
Step S23, described dielectric layer is carried out to etching, above grid, source electrode and the drain electrode of described MOS transistor, form respectively the first opening, the second opening and the 3rd opening, the bottom-exposed of described the first opening, the second opening and the 3rd opening goes out described the first barrier layer;
Step S24, first barrier layer of removing described the first opening, the second opening and the 3rd open bottom.
Fig. 5 to Fig. 8 shows the profile of the intermediate structure of the formation method of the contact hole of first embodiment of the invention, below in conjunction with Fig. 4 and Fig. 5 to Fig. 8, first embodiment of the invention is elaborated.
In conjunction with Fig. 4 and Fig. 8, execution step S21, provides semiconductor base, on described semiconductor base, is formed with MOS transistor.Concrete, semiconductor base 20 is provided, on described semiconductor base 20, be formed with MOS transistor.Described semiconductor base 20 can be monocrystalline silicon, can be also silicon Germanium compound, can also be epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or silicon.Described MOS transistor can be PMOS transistor or nmos pass transistor, comprise grid 21 and be formed on source electrode 22 and the drain electrode 23 in the semiconductor base 20 of grid 21 both sides, described grid 21 comprises gate dielectric layer and the gate electrode (not shown) being located thereon.In the present embodiment, the material of described gate electrode is polysilicon, on the surface of described gate electrode, is formed with metal silicide, is specially nickle silicide, similarly, on the surface of described source electrode 22 and drain electrode 23, is also formed with metal silicide.
In conjunction with Fig. 4 and Fig. 6, execution step S22, forms the first barrier layer and dielectric layer successively, covers described MOS transistor and semiconductor base, and the etching selection ratio of described the first barrier layer and described dielectric layer is more than or equal to 10.Concrete, forming successively the first barrier layer 24 and dielectric layer 25, the etching selection ratio between described the first barrier layer 24 and dielectric layer 25 is more than or equal to 10.The material of described dielectric layer 25 can be silica, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass etc., and its formation method can be chemical vapour deposition (CVD) (CVD), after forming, it is carried out to planarization, makes its surfacing.The material on described the first barrier layer 24 can be determined according to the material of described dielectric layer 25, ensures that the etching selection ratio between the two is more than or equal to 10.In the present embodiment, the material of described dielectric layer 25 is silica, and the material on described the first barrier layer 24 is preferably amorphous carbon that can ashing, and the thickness on described the first barrier layer is 100
to 200
its formation method is chemical vapour deposition (CVD).
In conjunction with Fig. 4 and Fig. 7, execution step S23, described dielectric layer is carried out to etching, above grid, source electrode and the drain electrode of described MOS transistor, form respectively the first opening, the second opening and the 3rd opening, the bottom-exposed of described the first opening, the second opening and the 3rd opening goes out described the first barrier layer.Concrete, described dielectric layer 25 is carried out to etching, above grid 21, source electrode 22 and the drain electrode 23 of described MOS transistor, form respectively the first opening 26, the second opening 27 and the 3rd opening 28, the bottom-exposed of described the first opening 26, the second opening 27 and the 3rd opening 28 goes out described the first barrier layer 24.The lithographic method of described dielectric layer 25 comprises: on the surface of described dielectric layer 25, form photoresist layer graphical, define the figure of described the first opening 26, the second opening 27 and the 3rd opening 28; Taking described photoresist layer after graphical as mask carries out dry etching, form described the first opening 26, the second opening 27 and the 3rd opening 28.Etching gas in described dry etching is mainly C
4f
6.
In to the etching process of dielectric layer 25, although the thickness of the dielectric layer 25 of grid 21 tops is less, be less than the thickness of the dielectric layer 25 of source electrode 22 and drain electrode 23 tops, but because the etching selection ratio of the first barrier layer 24 and dielectric layer 25 is more than or equal to 10, therefore make etching process stop on described the first barrier layer 24, crossing of effectively having reduced the first barrier layer 24 of grid 21 tops to cause carved.
In conjunction with Fig. 4 and Fig. 8, execution step S24, first barrier layer of removing described the first opening, the second opening and the 3rd open bottom.Concrete, remove the first barrier layer 24 of described the first opening 26, the second opening 27 and the 3rd opening 28 bottoms, expose respectively described grid 21, source electrode 22 and drain electrode 23.The removal method on described the first barrier layer 24 can be dry etching, because the thickness on the first barrier layer 24 of grid 21, source electrode 22 and drain electrode 23 tops is basically identical, therefore can the first barrier layer 24 of described grid 21, source electrode 22 and drain electrode 23 tops be removed by controlling etch rate and etch period, and effectively reduce, crossing of grid 21 carved, avoid its lip-deep metal silicide to cause damage, be beneficial to the contact resistance reducing between grid 21 and embolism, improve device performance.
In the present embodiment, the material on described the first barrier layer 24 is preferably material that can ashing, is specially amorphous carbon, therefore, can its ashing be removed by ashing method, and the reacting gas in podzolic process is preferably the plasma of oxygen or oxygen.Further preferred, after step S23 process, be that etching dielectric layer 25 forms after described the first opening 26, the second opening 27, the 3rd opening 28, in using ashing method ashing to remove photoresist layer, by described the first opening 26, the second opening 27 and the 3rd opening 28 bottoms can grey formed material the first barrier layer 24 ashing simultaneously remove, further simplify processing step.And cineration technics do not relate to the ion bombardment process in etching technics, also can avoid the damage to grid 21, source electrode 22 and drain electrode 23, be beneficial to and improve device performance.
Fig. 9 to Figure 13 shows the profile of the intermediate structure of the formation method of the contact hole of second embodiment of the invention, below in conjunction with Fig. 9 to Figure 13, the second embodiment of the present invention is elaborated.
With reference to figure 9, semiconductor base 30 is provided, on described semiconductor base 30, be formed with MOS transistor.The material of described semiconductor base 30 please refer to the first embodiment, and described MOS transistor comprises grid 31, and is formed on source electrode 32 and drain electrode 33 in the semiconductor base 30 of described grid 31 both sides.On the surface of described grid 31, source electrode 32 and drain electrode 33, be all formed with metal silicide.
With reference to Figure 10, form successively the second barrier layer 34, the first barrier layer 35 and dielectric layer 36, cover the surface of described MOS transistor and semiconductor base 30, the etching selection ratio of described the first barrier layer 35 and dielectric layer 36 is more than or equal to 10.In the present embodiment, the material on described the second barrier layer 34 is silicon nitride, and its formation method is chemical vapour deposition (CVD); The material on described the first barrier layer 35 is amorphous carbon, and formation method is chemical vapour deposition (CVD), and thickness is 100
to 200
the material of described dielectric layer 36 is silica, and formation method is chemical vapour deposition (CVD).
With reference to Figure 11, described dielectric layer 36 is carried out to etching, above described grid 31, source electrode 32 and drain electrode 33, form respectively the first opening 37, the second opening 38 and the 3rd opening 39, bottom-exposed goes out described the first barrier layer 35.The lithographic method of dielectric layer 36 described in the present embodiment can be dry etching, and etching gas mainly comprises C
4f
6.Etching process mainly comprises: on the surface of described dielectric layer 36, form photoresist layer graphical, define the figure of described the first opening 37, the second opening 38 and the 3rd opening 39; Taking described photoresist layer after graphical as mask carries out dry etching, form described the first opening 37, the second opening 38 and the 3rd opening 39.Because the etching selection ratio of the first barrier layer 35 and dielectric layer 36 is more than or equal to 10, therefore make etching process stop on described the first barrier layer 35, crossing of effectively having reduced the first barrier layer 35 of grid 31 tops to cause carved.
With reference to Figure 12, remove the first barrier layer 35 of described the first opening 37, the second opening 38 and the 3rd opening 39 bottoms, expose the second barrier layer 34.In the present embodiment, described the first barrier layer 35 is can grey formed material, is specially amorphous carbon, and its removal process can adopt ashing method, and reacting gas is the plasma of oxygen or oxygen.Preferably, after etching dielectric layer 36 forms described the first opening 37, the second opening 38 and the 3rd opening 39, when described photoresist layer is removed in ashing, the first barrier layer 35 of the first opening 37, the second opening 38 and the 3rd opening 39 bottoms in the lump ashing is removed, simplify processing step.In podzolic process, can't cause damage to the second barrier layer 34 of below, make the thickness on the second barrier layer 34 of grid 31, source electrode 32 and drain electrode 33 tops keep uniformity.
With reference to Figure 13, remove the second barrier layer 34 of described the first opening 37, the second opening 38 and the 3rd opening 39 bottoms, expose respectively described grid 31, source electrode 32 and drain electrode 33.Removal method can be dry etching, and etching gas mainly comprises CF4.Due to the consistency of thickness on the second barrier layer 34 of described grid 31, source electrode 32 and drain electrode 33 tops, therefore can the second barrier layer 34 of described the first opening 37, the second opening 38 and the 3rd opening 39 bottoms be removed in the lump by controlling etch rate and etch period, and can not cause damage to grid 31.
It should be noted that, in above-mentioned the second embodiment, because MOS transistor top is formed with the second barrier layer 34, therefore, when the first barrier layer 35 above grid 31, source electrode 32 and drain electrode 33 are removed in ashing, podzolic process can't directly impact grid 31, source electrode 32 and drain electrode 33, has avoided the oxidation of podzolic process to grid 31, source electrode 32 and drain electrode 33 and lip-deep metal silicide thereof, be conducive to reduce contact resistance, improve device performance.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (7)
1. a formation method for contact hole, is characterized in that, comprising:
Semiconductor base is provided, on described semiconductor base, is formed with MOS transistor;
Form successively the second barrier layer, the first barrier layer and dielectric layer, cover described MOS transistor and semiconductor base, the etching selection ratio of described the first barrier layer and described dielectric layer is more than or equal to 10;
On described dielectric layer, form photoresist layer and carry out graphically, the photoresist layer after graphical defines the figure of the first opening, the second opening and the 3rd opening;
Taking the photoresist layer after graphical as mask, described dielectric layer is carried out to etching, above grid, source electrode and the drain electrode of described MOS transistor, form respectively the first opening, the second opening and the 3rd opening, the bottom-exposed of described the first opening, the second opening and the 3rd opening goes out described the first barrier layer;
Use ashing method to remove described photoresist layer after graphical, in the time that described photoresist layer after graphical is removed in ashing, the first barrier layer that also described the first opening, the second opening and the 3rd open bottom are removed in ashing;
The second barrier layer that uses dry etching to remove described the first opening, the second opening and the 3rd open bottom, exposes respectively described grid, source electrode and drain electrode.
2. the formation method of contact hole according to claim 1, is characterized in that, the material on described the second barrier layer is silicon nitride.
3. the formation method of contact hole according to claim 1, is characterized in that, the material on described the first barrier layer is can grey formed material.
4. the formation method of contact hole according to claim 3, is characterized in that, the material on described the first barrier layer is amorphous carbon, and the material of described dielectric layer is silica.
5. the formation method of contact hole according to claim 1, is characterized in that, the plasma that the reacting gas that described ashing method uses is oxygen or oxygen.
6. the formation method of contact hole according to claim 4, is characterized in that, uses dry etching to carry out etching to described dielectric layer, and etching gas comprises C
4f
6.
7. the formation method of contact hole according to claim 1, is characterized in that, the thickness on described the first barrier layer is
extremely
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| CN103560137A (en) * | 2013-11-13 | 2014-02-05 | 上海华力微电子有限公司 | CMOS complementary metal oxide semiconductor contact hole etching method and CMOS complementary metal oxide semiconductor manufacturing method |
| CN104900520B (en) * | 2014-03-04 | 2018-02-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN105097430B (en) * | 2014-05-05 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN105092104B (en) * | 2014-05-14 | 2018-09-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of pressure sensor and preparation method thereof, electronic device |
| CN105439077A (en) * | 2014-06-18 | 2016-03-30 | 上海丽恒光微电子科技有限公司 | Preparation method of pressure sensor |
| CN105203235B (en) * | 2014-06-19 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method and electronic device of a kind of MEMS pressure sensor |
| CN113903660B (en) * | 2021-09-30 | 2022-08-19 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| CN116031205B (en) * | 2023-03-30 | 2023-06-30 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
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| US6884736B2 (en) * | 2002-10-07 | 2005-04-26 | Taiwan Semiconductor Manufacturing Co, Ltd. | Method of forming contact plug on silicide structure |
| US20050284573A1 (en) * | 2004-06-24 | 2005-12-29 | Egley Fred D | Bare aluminum baffles for resist stripping chambers |
| US7384799B2 (en) * | 2005-01-26 | 2008-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to avoid amorphous-si damage during wet stripping processes in the manufacture of MEMS devices |
| US7371634B2 (en) * | 2005-01-31 | 2008-05-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Amorphous carbon contact film for contact hole etch process |
| KR100739975B1 (en) * | 2005-12-20 | 2007-07-16 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| US7737036B2 (en) * | 2007-08-09 | 2010-06-15 | Applied Materials, Inc. | Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation |
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