US9236312B2 - Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device - Google Patents
Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device Download PDFInfo
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- US9236312B2 US9236312B2 US14/053,088 US201314053088A US9236312B2 US 9236312 B2 US9236312 B2 US 9236312B2 US 201314053088 A US201314053088 A US 201314053088A US 9236312 B2 US9236312 B2 US 9236312B2
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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Definitions
- This invention relates generally to the field of semiconductors, and more particularly, to forming a nitride spacer to protect a FinFET device.
- a typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits.
- FETs field effect transistors
- CMOS complementary insulated gate FET process
- layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer.
- SOI silicon on insulator
- a simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer.
- Each of these layers of shapes also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing, and level definition (e.g., etching, implanting, deposition, etc.).
- the FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off.
- DIBL drain-induced barrier lowering
- approaches for forming an oxide cap to protect a semiconductor device are provided.
- a semiconductor device e.g., a fin field effect transistor device (FinFET)
- approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing.
- the oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash).
- the oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.
- One aspect of the present invention includes a method for forming a device, the method comprising: forming a set of gate structures over a finned substrate, each of the set of gate structures comprising a nitride capping layer; forming a set of raised source drain (RSD) structures on the finned substrate; forming an oxide cap over a subset of the RSD structures; and removing the nitride capping layer.
- a method for forming a device comprising: forming a set of gate structures over a finned substrate, each of the set of gate structures comprising a nitride capping layer; forming a set of raised source drain (RSD) structures on the finned substrate; forming an oxide cap over a subset of the RSD structures; and removing the nitride capping layer.
- RSD raised source drain
- Another aspect of the present invention includes a method for forming an oxide cap to protect a fin-shaped field effect transistor (FinFET) device, the method comprising: forming a set of gate structures over a finned substrate, each of the set of gate structures comprising a nitride capping layer; forming a set of raised source drain (RSD) structures on the finned substrate; forming a silicate over a subset of the RSD structures; oxidizing the silicate to form the oxide cap; and removing the nitride capping layer.
- FinFET fin-shaped field effect transistor
- Yet another aspect of the present invention includes a fin-shaped field effect transistor (FinFET) device, formed via a process, comprising: forming a set of fins from a substrate to get a finned substrate; forming a set of gate structures over the finned substrate, each of the set of gate structures comprising a nitride capping layer; growing a set of epitaxial phosphorus-doped Si (SiP) regions over a subset of the set of gate structures; growing a silicate on the SiP regions; oxidizing the silicate using a plasma oxidation process to form an oxide cap; removing the nitride capping layer via a hot phosphorus rinse, wherein the oxide cap prevents damage to the SiP regions from the hot phosphorus rinse; and removing the oxide cap from the SiP regions.
- FinFET fin-shaped field effect transistor
- FIG. 1 shows a FinFET semiconductor device according to an embodiment of the present invention
- FIG. 2 shows a “dummy” gate formation according to an embodiment of the present invention
- FIG. 3 shows a spacer formation according to an embodiment of the present invention
- FIG. 4 shows a nitride cap formation according to an embodiment of the present invention
- FIG. 5 shows a formation of raise source drain (RSD) structures according to an embodiment of the present invention
- FIG. 6 shows RSD structures having SiP and SiGe regions according to an embodiment of the present invention
- FIG. 7 shows a formation of a silicate on the SiP regions according to an embodiment of the present invention.
- FIG. 8 shows an oxidizing of the silicate to form an oxide cap according to an embodiment of the present invention.
- FIG. 9 shows a removal of a nitride capping layer according an embodiment of the present invention.
- approaches for forming an oxide cap to protect a semiconductor device e.g., a fin field effect transistor device (FinFET)
- a semiconductor device e.g., a fin field effect transistor device (FinFET)
- approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing.
- the oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash).
- the oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.
- first element such as a first structure, e.g., a first layer
- second element such as a second structure, e.g. a second layer
- intervening elements such as an interface structure, e.g. interface layer
- depositing may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
- CVD chemical vapor deposition
- LPCVD low-pressure CVD
- PECVD plasma-enhanced CVD
- SACVD semi-
- the device 10 can be formed on a substrate 12 by forming a set of fins 14 from the substrate.
- device 10 generally comprises a uniform, oxide-fin surface having a fin region 14 and an oxide fill 16 .
- the oxide-fin surface is formed by polishing (e.g., via CMP) oxide fill 16 to a top surface of fin region 14 . This results in a substantially “planar” or “uniform” surface.
- a dummy gate 20 formation process is commenced.
- a gate material 22 and a hard mask layer 24 are positioned on the surface (collectively referred to as a gate structure or “dummy” gate 20 ).
- a set of spacers 26 are added to opposing sides of the gate structure.
- substrate 12 as used herein is intended to include a semiconductor substrate, a semiconductor epitaxial layer deposited or otherwise formed on a semiconductor substrate and/or any other type of semiconductor body, and all such structures are contemplated as falling within the scope of the present invention.
- the semiconductor substrate 12 may comprise a semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith.
- a portion or entire semiconductor substrate 12 may be amorphous, polycrystalline, or single-crystalline.
- the semiconductor substrate 12 employed in the present invention may also comprise a hybrid oriented (HOT) semiconductor substrate in which the HOT substrate has surface regions of different crystallographic orientation.
- the semiconductor substrate 12 may be doped, undoped or contain doped regions and undoped regions therein.
- the semiconductor substrate 12 may contain regions with strain and regions without strain therein, or contain regions of tensile strain and compressive strain.
- Gate structures 20 may be fabricated using any suitable process including one or more photolithography and etch processes.
- the photolithography process may include forming a photoresist layer (not shown) overlying substrate 12 (e.g., on a silicon layer), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist.
- the masking element may then be used to etch each gate 20 into the silicon layer, e.g., using reactive ion etch (RIE) and/or other suitable processes.
- RIE reactive ion etch
- gate structures 20 are formed by a double-patterning lithography (DPL) process.
- DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density.
- gate structures 20 each include a gate electrode. Numerous other layers may also be present, for example, a gate dielectric layer, interface layers, and/or other suitable features.
- the gate dielectric layer may include dielectric material such as, silicon oxide, silicon nitride, silicon oxinitride, dielectric with a high dielectric constant (high k), and/or combinations thereof.
- high k materials include hafnium silicate, hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy, and/or combinations thereof.
- the gate dielectric layer may be formed using processes such as, photolithography patterning, oxidation, deposition, etching, and/or other suitable processes.
- the gate electrode may include polysilicon, silicon-germanium, a metal including metal compounds such as, Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, and/or other suitable conductive materials known in the art.
- the gate electrode may be formed using processes such as, physical vapor deposition (PVD), CVD, plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes which may be followed, for example, by photolithography and/or etching processes.
- PVD physical vapor deposition
- CVD plasma-enhanced chemical vapor deposition
- PECVD atmospheric pressure chemical vapor deposition
- LPCVD low-pressure CVD
- HD CVD high density plasma CVD
- ACVD atomic layer CVD
- device 10 further comprises a nitride cap (e.g., SiN) 28 formed over gate region 20 .
- nitride cap 28 can be formed from silicon by thermal or plasma conversion of silicon into nitride, i.e., by thermal nitridation or by plasma nitridation of silicon.
- nitride cap 28 can be formed by deposition of silicon nitride, for example, by chemical vapor deposition (CVD), or by plasma oxidation.
- CVD chemical vapor deposition
- RSD raised source drain
- an RSD structure 30 can be formed on each fin 14 of FinFET device 10 .
- RSD structure 30 can be grown as an epitaxial structure or can be formed in any way now known or later developed. Further, RSD structure 30 can be formed using any material now known nor later developed for use as a source and/or drain.
- FinFET device 10 having a set of RSD structures 30 is shown. As illustrated, a subset of the fins 14 have been formed into a set of NFET regions 32 . Similarly, a subset of the fins 14 (e.g., a remainder of some or all fins that were not formed into the set of NFET regions 32 ) have been formed a set of PFET regions 34 . A set of phosphorus-doped Si (SiP) regions 36 of RSD structures 30 has been formed in NFET regions 32 . Similarly, a set of silicon germanium (SiGe) regions 38 of RSD structures 30 have been formed in PFET region 34 .
- SiP phosphorus-doped Si
- SiGe silicon germanium
- nitride capping layer 28 may have certain disadvantages. For example, as shown in FIG. 6 , nitride capping layer 28 and/or spacers 26 may have certain irregularities, such as elevated region 40 . Such irregularities can lead to portions of nitride capping layer 28 and/or spacers 26 being removed prior to other portions, leading to bleed-through of the substance (e.g., hot phosphorus wash) used to perform the removal. This bleed-through can cause damage to certain of RSD structures 30 , in particular SiP regions.
- the substance e.g., hot phosphorus wash
- an oxide cap can be formed over a subset of RSD structures 30 (e.g., SiP regions 36 ).
- a silicate 42 can be grown on SiP regions 36 , e.g., using an epitaxial method, or the like. Note that silicate 42 that is grown on SiP regions 36 is not present on SiGe regions 38 due to the fact that the SiGe regions 38 are covered with nitride capping layer 28 . In any case, silicate 42 can be oxidized to form oxide cap 44 .
- this oxidizing can include a thermal oxidation process with conventional furnace oxide process, an in situ steam generation (ISSG) or other rapid thermal oxidation technique, a plasma oxidation process and/or any other process that is now known or later developed for oxidizing a Si deposition (e.g., converting silicon (S) to silicon oxide SiO2).
- ISSG in situ steam generation
- plasma oxidation process e.g., converting silicon (S) to silicon oxide SiO2
- oxide cap 44 When, as shown in FIG. 9 , nitride capping layer 28 and/or spacers 26 are removed (e.g., using a hot phosphorus wash), oxide cap 44 will protect the RSD structures 30 (e.g., SiP regions 36 ) upon which the oxide cap 44 was formed. Oxide cap 44 can then be removed from the RSD structures 30 and subsequent formation (e.g., of gates, contacts, etc.) can be resumed.
- design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein, including a set of gate structures formed over a fined substrate, each of the set of gate structures comprising a nitride capping layer, RSD structures formed on the finned substrate, and an oxide cap formed over a subset of the RSD structures.
- Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof.
- a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof.
- a tool can be a computing device or other appliance on which software runs or in which hardware is implemented.
- a module might be implemented utilizing any form of hardware, software, or a combination thereof.
- processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module.
- the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules.
- the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations.
Abstract
Description
Claims (17)
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US14/053,088 US9236312B2 (en) | 2013-10-14 | 2013-10-14 | Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device |
US14/961,566 US20160086952A1 (en) | 2013-10-14 | 2015-12-07 | Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device |
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US14/053,088 US9236312B2 (en) | 2013-10-14 | 2013-10-14 | Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device |
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US9679978B2 (en) | 2015-09-24 | 2017-06-13 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
US9496371B1 (en) | 2015-10-07 | 2016-11-15 | International Business Machines Corporation | Channel protection during fin fabrication |
US9812453B1 (en) * | 2017-02-13 | 2017-11-07 | Globalfoundries Inc. | Self-aligned sacrificial epitaxial capping for trench silicide |
US11101356B2 (en) | 2017-09-29 | 2021-08-24 | Intel Corporation | Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors |
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US20150102414A1 (en) | 2015-04-16 |
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