US20160035728A1 - Retrograde doped layer for device isolation - Google Patents

Retrograde doped layer for device isolation Download PDF

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US20160035728A1
US20160035728A1 US14/882,308 US201514882308A US2016035728A1 US 20160035728 A1 US20160035728 A1 US 20160035728A1 US 201514882308 A US201514882308 A US 201514882308A US 2016035728 A1 US2016035728 A1 US 2016035728A1
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retrograde
doped layer
high mobility
mobility channel
substrate
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US14/882,308
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Ajey Poovannummoottil Jacob
Steven John Bentley
Murat Kerem Akarvardar
Jody Alan Fronheiser
Kangguo Cheng
Bruce B. Doris
Ali Khakifirooz
Toshiharu NAGUMO
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GlobalFoundries Inc
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GlobalFoundries Inc
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Priority to US14/882,308 priority Critical patent/US20160035728A1/en
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BENTLEY, STEVEN JOHN, AKARVARDAR, MURAT KEREM, CHENG, KANGGUO, DORIS, BRUCE B., NAGUMO, TOSHIHARU, JACOB, AJEY POOVANNUMMOOTTIL, KHAKIFIROOZ, ALI, FRONHEISER, JODY ALAN
Publication of US20160035728A1 publication Critical patent/US20160035728A1/en
Assigned to GLOBALFOUNDRIES U.S. INC. reassignment GLOBALFOUNDRIES U.S. INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor

Definitions

  • This invention relates generally to the field of semiconductors, and more particularly, to approaches used to form a complementary metal-oxide field effect transistor.
  • a typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FINFETs)) and connect the devices into circuits.
  • devices e.g., fin field effect transistors (FINFETs)
  • CMOS complementary insulated gate FINFET process
  • layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer.
  • SOI silicon on insulator
  • a simple FINFET is formed by the intersection of two shapes, i.e., a gate layer rectangle on a silicon island formed from the silicon surface layer.
  • Each of these layers of shapes also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching,
  • Silicon based FinFETs have been successfully fabricated using conventional MOSFET technology.
  • a typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate.
  • the channel of the FET is formed in this vertical fin.
  • a gate is provided over the fin(s).
  • a double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow.
  • Other FinFET architectures may include three or more effective gates.
  • Germanium based devices include a fin formed at least in part, of germanium (as opposed to silicon fin).
  • Typical Ge-FinFET fabrication includes patterning a germanium layer on a substrate to form a narrow Ge-fin.
  • high mobility channel materials like Ge have aggravated junction leakage if the device interface is not properly engineered.
  • the bulk FinFET suffers from punch-through leakage along the fin channel, which significantly contributes to overall device leakage.
  • prior art device 10 is highly susceptible to damage during punch-through implant, and suffers from carrier spill-out to the undoped fin channel, which lowers the carrier mobility. Accordingly, what is needed is a solution to at least one of these deficiencies.
  • CMOS complimentary metal-oxide-semiconductor
  • finFET fin field effect transistor
  • a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage.
  • a set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., Si or silicon-germanium).
  • the retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant.
  • the device may further include a carbon liner formed over the retrograde doped layer to prevent carrier spill-out to the high mobility channel fins.
  • One aspect of the present invention includes a method for forming a device, the method comprising: forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); forming a set of high mobility channel fins over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and forming a set of silicon fins adjacent the set of high mobility channel fins.
  • Another aspect of the present invention includes a method for providing device isolation in a complementary metal-oxide-semiconductor fin field effect transistor, the method comprising: forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); forming a set of high mobility channel fins over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and forming a set of silicon fins adjacent the set of high mobility channel fins.
  • a retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge)
  • Si—Ge doped silicon-germanium
  • Another aspect of the present invention includes a semiconductor device comprising: a retrograde doped layer formed over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); a set of high mobility channel fins formed over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and a set of silicon fins formed adjacent the set of high mobility channel fins.
  • a semiconductor device comprising: a retrograde doped layer formed over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); a set of high mobility channel fins formed over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and a set of silicon fins formed adjacent the set of high mobility channel fins.
  • FIG. 1 shows a cross-sectional view of a prior art semiconductor device
  • FIG. 2 shows a cross-sectional view of an opening formed in a substrate according to illustrative embodiments
  • FIG. 3 shows a cross-sectional view of formation of a retrograde doped layer in the opening formed in the substrate according to illustrative embodiments
  • FIG. 4 shows a cross-sectional view of formation of a carbon liner over the retrograde doped layer according to illustrative embodiments
  • FIG. 5 shows a cross-sectional view of formation of a high mobility channel material according to illustrative embodiments
  • FIG. 6 shows a cross-sectional view of removal of a hardmask according to illustrative embodiments
  • FIG. 7 shows a cross-sectional view of a set of high mobility channel fins formed over the retrograde doped layer and the carbon liner according to illustrative embodiments
  • FIG. 8 shows a cross-sectional view of an opening formed in the substrate according to illustrative embodiments
  • FIG. 9 shows a cross-sectional view of formation of a high mobility channel material according to illustrative embodiments
  • FIG. 10 shows a cross-sectional view of formation of a retrograde doped layer according to illustrative embodiments
  • FIG. 11 shows a cross-sectional view of formation of a carbon liner according to illustrative embodiments
  • FIG. 12 shows a cross-sectional view of formation of a retrograde doped layer according to illustrative embodiments
  • FIG. 13 shows a cross-sectional view of formation of a carbon liner according to illustrative embodiments
  • FIG. 14 shows a cross-sectional view of formation of a retrograde doped layer according to illustrative embodiments
  • FIG. 15 shows a cross-sectional view of formation of a carbon liner according to illustrative embodiments
  • FIG. 16 shows a cross-sectional view of formation of an opening in the substrate according to illustrative embodiments
  • FIG. 17 shows a cross-sectional view of formation of formation of a high mobility channel material according to illustrative embodiments
  • FIG. 18 shows a cross-sectional shows removal of the hardmask according to illustrative embodiments
  • FIG. 19 shows a cross-sectional view shows formation of a set of high mobility channel fins over the substrate according to illustrative embodiments
  • FIG. 20 shows a cross-sectional view of an opening formed in the substrate according to illustrative embodiments
  • FIG. 21 shows a cross-sectional view of formation of the high mobility channel material according to illustrative embodiments
  • FIG. 22 shows a cross-sectional view of the formation retrograde doped layer according to illustrative embodiments.
  • FIG. 23 shows a cross-sectional view of formation of the carbon layer over the retrograde doped layer according to illustrative embodiments
  • a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage.
  • a set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium).
  • the retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant.
  • the device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.
  • first element such as a first structure, e.g., a first layer
  • second element such as a second structure, e.g. a second layer
  • intervening elements such as an interface structure, e.g. interface layer
  • depositing may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
  • CVD chemical vapor deposition
  • LPCVD low-pressure CVD
  • PECVD plasma-enhanced CVD
  • SACVD semi-
  • FIG. 2 shows a cross sectional view of a device 100 according to an embodiment of the invention.
  • Device 100 comprises a substrate 102 and a hard mask 104 formed over substrate 102 .
  • an opening 106 is formed in substrate 102 .
  • Opening 106 is patterned, for example, using a photo-lithography processes or other lithographic process (e.g., electron beam lithography, imprint lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like.
  • hard mask 104 comprises SiN or SiO2
  • substrate 102 includes a silicon substrate (e.g., wafer).
  • Substrate 102 may be silicon in a crystalline structure (e.g., a bulk silicon substrate).
  • a retrograde doped layer 108 is formed within opening 106 of substrate 102 .
  • retrograde doped layer 108 is grown within opening 106 and doped using an in situ doping process.
  • Retrograde doped layer 108 comprises Si or Si—Ge, and is grown by a CMOS compatible process, e.g., CVD.
  • Retrograde doped layer 108 is doped using an in-situ doping technique wherein dopants are introduced to the Si/Si—Ge at the same time the Si/Si—Ge is being deposited.
  • the Si/Si—Ge of retrograde doped layer 108 is counter doped, e.g., with arsenic, antimony, or phosphorous, to ensure proper isolation.
  • retrograde doped layer 108 comprises doped N+Silicon/SiC Silicon layers (for PMOS), doped P+Silicon/SiC silicon layers (for NMOS), doped N+SiGe/SiGeC layers (for PMOS), or doped P+SiGe/SiGeC (for NMOS).
  • the Silicon NMOS may be strained as well.
  • device 100 further comprises a carbon liner 110 formed over the retrograde doped layer 108 within opening 106 .
  • carbon liner 110 comprises Silicon Germanium:Carbon (SiGe:C), which is grown over retrograde doped layer 108 .
  • a high mobility channel material 112 is then formed over carbon liner 110 , as shown in FIG. 5 .
  • high mobility channel material 112 i.e., Si or Si—Ge
  • CVD chemical vapor deposition
  • hardmask 104 is then removed, resulting in device 100 shown in FIG. 6 .
  • a set of fins 114 i.e., silicon fins
  • a set of high mobility channel fins 116 are then patterned and formed over substrate 102 .
  • Fins 114 and high mobility channel fins 116 may be fabricated using any suitable process including one or more photolithography and etch processes.
  • the photolithography process may include forming a photoresist layer (not shown) overlying substrate 102 (e.g., on a silicon layer), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist.
  • the masking element may then be used to etch fins 114 into the silicon layer, e.g., using reactive ion etch (RIE) and/or other suitable processes, and etch high mobility channel fins 116 into high mobility channel material 112 .
  • fins 114 and high mobility channel fins 116 are formed using a sidewall image transfer technique.
  • fins 114 are formed by a double-patterning lithography (DPL) process.
  • DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density.
  • DPL methodologies may be used including, double exposure (e.g., using two mask sets), forming spacers adjacent features and removing the features to provide a pattern of spacers, resist freezing, and/or other suitable processes.
  • Device 200 comprises a substrate 202 and a hard mask 204 formed over substrate 202 .
  • an opening 206 is formed in substrate 202 .
  • Opening 206 is patterned, for example, using a photo-lithography processes or other lithographic process (e.g., electron beam lithography, imprint lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like.
  • hard mask 104 comprises SiN or SiO2
  • substrate 202 includes a silicon substrate (e.g., wafer).
  • Substrate 202 may be silicon in a crystalline structure (e.g., a bulk silicon substrate).
  • a high mobility channel material 212 is formed over substrate 202 within opening 206 .
  • high mobility channel material 212 is grown within opening 206 using an in situ process.
  • a retrograde doped layer 208 is then formed over substrate 202 , as shown in FIG. 10 .
  • retrograde doped layer 208 is formed along a bottom edge/surface of high mobility channel material 212 and over substrate 202 , e.g., via a counter dopant retrograde implant 214 .
  • Retrograde doped layer 208 comprises Si or Si—Ge, which is counter doped with N-type dopants (e.g., arsenic, antimony, or phosphorus) to ensure proper isolation.
  • N-type dopants e.g., arsenic, antimony, or phosphorus
  • carbon liner 210 is formed over retrograde doped layer 208 within substrate 202 using a retrograde carbon implant 218 .
  • the processing steps described and shown by FIGS. 6-7 are then repeated to remove hardmask 204 and form the silicon fins and high mobility channel fins over substrate 102 .
  • Device 300 comprises a substrate 302 and a hard mask 304 formed over substrate 302 .
  • retrograde doped layer 308 is formed within substrate 302 , e.g., via a counter dopant retrograde implant process 314 .
  • retrograde doped layer 308 comprises Si or Si—Ge, which is counter doped (e.g., with arsenic, antimony, or phosphorus) to ensure proper isolation.
  • hardmask 304 is formed and patterned over substrate 302 , and dopant implantation process 314 is performed.
  • carbon liner 310 is formed over retrograde doped layer 308 within substrate 302 using a retrograde carbon implant 318 .
  • a high mobility channel material is then formed within an opening patterned over carbon liner 310 , and the processing steps described and shown by FIGS. 6-7 are repeated to remove hardmask 304 and form the silicon fins and high mobility channel fins over substrate 302 .
  • Device 400 comprises a substrate 402 with retrograde doped layer 408 formed therein, e.g., via dopant implantation process 414 .
  • retrograde doped layer 408 comprises Si or Si—Ge, which is counter doped (e.g., with arsenic, antimony, or phosphorus) to ensure proper isolation.
  • Dopant implantation process 414 therefore impacts all of substrate 402 and results in retrograde doped layer 408 being formed along the entire width of substrate 402 .
  • Carbon liner 410 is then formed over the retrograde doped layer 408 within substrate 402 using a retrograde carbon implant 418 , as shown in FIG. 15 . Similarly, carbon liner 410 is also formed along the entire width of substrate 402 .
  • opening 406 is formed in substrate 402 .
  • Opening 406 is patterned, for example, using a photo-lithography processes or other lithographic process (e.g., electron beam lithography, imprint lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like.
  • substrate 402 is removed to a top surface of carbon liner 410 .
  • High mobility channel material 412 is then formed over carbon liner 410 within opening 406 , as shown in FIG. 17 .
  • high mobility channel material 412 is grown within opening 406 using an in situ process.
  • Hardmask 404 is then removed, resulting in the structure shown in FIG.
  • a set of fins 414 i.e., silicon fins
  • a set of high mobility channel fins 416 are then patterned and formed over substrate 402 .
  • device 400 comprises a set of silicon fins 414 adjacent high mobility channel fins 416 , wherein silicon fins 414 are also formed atop retrograde doped layer 408 and carbon liner 410 .
  • the same retrograde well is used for both Silicon PFETS and SiGe PFETS. Each is formed on the same substrate 402 with the same retrograde well implants.
  • Device 500 comprises a substrate 502 with opening 506 formed therein.
  • High mobility channel material 512 is then formed over substrate 502 within opening 506 , as shown in FIG. 21 .
  • high mobility channel material 512 is grown within opening 506 using an in situ process.
  • retrograde doped layer 508 is formed over substrate 502 , as shown in FIG. 22 .
  • retrograde doped layer 508 is formed along a bottom edge of high mobility channel material 512 and within substrate 502 , e.g., via a counter dopant retrograde implant 514 . As shown, no hardmask is present during this processing step. Dopant implantation process 514 therefore impacts both high mobility channel material 512 and substrate 502 , resulting in retrograde doped layer 508 being formed along the entire width of substrate 502 .
  • Retrograde doped layer 508 comprises Si or Si—Ge, which is counter doped with N-type dopants (e.g., arsenic, antimony, or phosphorus) to ensure proper isolation.
  • N-type dopants e.g., arsenic, antimony, or phosphorus
  • retrograde carbon implant 518 impacts both high mobility channel material 512 and substrate 502 , resulting in retrograde carbon implant being formed along the entire width of substrate 502 .
  • the processing steps described and shown in FIG. 19 are then repeated to form the silicon fins and high mobility channel fins over substrate 502 .
  • the gate structure includes a gate dielectric layer and a gate electrode. Numerous other layers may also be present, for example, capping layers, interface layers, spacer elements, and/or other suitable features.
  • the gate dielectric layer may include dielectric material such as, silicon oxide, silicon nitride, silicon oxinitride, dielectric with a high dielectric constant (high k), and/or combinations thereof.
  • high k materials include hafnium silicate, hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (Hf O2 -A l2O3 ) alloy, and/or combinations thereof.
  • the gate dielectric layer may be formed using processes such as, photolithography patterning, oxidation, deposition, etching, and/or other suitable processes.
  • the gate electrode may include polysilicon, silicon-germanium, a metal including metal compounds such as, Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, and/or other suitable conductive materials known in the art.
  • the gate electrode may be formed using processes such as, physical vapor deposition (PVD), CVD, plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes which may be followed, for example, by photolithography and/or etching processes.
  • PVD physical vapor deposition
  • CVD plasma-enhanced chemical vapor deposition
  • PECVD atmospheric pressure chemical vapor deposition
  • LPCVD low-pressure CVD
  • HD CVD high density plasma CVD
  • ACVD atomic layer CVD
  • design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein.
  • Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof.
  • a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof.
  • a tool can be a computing device or other appliance on which software runs or in which hardware is implemented.
  • a module might be implemented utilizing any form of hardware, software, or a combination thereof.
  • processors for example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module.
  • the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules.
  • the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations.

Abstract

Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Description

    BACKGROUND
  • 1. Technical Field
  • This invention relates generally to the field of semiconductors, and more particularly, to approaches used to form a complementary metal-oxide field effect transistor.
  • 2. Related Art
  • A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FINFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FINFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FINFET is formed by the intersection of two shapes, i.e., a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition and etc.
  • Silicon based FinFETs have been successfully fabricated using conventional MOSFET technology. A typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over the fin(s). A double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow. Other FinFET architectures may include three or more effective gates.
  • It is currently known that performance improvement in a bulk finFET can be increased by adding high mobility channel materials. Germanium based devices (Ge-FinFET) include a fin formed at least in part, of germanium (as opposed to silicon fin). Typical Ge-FinFET fabrication includes patterning a germanium layer on a substrate to form a narrow Ge-fin. However, even high mobility channel materials like Ge have aggravated junction leakage if the device interface is not properly engineered. As shown by the prior art device 10 of FIG. 1, the bulk FinFET suffers from punch-through leakage along the fin channel, which significantly contributes to overall device leakage. Furthermore, prior art device 10 is highly susceptible to damage during punch-through implant, and suffers from carrier spill-out to the undoped fin channel, which lowers the carrier mobility. Accordingly, what is needed is a solution to at least one of these deficiencies.
    • SUMMARY
  • In general, embodiments herein provide device isolation in a complimentary metal-oxide-semiconductor (CMOS) fin field effect transistor (finFET). Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., Si or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner formed over the retrograde doped layer to prevent carrier spill-out to the high mobility channel fins.
  • One aspect of the present invention includes a method for forming a device, the method comprising: forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); forming a set of high mobility channel fins over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and forming a set of silicon fins adjacent the set of high mobility channel fins.
  • Another aspect of the present invention includes a method for providing device isolation in a complementary metal-oxide-semiconductor fin field effect transistor, the method comprising: forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); forming a set of high mobility channel fins over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and forming a set of silicon fins adjacent the set of high mobility channel fins.
  • Another aspect of the present invention includes a semiconductor device comprising: a retrograde doped layer formed over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); a set of high mobility channel fins formed over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; and a set of silicon fins formed adjacent the set of high mobility channel fins.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
  • FIG. 1 shows a cross-sectional view of a prior art semiconductor device;
  • FIG. 2 shows a cross-sectional view of an opening formed in a substrate according to illustrative embodiments;
  • FIG. 3 shows a cross-sectional view of formation of a retrograde doped layer in the opening formed in the substrate according to illustrative embodiments;
  • FIG. 4 shows a cross-sectional view of formation of a carbon liner over the retrograde doped layer according to illustrative embodiments;
  • FIG. 5 shows a cross-sectional view of formation of a high mobility channel material according to illustrative embodiments;
  • FIG. 6 shows a cross-sectional view of removal of a hardmask according to illustrative embodiments;
  • FIG. 7 shows a cross-sectional view of a set of high mobility channel fins formed over the retrograde doped layer and the carbon liner according to illustrative embodiments;
  • FIG. 8 shows a cross-sectional view of an opening formed in the substrate according to illustrative embodiments;
  • FIG. 9 shows a cross-sectional view of formation of a high mobility channel material according to illustrative embodiments;
  • FIG. 10 shows a cross-sectional view of formation of a retrograde doped layer according to illustrative embodiments;
  • FIG. 11 shows a cross-sectional view of formation of a carbon liner according to illustrative embodiments;
  • FIG. 12 shows a cross-sectional view of formation of a retrograde doped layer according to illustrative embodiments;
  • FIG. 13 shows a cross-sectional view of formation of a carbon liner according to illustrative embodiments;
  • FIG. 14 shows a cross-sectional view of formation of a retrograde doped layer according to illustrative embodiments;
  • FIG. 15 shows a cross-sectional view of formation of a carbon liner according to illustrative embodiments;
  • FIG. 16 shows a cross-sectional view of formation of an opening in the substrate according to illustrative embodiments;
  • FIG. 17 shows a cross-sectional view of formation of formation of a high mobility channel material according to illustrative embodiments;
  • FIG. 18 shows a cross-sectional shows removal of the hardmask according to illustrative embodiments;
  • FIG. 19 shows a cross-sectional view shows formation of a set of high mobility channel fins over the substrate according to illustrative embodiments;
  • FIG. 20 shows a cross-sectional view of an opening formed in the substrate according to illustrative embodiments;
  • FIG. 21 shows a cross-sectional view of formation of the high mobility channel material according to illustrative embodiments;
  • FIG. 22 shows a cross-sectional view of the formation retrograde doped layer according to illustrative embodiments; and
  • FIG. 23 shows a cross-sectional view of formation of the carbon layer over the retrograde doped layer according to illustrative embodiments;
    •
  • The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements.
    • DETAILED DESCRIPTION
  • Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. Described are approaches for device isolation in a complementary metal-oxide finFET (e.g., a bulk finFET). Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.
  • It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
  • Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
  • The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
  • As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.
  • With reference again to the figures, FIG. 2 shows a cross sectional view of a device 100 according to an embodiment of the invention. Device 100 comprises a substrate 102 and a hard mask 104 formed over substrate 102. As shown, an opening 106 is formed in substrate 102. Opening 106 is patterned, for example, using a photo-lithography processes or other lithographic process (e.g., electron beam lithography, imprint lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like. In one embodiment, hard mask 104 comprises SiN or SiO2, and substrate 102 includes a silicon substrate (e.g., wafer). Substrate 102 may be silicon in a crystalline structure (e.g., a bulk silicon substrate).
  • Next, as shown in FIG. 3, a retrograde doped layer 108 is formed within opening 106 of substrate 102. In one embodiment, retrograde doped layer 108 is grown within opening 106 and doped using an in situ doping process. Retrograde doped layer 108 comprises Si or Si—Ge, and is grown by a CMOS compatible process, e.g., CVD. Retrograde doped layer 108 is doped using an in-situ doping technique wherein dopants are introduced to the Si/Si—Ge at the same time the Si/Si—Ge is being deposited. In one embodiment, the Si/Si—Ge of retrograde doped layer 108 is counter doped, e.g., with arsenic, antimony, or phosphorous, to ensure proper isolation. In alternative embodiments, retrograde doped layer 108 comprises doped N+Silicon/SiC Silicon layers (for PMOS), doped P+Silicon/SiC silicon layers (for NMOS), doped N+SiGe/SiGeC layers (for PMOS), or doped P+SiGe/SiGeC (for NMOS). In these embodiments, the Silicon NMOS may be strained as well.
  • As shown in FIG. 4, device 100 further comprises a carbon liner 110 formed over the retrograde doped layer 108 within opening 106. In one embodiment, carbon liner 110 comprises Silicon Germanium:Carbon (SiGe:C), which is grown over retrograde doped layer 108. A high mobility channel material 112 is then formed over carbon liner 110, as shown in FIG. 5. In one embodiment, high mobility channel material 112 (i.e., Si or Si—Ge) is grown over carbon liner 110 within opening 106 using CVD. Next, hardmask 104 is then removed, resulting in device 100 shown in FIG. 6.
  • As shown in FIG. 7, a set of fins 114 (i.e., silicon fins) and a set of high mobility channel fins 116 are then patterned and formed over substrate 102. Fins 114 and high mobility channel fins 116 may be fabricated using any suitable process including one or more photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) overlying substrate 102 (e.g., on a silicon layer), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. The masking element may then be used to etch fins 114 into the silicon layer, e.g., using reactive ion etch (RIE) and/or other suitable processes, and etch high mobility channel fins 116 into high mobility channel material 112. In one embodiment, fins 114 and high mobility channel fins 116 are formed using a sidewall image transfer technique. In another embodiment, fins 114 are formed by a double-patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density. Various DPL methodologies may used including, double exposure (e.g., using two mask sets), forming spacers adjacent features and removing the features to provide a pattern of spacers, resist freezing, and/or other suitable processes.
  • Referring now to FIG. 8, a cross sectional view of a device 200 according to an embodiment of the invention is shown. Device 200 comprises a substrate 202 and a hard mask 204 formed over substrate 202. As shown, an opening 206 is formed in substrate 202. Opening 206 is patterned, for example, using a photo-lithography processes or other lithographic process (e.g., electron beam lithography, imprint lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like. In one embodiment, hard mask 104 comprises SiN or SiO2, and substrate 202 includes a silicon substrate (e.g., wafer). Substrate 202 may be silicon in a crystalline structure (e.g., a bulk silicon substrate).
  • Next, as shown in FIG. 9, a high mobility channel material 212 is formed over substrate 202 within opening 206. In this embodiment, high mobility channel material 212 is grown within opening 206 using an in situ process. A retrograde doped layer 208 is then formed over substrate 202, as shown in FIG. 10. In this embodiment, retrograde doped layer 208 is formed along a bottom edge/surface of high mobility channel material 212 and over substrate 202, e.g., via a counter dopant retrograde implant 214. Retrograde doped layer 208 comprises Si or Si—Ge, which is counter doped with N-type dopants (e.g., arsenic, antimony, or phosphorus) to ensure proper isolation.
  • Next, as shown in FIG. 11, carbon liner 210 is formed over retrograde doped layer 208 within substrate 202 using a retrograde carbon implant 218. The processing steps described and shown by FIGS. 6-7 are then repeated to remove hardmask 204 and form the silicon fins and high mobility channel fins over substrate 102.
  • Turning now to FIG. 12, a cross sectional view of a device 300 according to an embodiment of the invention is shown. Device 300 comprises a substrate 302 and a hard mask 304 formed over substrate 302. As shown, retrograde doped layer 308 is formed within substrate 302, e.g., via a counter dopant retrograde implant process 314. In this embodiment, retrograde doped layer 308 comprises Si or Si—Ge, which is counter doped (e.g., with arsenic, antimony, or phosphorus) to ensure proper isolation. To accomplish this, hardmask 304 is formed and patterned over substrate 302, and dopant implantation process 314 is performed.
  • Next, as shown in FIG. 13, carbon liner 310 is formed over retrograde doped layer 308 within substrate 302 using a retrograde carbon implant 318. Although not shown for the sake of brevity, a high mobility channel material is then formed within an opening patterned over carbon liner 310, and the processing steps described and shown by FIGS. 6-7 are repeated to remove hardmask 304 and form the silicon fins and high mobility channel fins over substrate 302.
  • Turning now to FIG. 14, a cross sectional view of a device 400 according to an embodiment of the invention is shown. Device 400 comprises a substrate 402 with retrograde doped layer 408 formed therein, e.g., via dopant implantation process 414. In this embodiment, retrograde doped layer 408 comprises Si or Si—Ge, which is counter doped (e.g., with arsenic, antimony, or phosphorus) to ensure proper isolation. As shown, no hardmask is present during this processing step. Dopant implantation process 414 therefore impacts all of substrate 402 and results in retrograde doped layer 408 being formed along the entire width of substrate 402. Carbon liner 410 is then formed over the retrograde doped layer 408 within substrate 402 using a retrograde carbon implant 418, as shown in FIG. 15. Similarly, carbon liner 410 is also formed along the entire width of substrate 402.
  • Next, opening 406 is formed in substrate 402. Opening 406 is patterned, for example, using a photo-lithography processes or other lithographic process (e.g., electron beam lithography, imprint lithography, etc.), and removed by a suitable etching process including a wet etch, dry etch, plasma etch, and the like. As shown, substrate 402 is removed to a top surface of carbon liner 410. High mobility channel material 412 is then formed over carbon liner 410 within opening 406, as shown in FIG. 17. In this embodiment, high mobility channel material 412 is grown within opening 406 using an in situ process. Hardmask 404 is then removed, resulting in the structure shown in FIG.
  • As shown in FIG. 19, a set of fins 414 (i.e., silicon fins) and a set of high mobility channel fins 416 are then patterned and formed over substrate 402. As a result, device 400 comprises a set of silicon fins 414 adjacent high mobility channel fins 416, wherein silicon fins 414 are also formed atop retrograde doped layer 408 and carbon liner 410. In this embodiment, the same retrograde well is used for both Silicon PFETS and SiGe PFETS. Each is formed on the same substrate 402 with the same retrograde well implants.
  • Turning now to FIG. 20, a cross sectional view of a device 500 according to an embodiment of the invention is shown. Device 500 comprises a substrate 502 with opening 506 formed therein. High mobility channel material 512 is then formed over substrate 502 within opening 506, as shown in FIG. 21. In this embodiment, high mobility channel material 512 is grown within opening 506 using an in situ process.
  • Next, hardmask 504 is removed and retrograde doped layer 508 is formed over substrate 502, as shown in FIG. 22. In this embodiment, retrograde doped layer 508 is formed along a bottom edge of high mobility channel material 512 and within substrate 502, e.g., via a counter dopant retrograde implant 514. As shown, no hardmask is present during this processing step. Dopant implantation process 514 therefore impacts both high mobility channel material 512 and substrate 502, resulting in retrograde doped layer 508 being formed along the entire width of substrate 502. Retrograde doped layer 508 comprises Si or Si—Ge, which is counter doped with N-type dopants (e.g., arsenic, antimony, or phosphorus) to ensure proper isolation.
  • Next, as shown in FIG. 23, carbon liner 510 is formed over retrograde doped layer 508 within substrate 502 using a retrograde carbon implant 518. Retrograde carbon implant 518 impacts both high mobility channel material 512 and substrate 502, resulting in retrograde carbon implant being formed along the entire width of substrate 502. The processing steps described and shown in FIG. 19 are then repeated to form the silicon fins and high mobility channel fins over substrate 502.
  • Although not shown, it will be appreciated that a set of gate structures are then formed atop each device, i.e., devices 100, 200, 300, 400, and 500. In one embodiment, the gate structure includes a gate dielectric layer and a gate electrode. Numerous other layers may also be present, for example, capping layers, interface layers, spacer elements, and/or other suitable features. The gate dielectric layer may include dielectric material such as, silicon oxide, silicon nitride, silicon oxinitride, dielectric with a high dielectric constant (high k), and/or combinations thereof. Examples of high k materials include hafnium silicate, hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, and/or combinations thereof. The gate dielectric layer may be formed using processes such as, photolithography patterning, oxidation, deposition, etching, and/or other suitable processes. The gate electrode may include polysilicon, silicon-germanium, a metal including metal compounds such as, Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, and/or other suitable conductive materials known in the art. The gate electrode may be formed using processes such as, physical vapor deposition (PVD), CVD, plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes which may be followed, for example, by photolithography and/or etching processes.
  • Furthermore, in various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.
  • It is apparent that there has been provided device isolation in a complimentary metal-oxide fin field effect transistor. While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.

Claims (20)

1. A method for forming a device, the method comprising:
forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of:
doped silicon (Si), and doped silicon-germanium (Si—Ge);
forming a set of high mobility channel fins over the retrograde doped layer, wherein each of the set of high mobility channel fins comprises at least one of: Si, and Si—Ge, and a retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); and
forming a set of silicon fins adjacent the set of high mobility channel fins.
2. The method according to claim 1, further comprising forming a carbon liner over the retrograde doped layer.
3. The method according to claim 1, the forming the retrograde doped layer comprising performing an in situ doping process.
4. The method according to claim 3, the forming the set of high mobility channel fins comprising:
depositing the a high mobility channel material over the retrograde doped layer;
patterning the high mobility channel material, the retrograde doped layer, and the a substrate; and
etching the high mobility channel material, the retrograde doped layer, and the substrate.
5. The method according to claim 4, the depositing comprising growing the high mobility channel material using a chemical vapor deposition of at least one of: Si, and Si—Ge.
6. The method according to claim 2, the forming the retrograde doped layer comprising:
forming an opening in the a substrate;
depositing the a high mobility channel material in the opening; and
performing a counter dopant retrograde implant to form the retrograde doped layer over the substrate in the opening.
7. The method according to claim 6, further comprising performing a retrograde carbon implant to form the carbon liner over the retrograde doped layer.
8. The method according to claim 1, the forming the retrograde doped layer comprising performing a counter dopant retrograde implant to form the retrograde doped layer within the a substrate.
9. The method according to claim 8, further comprising:
patterning an opening in a hardmask formed over the substrate prior to formation of the retrograde doped layer; and
performing a retrograde carbon implant to form the a carbon liner over the retrograde doped layer.
10. A method for providing device isolation in a complementary metal-oxide semiconductor fin field effect transistor, the method comprising:
forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of:
doped silicon (Si), and doped silicon-germanium (Si—Ge);
forming a set of high mobility channel fins over the retrograde doped layer, wherein each of the set of high mobility channel fins comprises at least one of: Si, and Si—Ge, and the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); and
forming a set of silicon fins adjacent the set of high mobility channel fins.
11. The method according to claim 10, further comprising forming a carbon liner over the retrograde doped layer.
12. The method according to claim 10, the forming the retrograde doped layer comprising performing an in situ doping process.
13. The method according to claim 12, the forming the set of high mobility channel fins comprising:
depositing the a high mobility channel material over the retrograde doped layer;
patterning the high mobility channel material, the retrograde doped layer, and the a substrate; and
etching the high mobility channel material, the retrograde doped layer, and the substrate.
14. The method according to claim 13, the depositing comprising growing the high mobility channel material using a chemical vapor deposition of at least one of: Si, and Si—Ge.
15. The method according to claim 11, the forming the retrograde doped layer comprising:
forming an opening in the a substrate;
depositing the a high mobility channel material in the opening; and
performing a counter dopant retrograde implant to form the retrograde doped layer over the substrate in the opening.
16. The method according to claim 15, further comprising performing a retrograde carbon implant to form the carbon liner over the retrograde doped layer.
17. The method according to claim 10, the forming the retrograde doped layer comprising performing a counter dopant retrograde implant to form the retrograde doped layer within the a substrate.
18. The method according to claim 17, further comprising:
patterning an opening in a hardmask formed over the substrate prior to formation of the retrograde doped layer; and
performing a retrograde carbon implant to form the carbon liner over the retrograde doped layer.
19. A semiconductor device comprising:
a retrograde doped layer formed over a substrate, the retrograde doped layer comprising one of:
doped silicon (Si), and doped silicon-germanium (Si—Ge);
a set of high mobility channel fins formed over the retrograde doped layer, wherein each of the set of high mobility channel fins comprises at least one of: Si, and Si—Ge, and a retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); and
a set of silicon fins adjacent the set of high mobility channel fins.
20. The semiconductor device according to claim 19, further comprising a carbon liner formed over the retrograde doped layer, wherein the set of high mobility channel fins and the set of silicon fins are formed over the carbon liner.
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