CN102800576B - The method of graphic diaphragm layer, the method for grid, MOS transistor of being formed - Google Patents
The method of graphic diaphragm layer, the method for grid, MOS transistor of being formed Download PDFInfo
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- CN102800576B CN102800576B CN201110139487.8A CN201110139487A CN102800576B CN 102800576 B CN102800576 B CN 102800576B CN 201110139487 A CN201110139487 A CN 201110139487A CN 102800576 B CN102800576 B CN 102800576B
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Abstract
The method of graphic diaphragm layer, form the method for grid, MOS transistor, the method for described graphic diaphragm layer comprises: provide substrate; Form patterned sacrifice layer on the substrate; Formed on the substrate and need patterned rete, the upper surface of described rete is equal with the upper surface of described patterned sacrifice layer; Described rete forms graph layer, and described graph layer and patterned sacrifice layer define the figure of membrane graphic jointly; With described graph layer for rete described in mask etching, form patterned rete; Remove described graph layer, patterned sacrifice layer.The technical program completes rete when taking graph layer as mask etching rete graphical, saves the step of etched membrane layer.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the method for graphic diaphragm layer, form the method for grid.
Background technology
The method forming grid in traditional handicraft is: provide substrate, and described based top layer is gate dielectric layer; Described gate dielectric layer forms polysilicon layer; Described polysilicon layer forms photoresist layer, and photoresist layer is exposed, develop formed patterned photoresist layer; With patterned photoresist layer for polysilicon layer described in mask etching forms grid.
But, more and more less along with semiconductor device critical size, when the technique node (1/2nd pitch-rows) of semiconductor technology is less than 32nm, under 193nm (nanometer) depositing in water immersion lithography condition, utilize a mask plate to form patterning process as mask encounter physical restriction, adjacent figure pitch-row is too small, due to optical proximity effect, there will be the phenomenon of adjacent pattern adhesion.Therefore, semiconductor device critical size more and more less, when the technique node (1/2nd pitch-rows) of semiconductor technology is less than 32nm, the phenomenon utilizing the technique of traditional graphical polysilicon layer to form grid to there will be adjacent pattern adhesion.
In order to solve above technical problem, the technology of Dual graphing is proposed in prior art, the first figure and second graph is divided into by needing the figure transferred on photoresist layer, namely patterned photoresist layer is divided into the photoresist layer of the first patterned photoresist layer and second graphical, at twice polysilicon layer is carried out graphically.Be specially: provide substrate, described based top layer is gate dielectric layer; Described gate dielectric layer forms polysilicon layer; Described polysilicon layer forms the first patterned photoresist layer; With patterned first photoresist layer for polysilicon layer described in mask etching; Afterwards, polysilicon layer is after etching formed the photoresist layer of second graphical, continue the described polysilicon layer of etching with the photoresist layer of second graphical for mask, form grid.
Also many patterned methods are disclosed, the method that the application number applied for such as on May 30th, 2008 is graphical substrate disclosed in the Chinese patent application of 200810113985.3 in prior art.
Summary of the invention
The problem to be solved in the present invention is that the method step of the Dual graphing of prior art is complicated.
For solving the problem, the invention provides a kind of method of graphic diaphragm layer, comprising:
Substrate is provided;
Form patterned sacrifice layer on the substrate;
Form rete on the substrate, the upper surface of described rete is equal with the upper surface of described patterned sacrifice layer;
Described rete forms graph layer, and described graph layer and patterned sacrifice layer define the figure of membrane graphic jointly;
With described graph layer for rete described in mask etching, form patterned rete;
Remove described graph layer, patterned sacrifice layer.
Optionally, described rete is polysilicon layer;
The top layer of described substrate is gate dielectric layer, and described polysilicon layer, patterned sacrifice layer are formed on the gate dielectric layer of described substrate;
Described patterned rete is grid.
Optionally, described rete is hard mask layer;
The top layer of described substrate is followed successively by gate dielectric layer and pseudo-gate layer, and described pseudo-gate layer is formed on described gate dielectric layer, and described hard mask layer is formed in described pseudo-gate layer.
Optionally, the material of described pseudo-gate layer is polysilicon.
Optionally, the material of described sacrifice layer is silicon nitride, metal, agraphitic carbon, carbon doped silicon or polymer.
Optionally, form patterned sacrifice layer on the substrate to comprise:
Form sacrifice layer on the substrate;
Described sacrifice layer forms photoresist layer;
Utilize photoetching or impress described photoresist layer and form patterned photoresist layer, afterwards with patterned photoresist layer for mask etching sacrifice layer, form patterned sacrifice layer;
Remove patterned photoresist layer.
Optionally, wet etching is utilized to remove described patterned sacrifice layer.
Optionally, described graph layer is patterned photoresist layer;
Described rete forms graph layer comprise: on described rete, form photoresist layer, utilization exposure, the graphical described photoresist layer of developing process form patterned photoresist layer.
Optionally, ashing is utilized to remove described graph layer.
Optionally, the method for described formation rete comprises:
Utilize vapour deposition to form rete, cover described substrate and described patterned sacrifice layer;
Described rete is planarized to the upper surface exposing described patterned sacrifice layer, makes the upper surface of rete equal with the upper surface of patterned sacrifice layer.
Optionally, the material of described gate dielectric layer is silica.
Optionally, the material of described hard mask layer is silicon nitride.
The present invention also provides a kind of method forming grid, comprising:
Patterned hard mask layer is formed by above-described method;
With described patterned hard mask layer for mask etches successively described pseudo-gate layer, gate dielectric layer, the pseudo-gate layer after etching forms dummy grid;
Form interlayer dielectric layer, cover described substrate, the upper surface of described interlayer dielectric layer is equal with the upper surface of described dummy grid;
Remove described dummy grid and form dummy grid groove;
In described dummy grid groove, filled conductive material forms grid.
Optionally, described electric conducting material is metal.
Optionally, the material of described hard mask layer is silicon nitride.
Optionally, the material of described interlayer dielectric layer is low-k materials or ultralow-k material film.
Optionally, described low-k materials is selected from SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON one of them or they combination in any.
Optionally, described ultralow-k material film is black diamond.
The embodiment of the present invention also provides a kind of method forming MOS transistor, comprises and forms grid by above-described method.
Compared with prior art, technical solution of the present invention has the following advantages:
The technical program defines the figure of membrane graphic jointly by patterned sacrifice layer and graph layer, and the step forming patterned sacrifice layer is before the step forming rete, from existing to define two patterned photoresist layers after rete is formed again respectively different.Further, what complete rete when taking graph layer as mask etching rete is graphical, saves the step of etched membrane layer, simplifies the method for graphic diaphragm layer.
In the present invention one specific embodiment, rete is polysilicon layer, and the top layer of substrate is gate dielectric layer, and graphical polysilicon layer defines grid.
In another specific embodiment of the present invention, rete is hard mask layer, and the top layer of substrate is gate dielectric layer and polysilicon layer, and graphic diaphragm layer defines dummy grid.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the method for the graphic diaphragm layer of the specific embodiment of the invention;
Fig. 2 a, Fig. 2 b ~ Fig. 7 a, Fig. 7 b are cross-sectional view and the schematic top plan view of the method for the graphic diaphragm layer of the present invention first specific embodiment;
Fig. 8 a, Fig. 8 b are cross-sectional view and the schematic top plan view of the structure that the method for the graphic diaphragm layer that the present invention second specifically implements is formed.
Embodiment
The technical program defines the figure of membrane graphic jointly by patterned sacrifice layer and graph layer, and the step forming patterned sacrifice layer is before the step forming rete, from existing to define two patterned photoresist layers after rete is formed again respectively different.Further, what complete rete when taking graph layer as mask etching rete is graphical, saves the step of etched membrane layer.
In order to make those skilled in the art can better understand the present invention, describe the specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the flow chart of the method for the graphic diaphragm layer of the specific embodiment of the invention, and with reference to figure 1, the method for the graphic diaphragm layer of the specific embodiment of the invention comprises:
Step S11, provides substrate;
Step S12, forms patterned sacrifice layer on the substrate;
Step S13, forms rete on the substrate, and the upper surface of described rete is equal with the upper surface of described patterned sacrifice layer;
Step S14, described rete forms graph layer, and described graph layer and patterned sacrifice layer define the figure of membrane graphic jointly;
Step S15, with described graph layer for rete described in mask etching, forms patterned rete;
Step S16, removes described graph layer, patterned sacrifice layer.
Fig. 2 a, Fig. 2 b ~ Fig. 7 a, Fig. 7 b are cross-sectional view and the schematic top plan view of the method for the graphic diaphragm layer of the present invention first specific embodiment, the embodiment that can better understand the present invention to make those skilled in the art, describes the method for the graphic diaphragm layer of the specific embodiment of the present invention in detail below in conjunction with specific embodiment and Fig. 1, Fig. 2 a, Fig. 2 b ~ Fig. 7 a, Fig. 7 b.
In the present invention first specific embodiment, the method for graphic diaphragm layer of the present invention is utilized to form grid.The following detailed description of the first specific embodiment of the present invention.
In conjunction with being the cross-sectional view of Fig. 2 b along a-a direction with reference to figure 1 and Fig. 2 a, Fig. 2 b, Fig. 2 a, Fig. 2 b is the schematic top plan view of Fig. 2 a, performs step S11, provides substrate 20.In the present invention first specific embodiment, the top layer of substrate 20 is gate dielectric layer 21.The material of substrate 20 is silicon or the SiGe of monocrystalline; Also can be silicon-on-insulator (SOI); Or other material can also be comprised, the III-V such as such as GaAs.The (not shown) such as source region, drain region and isolation structure are formed in described substrate 20.The material of described gate dielectric layer 21 is silica, the other materials that also can be known to the skilled person.
In conjunction with being the cross-sectional view of Fig. 3 b along a-a direction with reference to figure 1 and Fig. 3 a, Fig. 3 b, Fig. 3 a, Fig. 3 b is the schematic top plan view of Fig. 3 a, performs step S12, described substrate 20 forms patterned sacrifice layer 22.Due in first embodiment of the invention, the top layer of substrate 20 is gate dielectric layer 21, in described substrate 20, therefore forms patterned sacrifice layer 22 namely on gate dielectric layer 21, form patterned sacrifice layer 22.The method that described substrate 20 is formed patterned sacrifice layer 22 is: in described substrate 20, form sacrifice layer 22, in this specific embodiment, namely on the gate dielectric layer 21 of substrate 20 top layer, forms sacrifice layer 22; Described sacrifice layer 22 forms photoresist layer (not shown); Utilize photoetching or impress described photoresist layer and form patterned photoresist layer, afterwards with patterned photoresist layer for mask etching sacrifice layer, form patterned sacrifice layer 22; Remove patterned photoresist layer.The material of sacrifice layer 22 is silicon nitride, metal, agraphitic carbon, carbon doped silicon or polymer.In concrete enforcement, need specifically to select with photoetching process or the graphical sacrifice layer of imprint process according to the material of sacrifice layer 22.
In conjunction with reference to figure 1 and Fig. 4 a, Fig. 4 b, Fig. 4 a is the cross-sectional view of Fig. 4 b along a-a direction, Fig. 4 b is the schematic top plan view of Fig. 4 a, perform step S13, described substrate 20 forms rete 23, the upper surface of described rete 23 is equal with the upper surface of described patterned sacrifice layer 22, and that is, rete 23 is formed in the substrate 20 of not graphical sacrifice layer 22 covering.The method forming rete 23 comprises: utilize vapour deposition to form rete 23, cover described substrate 20 and described patterned sacrifice layer 22; The upper surface exposing described patterned sacrifice layer 22 is planarized to described rete 23, makes the upper surface of rete 23 equal with the upper surface of patterned sacrifice layer 22.In this specific embodiment, rete 23 is polysilicon layer.
In conjunction with reference to figure 1 and Fig. 5 a, Fig. 5 b, Fig. 5 a is the cross-sectional view of Fig. 5 b along a-a direction, Fig. 5 b is the schematic top plan view of Fig. 5 a, perform step S14, described rete 23 forms graph layer 24, and described graph layer 24 and patterned sacrifice layer 22 define the patterned figure of rete 23 jointly.In this specific embodiment, graph layer 24 is patterned photoresist layer.Described rete 23 forms photoresist layer, and utilization exposure, the graphical described photoresist layer of developing process form patterned photoresist layer.The figure of both patterned photoresist layer and patterned sacrifice layer 22 composition jointly defined rete 23 graphical after figure.
In conjunction with being the cross-sectional view of Fig. 6 b along a-a direction with reference to figure 1 and Fig. 6 a, Fig. 6 b, Fig. 6 a, Fig. 6 b is the schematic top plan view of Fig. 6 a, performs step S15, with described graph layer 24 for rete described in mask etching 23, forms patterned rete 25.In this specific embodiment, rete 25 is polysilicon layer, and patterned polysilicon layer is grid.
In conjunction with reference to figure 1 and Fig. 7 a, Fig. 7 b, perform step S16, remove described graph layer, patterned sacrifice layer.In the specific embodiment of the invention, graph layer 24 is patterned photoresist layer, utilizes ashing to remove patterned photoresist layer.In other embodiments, if the material of graph layer 24 is other materials, then need to change the corresponding method removing graph layer according to the material of graph layer 24.After removing graph layer 24, utilize wet etching to remove described patterned sacrifice layer 22, the method namely utilizing selectivity to clean removes patterned sacrifice layer 22, guarantees to clean in the process of the patterned sacrifice layer 22 of removal, does not substantially damage substrate 20.
In the graphic diaphragm layer of above first embodiment, rete 25 is polysilicon layer, and graphical polysilicon layer defines grid, and therefore the method for the graphic diaphragm layer of this first embodiment also can be the method forming grid.
In the present invention, rete 25 is not limited to polysilicon layer, can, for needing the rete of patterned other materials in semiconductor applications, such as, can be also the hard mask layer formed in rear grid technique in dummy grid process.Fig. 8 a, Fig. 8 b are cross-sectional view and the schematic top plan view of the structure that the method for the graphic diaphragm layer that the present invention second specifically implements is formed, wherein, Fig. 8 a is the cross-sectional view of Fig. 8 b along a-a direction, Fig. 8 b is the schematic top plan view of Fig. 8 a, and this second specific embodiment illustrates the present invention for the dummy grid formed in rear grid technique.
In second specific embodiment, the top layer of substrate 30 is followed successively by gate dielectric layer 31 and pseudo-gate layer 32, and described pseudo-gate layer 32 is formed on described gate dielectric layer 31, and rete is hard mask layer, and this hard mask layer is formed in described pseudo-gate layer 32.In this second embodiment, the material of pseudo-gate layer 32 is polysilicon, but the material of pseudo-gate layer 32 is not limited to polysilicon, the other materials that also can be known to the skilled person.The method of the graphical hard mask layer of this second embodiment is substantially identical with the method for the graphical polysilicon layer of the first embodiment, does not repeat at this.Form patterned hard mask layer 33 by the graphical hard mask layer of method of the present invention, this patterned hard mask layer 33 has defined the figure needing the dummy grid formed.After utilization, grid technique is formed in the process of grid, utilizes patterned hard mask layer 33 to be that the pseudo-gate layer 32 of mask etching can form dummy grid.In this second embodiment, the material of hard mask layer 33 is silicon nitride, the other materials that also can be known to the skilled person.
According to the second embodiment, graphical hard mask layer defines the figure of dummy grid, the invention provides a kind of method forming grid, forms patterned hard mask layer 33 by the method in the second embodiment; Etch described pseudo-gate layer 32 and gate dielectric layer 31 with described patterned hard mask layer 33 successively for mask, the pseudo-gate layer 32 after etching forms dummy grid; Remove patterned hard mask layer 33, form interlayer dielectric layer, cover substrate, the upper surface of described interlayer dielectric layer is equal with the upper surface of described dummy grid; Remove described dummy grid and form dummy grid groove; In described dummy grid groove, filled conductive material forms grid.
In this specific embodiment, the material of pseudo-gate layer 32 is polysilicon layer, but the material of pseudo-gate layer 32 is not limited to polysilicon layer, the other materials that also can be known to the skilled person.The material of gate dielectric layer 31 is silica, but is not limited to silica.With patterned hard mask layer 33 for mask utilizes dry etching etches polycrystalline silicon layer and gate dielectric layer 31 successively.
After etches polycrystalline silicon layer and gate dielectric layer 31, remove patterned hard mask layer 33, then CVD (Chemical Vapor Deposition) method is utilized to form interlayer dielectric layer, this interlayer dielectric layer covers the polysilicon layer after etching, gate dielectric layer 31 and substrate 20, afterwards, flatening process (can be chemical-mechanical planarization, CMP) planarization interlayer dielectric layer is utilized, remove polysilicon layer upper interlayer dielectric layer, make the upper surface of interlayer dielectric layer equal with the upper surface of polysilicon layer.The material of interlayer dielectric layer is low-k materials or ultralow-k material film, and wherein low-k materials is selected from SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON one of them or they combination in any.Ultralow-k material film is black diamond.
After forming interlayer dielectric layer, utilize wet etching or dry etching, or dummy grid is removed in both combinations, form dummy grid groove.Physical vapour deposition (PVD) or electric plating method filled conductive material in dummy grid groove is utilized to form grid.This electric conducting material can be metal, also can be other electric conducting materials.
Based on the method for above-described formation grid, the present invention also provides a kind of method forming MOS transistor, comprises and forms grid by the method for the graphical polysilicon layer of the first embodiment, or form grid by the method for above-described formation grid.Two kinds are formed in the method for MOS transistor, and the method for the graphical polysilicon layer of the first embodiment is formed in grid technology, in substrate, defines source electrode, drain electrode before the gate is formed; Formed with rear grid technique in the method for grid, after forming grid, need in the substrate of grid both sides, to form source electrode and drain electrode by ion implantation.
It should be noted that, mention " equal " word in the present invention, the surface not representing two kinds of materials is completely equal, allows the difference in height between them in certain error range.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. a method for graphic diaphragm layer, is characterized in that, comprising:
Substrate is provided;
Form patterned sacrifice layer on the substrate;
Form rete on the substrate, the upper surface of described rete is equal with the upper surface of described patterned sacrifice layer;
Described rete forms graph layer, and described graph layer and patterned sacrifice layer define the figure of membrane graphic jointly;
With described graph layer and patterned sacrifice layer for rete described in mask etching, form patterned rete;
Remove described graph layer, patterned sacrifice layer.
2. the method for graphic diaphragm layer as claimed in claim 1, it is characterized in that, described rete is polysilicon layer;
The top layer of described substrate is gate dielectric layer, and described polysilicon layer, patterned sacrifice layer are formed on the gate dielectric layer of described substrate;
Described patterned rete is grid.
3. the method for graphic diaphragm layer as claimed in claim 1, it is characterized in that, described rete is hard mask layer;
The top layer of described substrate is followed successively by gate dielectric layer and pseudo-gate layer, and described pseudo-gate layer is formed on described gate dielectric layer, and described hard mask layer is formed in described pseudo-gate layer.
4. the method for graphic diaphragm layer as claimed in claim 3, it is characterized in that, the material of described pseudo-gate layer is polysilicon.
5. the method for the graphic diaphragm layer as described in any one of Claims 1 to 4, is characterized in that, the material of described sacrifice layer is silicon nitride, metal, agraphitic carbon, carbon doped silicon or polymer.
6. the method for graphic diaphragm layer as claimed in claim 5, is characterized in that, form patterned sacrifice layer on the substrate and comprise:
Form sacrifice layer on the substrate;
Described sacrifice layer forms photoresist layer;
Utilize photoetching or impress described photoresist layer and form patterned photoresist layer, afterwards with patterned photoresist layer for mask etching sacrifice layer, form patterned sacrifice layer;
Remove patterned photoresist layer.
7. the method for graphic diaphragm layer as claimed in claim 6, is characterized in that, utilizes wet etching to remove described patterned sacrifice layer.
8. the method for the graphic diaphragm layer as described in any one of Claims 1 to 4, is characterized in that, described graph layer is patterned photoresist layer;
Described rete forms graph layer comprise: on described rete, form photoresist layer, utilization exposure, the graphical described photoresist layer of developing process form patterned photoresist layer.
9. the method for graphic diaphragm layer as claimed in claim 8, is characterized in that, utilize ashing to remove described graph layer.
10. the method for the graphic diaphragm layer as described in any one of Claims 1 to 4, is characterized in that, the method for described formation rete comprises:
Utilize vapour deposition to form rete, cover described substrate and described patterned sacrifice layer;
Described rete is planarized to the upper surface exposing described patterned sacrifice layer, makes the upper surface of rete equal with the upper surface of patterned sacrifice layer.
The method of 11. graphic diaphragm layers as claimed in claim 2 or claim 3, is characterized in that, the material of described gate dielectric layer is silica.
The method of 12. graphic diaphragm layers as claimed in claim 3, is characterized in that, the material of described hard mask layer is silicon nitride.
13. 1 kinds of methods forming grid, is characterized in that, comprising:
Patterned hard mask layer is formed by the method described in claim 3 or 4;
With described patterned hard mask layer for mask etches successively described pseudo-gate layer, gate dielectric layer, the pseudo-gate layer after etching forms dummy grid;
Form interlayer dielectric layer, cover described substrate, the upper surface of described interlayer dielectric layer is equal with the upper surface of described dummy grid;
Remove described dummy grid and form dummy grid groove;
In described dummy grid groove, filled conductive material forms grid.
14. methods forming grid as claimed in claim 13, it is characterized in that, described electric conducting material is metal.
15. methods forming grid as claimed in claim 14, it is characterized in that, the material of described hard mask layer is silicon nitride.
16. methods forming grid as claimed in claim 13, it is characterized in that, the material of described interlayer dielectric layer is low-k materials or ultralow-k material film.
17. methods forming grid as claimed in claim 16, it is characterized in that, described low-k materials is selected from SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON one of them or they combination in any.
18. methods forming grid as claimed in claim 16, it is characterized in that, described ultralow-k material film is black diamond.
19. 1 kinds of methods forming MOS transistor, is characterized in that, comprise and form grid by the method described in any one of claim 2,13 ~ 18.
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| CN103021817B (en) * | 2012-12-27 | 2017-12-08 | 上海集成电路研发中心有限公司 | Cleaning method after wet etching |
| CN105448688A (en) * | 2014-07-09 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Gate formation method and semiconductor device |
| CN106158758B (en) * | 2015-04-08 | 2018-12-28 | 北大方正集团有限公司 | Mask plate component, the preparation method of integrated circuit board and integrated circuit board |
| CN109239815A (en) * | 2017-07-10 | 2019-01-18 | 上海箩箕技术有限公司 | Cover board and forming method thereof, cover board motherboard, electronic equipment |
| CN107910299B (en) | 2017-11-20 | 2020-05-12 | 合肥鑫晟光电科技有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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| CN101027761A (en) * | 2004-07-28 | 2007-08-29 | 英特尔公司 | Planarizing a semiconductor structure to form replacement metal gates |
| CN101140421A (en) * | 2006-09-04 | 2008-03-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming a photoresist pattern |
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| KR20030049166A (en) * | 2001-12-14 | 2003-06-25 | 주식회사 하이닉스반도체 | A fabricating method of semiconductor device |
| KR100478502B1 (en) * | 2003-05-12 | 2005-03-29 | 동부아남반도체 주식회사 | Formation method of floating gate in flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101027761A (en) * | 2004-07-28 | 2007-08-29 | 英特尔公司 | Planarizing a semiconductor structure to form replacement metal gates |
| CN101140421A (en) * | 2006-09-04 | 2008-03-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming a photoresist pattern |
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