CN103996604A - Method for forming ultralow-size patterns by adopting double-side-wall process - Google Patents
Method for forming ultralow-size patterns by adopting double-side-wall process Download PDFInfo
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- CN103996604A CN103996604A CN201410253948.8A CN201410253948A CN103996604A CN 103996604 A CN103996604 A CN 103996604A CN 201410253948 A CN201410253948 A CN 201410253948A CN 103996604 A CN103996604 A CN 103996604A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Abstract
Provided is a method for forming ultralow-size patterns by adopting a double-side-wall process. The method comprises the following steps that through a layer of mask plate, primary photoetching is conducted, a mask layer on a substrate is etched, and therefore the pattern with the first feature size is formed; a layer of thin-film material is deposited on the pattern, so that a conformal layer is formed, wherein the mask pattern with the first feature size is evenly covered with the conformal layer, and the thickness of a thin film on a side wall is a first thickness; secondary photoetching is conducted and etching is conducted, wherein a part of the thin-film material is covered with a photoresist, and the portion, enabling the photoresist to be exposed, of the thin-film material is thinned to form a side wall with a second thickness; the photoresist is removed, so that the pattern with the side walls with the two thicknesses is formed; the thin-film material is etched anisotropically, the portions, on the top and the bottom of the mask layer, of the thin-film material are moved, and only the portions, on the side walls, of the thin-film are left; the mask layer is selectively removed according to the ashing process, and only the side wall formed by the thin-film material is left; etching is conducted by making the thin-film material as a mask for etching, so that the superfine patterns with the two sizes are formed, and the sizes corresponding to the first thickness and the second thickness of the side walls.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate to particularly the method for the hyperfine characteristic size figure of a kind of self aligned formation.More particularly, the present invention relates to a kind of method that adopts bilateral wall technique to form ultralow size figure.
Background technology
The characteristic size of very lagre scale integrated circuit (VLSIC) is according to the development of Moore's Law, 20 nanometers and following characteristic size have been developed into, to more increasing the capacity of semiconductor device and reducing costs on small size, form and there is better performance, the semiconductor device of lower power consumption.The contraction of the characteristic size of each device needs more complicated technology.Photoetching process be commonly use device and circuit pattern are transferred to the method on substrate, the width of line and spacing are two parameters the most key in photoetching process.Spacing is defined as the distance between the identical point of two adjacent lines.Due to various factors, as physical restriction such as optics and light wavelengths, existing photoetching technique has minimum spacing can not meet the demand of integrated circuit below 20 nanometers, lower than the figure of the characteristic size of this particular lithography technique limit, can not form by existing photoetching technique.Therefore, find a kind of method of utilizing existing photoetching technique can meet again characteristic size demand simultaneously just extremely important.
Self aligned secondary graphical method is to be widely studied in recent years and the figure transfer techniques of large-scale production very likely, and by the method, the figure that can meet below 20 nanometers shifts demand, is not subject to the physics of photoetching process and the restriction of the equipment limit.
But the width of the spacer that self aligned secondary graphical method obtains (thickness of conforma layer) is unique, the size of the figure obtaining is like this also unique, but in actual Application of integrated circuit, particularly in logical circuit, SRAM circuit, requirement has the active area of different characteristic size, the grid of different characteristic size etc.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of method that can adopt bilateral wall technique to form ultralow size figure is provided.
In order to realize above-mentioned technical purpose, according to the present invention, a kind of method that adopts bilateral wall technique to form ultralow size figure is provided, and it comprises: first with one deck mask, carry out photoetching for the first time etch mask layer (amorphous carbon sacrifice layer) and form the figure with First Characteristic size (physics limit of this size Proximity Photolithography); Then on this figure, deposit thin film material layer, form the side wall of uniform fold mask graph, the thickness of side wall upper film is the first thickness; Carry out photoetching for the second time etching, photoresist covers a part of material, the thin-film material of the part of exposure is thinned to the side wall with the second thickness; Remove photoresist, form the figure with two kinds of thickness side walls; Anisotropic etched film material, removes the film thin-film material of mask layer top and bottom, only leaves the film on sidewall; Cineration technics is optionally removed hard mask (sacrifice layer), only leaves the side wall that material forms; Thin-film material carries out etching as the mask of etching, form the hyperfine figure with two kinds of sizes, and the size of size is close to the first thickness and second thickness of side wall.
In one embodiment, the method that forms the shallow trench of patterning in silicon substrate comprises: on silicon substrate, form silicon nitride, and on silicon nitride, form mask layer (sacrifice layer), and adopt photoetching process to form the mask graph with First Characteristic size; The method is further included on above-mentioned figure and covers layer of silicon dioxide formation conforma layer, forms the side wall of uniform fold mask graph, and the thickness of side wall upper film is the first thickness; Immediately go photoetching for the second time etching, photoresist covers a part of silicon dioxide conforma layer, the conforma layer of the part of exposure is thinned to the side wall with the second thickness; Anisotropic etched film material, removes the thin-film material of sacrifice layer top and bottom, only leaves the film on sidewall; Adopt oxygen ashing process place to go to be exposed to surperficial mask layer (sacrifice layer); The conforma layer that adopts dry etching etching to carry over, and as hard mask etching silicon nitride and silicon substrate, form shallow trench, the shallow trench isolation finally obtaining from the size of active area have two kinds, first size is close to the first thickness, and the second size is close to the second thickness.
The method that forms in another embodiment the polysilicon gate of patterning on substrate comprises: form silicon dioxide gate dielectric layer, form polysilicon gate, and on polysilicon gate, form mask layer (sacrifice layer), and adopt photoetching process to form the mask graph with First Characteristic size; The method is further included on above-mentioned figure and covers layer of silicon dioxide formation conforma layer, forms the side wall of uniform fold mask graph, and the thickness of side wall upper film is the first thickness; Immediately go photoetching for the second time etching, photoresist covers a part of silicon dioxide conforma layer, the conforma layer of the part of exposure is thinned to the side wall with the second thickness; Anisotropic etching silicon dioxide conforma layer, removes the silicon dioxide of sacrifice layer top and bottom, only leaves the film on sidewall; Adopt oxygen ashing process place to go to be exposed to surperficial mask layer (sacrifice layer); The conforma layer that adopts dry etching etching to carry over, and as hard mask etching polysilicon gate and gate dielectric layer, form grid structure, the size of the grid structure finally obtaining has two kinds, and first size is close to the first thickness, and the second size is close to the second thickness.
By the present invention, can form the spacer with two kinds of thickness by increasing a photoetching; And, by this method, can disposablely etch the figure of two kinds of characteristic sizes, even can unrestrictedly increase the spacer spacer that photoetching number of times forms various thickness, obtain the figure of how different characteristic sizes, meet the actual demand of integrated circuit, significant to the large-scale application of SADP.
The present invention adopts advanced photoetching process to form the figure with First Characteristic size, First Characteristic size is close to the physics limit of photoetching, by adopting the method for two spacer double patterning moulding, the physical restriction of photoetching can be broken, formation is much smaller than the figure of First Characteristic size, by Twi-lithography, obtain the figure of two kinds of ultralow sizes, the figure that meets 20 nanometers and following integrated circuit technology shifts demand.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily to the present invention, there is more complete understanding and more easily understand its advantage of following and feature, wherein:
Fig. 1 to Figure 10 schematically shows respectively sectional view or the vertical view of each step of the method that adopts according to the preferred embodiment of the invention bilateral wall technique to form ultralow size figure.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 to Figure 10 schematically shows respectively sectional view or the vertical view of each step of the method that adopts according to the preferred embodiment of the invention bilateral wall technique to form ultralow size figure.
As shown in Figures 1 to 10, the method that adopts according to the preferred embodiment of the invention bilateral wall technique to form ultralow size figure comprises:
On silicon substrate 1, form silicon nitride (not shown), and on silicon nitride, form amorphous carbon layer (mask layer) 2 (as shown in Figure 1), and adopt photoetching process to form the mask graph (as shown in the sectional view of Fig. 2) with First Characteristic size; Wherein First Characteristic size is formed on or approaches the limit by the optical resolution of high-resolution photomask etching system, and in present stage, the resolution limit of state-of-the-art immersed photoetching machine is of a size of 20-28 nanometer.
On aforementioned mask figure, cover layer of silicon dioxide conforma layer (as shown in the sectional view of the vertical view of Fig. 3 and Fig. 4), after this conforma layer, extended meeting forms the side wall (as shown in the sectional view of Fig. 5) of uniform fold mask graph, and the thickness of side wall upper film is the first thickness;
Immediately carry out photoetching for the second time etching, photoresist 4 covers a part of silicon dioxide conforma layer (as shown in the vertical view of Fig. 6), the conforma layer of the part of exposure 5 is thinned to the side wall (as shown in the vertical view of Fig. 7) with the second thickness;
Remove all photoresists, anisotropically etching silicon dioxide conforma layer, removes the silicon dioxide of mask layer top and bottom, only leaves the silica membrane (as shown in the vertical view of Fig. 8) on sidewall;
Adopt oxygen ashing process place to go to be exposed to surperficial mask layer (sacrifice layer); The silicon dioxide conforma layer that adopts dry etching etching to carry over, and as hard mask etching silicon nitride and silicon substrate, form shallow trench (as shown in the vertical view of the sectional view of Fig. 9 and Figure 10), the shallow trench isolation finally obtaining from the size of active area have two kinds, first size is close to the first thickness, and the second size is close to the second thickness.
In the present invention, the size of the figure obtaining as silicon dioxide or the silicon nitride of final etching mask has two kinds, and two kinds of sizes are not subject to the restriction of the physics limit of photoetching, and only the thickness by side wall determines.
The method that adopts according to the preferred embodiment of the invention bilateral wall technique to form ultralow size figure can advantageously be applied in 20 nanometers and following integrated circuit is manufactured in chemical wet etching technique.For example, said method can be used as the method for the shallow trench that forms patterning in silicon substrate or on substrate, forms the method for the polysilicon gate of patterning.
< concrete technology example >
Concrete technology example according to the embodiment of the present invention is described below, can carries out successively following step:
Adopt thermal oxidation method on silicon substrate, to form the silicon dioxide layer of 3 to 5 nanometers, at silicon dioxide layer, adopt LPCVD to form the silicon nitride layer of 50-80 nano thickness;
On silicon nitride layer, by the method for PECVD, deposit the amorphous carbon layer of 50-200 nano thickness, by decomposing C
2h
2, forming amorphous carbon, technique initialization is: C
2h
2flow be 1500sccm, temperature is 400C, buffer gas He flow is 300-1500sccm, radio frequency is that 13.56Mhz power is 800-1200W, pressure is 10 holders;
Photoetching etching amorphous carbon layer form the figure with First Characteristic size, and this example is of a size of 80 nanometers;
On above-mentioned figure, adopt the method for ald (ALD) to form silicon dioxide conforma layer, technique initialization is: 2Nte flow is 1mgm, and power is 2000-3000W, O
2flow be 3000-4000sccm, the flow of Ar is 1000-2000sccm; The thickness of conforma layer is 15-35 nanometer, and step coverage is 100%;
Carry out photoetching for the second time: spin coating gel method forms one deck positive photoresist, the second device area is developed, retain the first device area photoresist, this example is developed for the drop-down metal-oxide-semiconductor region in 6T-SRAM region, retains the photoresist in transmission metal-oxide-semiconductor region;
Adopt dry etching to carry out attenuate to the conforma layer in the drop-down metal-oxide-semiconductor region of coming out, be thinned to 10 to 25 nanometers, step coverage be 80% and more than;
The anisotropic silicon dioxide conforma layer of getting rid of amorphous carbon top and bottom of using plasma etching, only leaves the silicon dioxide on side wall;
Adopt oxygen ashing process to remove amorphous carbon sacrifice layer, technique initialization is: the flow of O2 is 500-1500sccm, and temperature is 200 degree, and power is 300W;
The residual silicon dioxide conforma layer of take carries out dry etching to substrate as hard mask, form shallow trench isolation from active area, this active area is of a size of the thickness of conforma layer, the first device area (transmission metal-oxide-semiconductor) is of a size of 15-35 nanometer; The second device area (drop-down metal-oxide-semiconductor) is of a size of 10-25 nanometer.
The present invention adopts advanced photoetching process to form the figure with First Characteristic size, First Characteristic size is close to the physics limit of photoetching, by adopting the method for two isolation double patterning moulding, the physical restriction of photoetching can be broken, formation is much smaller than the figure of First Characteristic size, by Twi-lithography, obtain the figure of two kinds of ultralow sizes, the figure that meets 20 nanometers and following integrated circuit technology shifts demand.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as the term in specification " first ", " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., rather than for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (6)
1. adopt bilateral wall technique to form a method for ultralow size figure, it is characterized in that comprising: the mask layer that first utilizes one deck mask to carry out in photoetching for the first time etched substrate has the figure of First Characteristic size with formation; Then on this figure, deposit thin film material layer, form the conforma layer of uniform fold mask graph, the thickness of side wall upper film is the first thickness; Carry out photoetching for the second time etching, wherein photoresist covers a part of thin-film material, and the thin-film material of the part that photoresist is exposed is thinned to the side wall with the second thickness; Remove photoresist, form the figure with two kinds of thickness side walls; Anisotropically etched film material, removes the thin-film material of mask layer top and bottom, only leaves the film on sidewall; Cineration technics is optionally removed mask layer, only leaves the side wall that thin-film material forms; Thin-film material carries out etching as the mask of etching, form the hyperfine figure with two kinds of sizes, and the size of size is corresponding to the first thickness and second thickness of side wall.
2. employing bilateral wall technique according to claim 1 forms the method for ultralow size figure, it is characterized in that, mask layer is amorphous carbon film.
3. employing bilateral wall technique according to claim 1 and 2 forms the method for ultralow size figure, it is characterized in that, First Characteristic size equals the limit of the optical resolution of high-resolution photomask etching system.
4. employing bilateral wall technique according to claim 1 and 2 forms the method for ultralow size figure, it is characterized in that, thin-film material is silicon dioxide or silicon nitride.
5. adopt bilateral wall technique to form a method for ultralow size figure, it is characterized in that comprising: on silicon substrate, form silicon nitride, and on silicon nitride, form mask layer, and adopt photoetching process to form the mask graph with First Characteristic size; On mask graph, cover layer of silicon dioxide and form conforma layer, form the side wall of uniform fold mask graph, the thickness of side wall upper film is the first thickness; Immediately carry out photoetching for the second time etching, photoresist covers a part of silicon dioxide conforma layer, the conforma layer of the part of exposure is thinned to the side wall with the second thickness; Anisotropic etched film material, removes the thin-film material of sacrifice layer top and bottom, only leaves the film on sidewall; Adopt oxygen ashing process place to go to be exposed to surperficial mask layer; The conforma layer that adopts dry etching etching to carry over, and as hard mask etching silicon nitride and silicon substrate, form shallow trench, the shallow trench isolation finally obtaining from the size of active area have two kinds, first size equals the first thickness, the second size equals the second thickness.
6. a method that adopts bilateral wall technique to form ultralow size figure, it is characterized in that comprising: form silicon dioxide gate dielectric layer, form polysilicon gate, and form the mask layer as sacrifice layer on polysilicon gate, and adopt photoetching process to form the mask graph with First Characteristic size; On aforementioned mask figure, cover layer of silicon dioxide and form conforma layer, form the side wall of uniform fold mask graph, the thickness of side wall upper film is the first thickness; Immediately go photoetching for the second time etching, photoresist covers a part of silicon dioxide conforma layer, the conforma layer of the part of exposure is thinned to the side wall with the second thickness; Anisotropic etching silicon dioxide conforma layer, removes the silicon dioxide of sacrifice layer top and bottom, only leaves the film on sidewall; Adopt oxygen ashing process place to go to be exposed to surperficial mask layer; The conforma layer that adopts dry etching etching to carry over, and as hard mask etching polysilicon gate and gate dielectric layer, form grid structure, the size of the grid structure finally obtaining has two kinds, and first size equals the first thickness, and the second size equals the second thickness.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154743A (en) * | 2015-03-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Mask and forming method thereof |
| CN108807170A (en) * | 2018-06-11 | 2018-11-13 | 中国科学院微电子研究所 | A kind of production method of nano wire |
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| KR20090049407A (en) * | 2007-11-13 | 2009-05-18 | 주식회사 하이닉스반도체 | Process for forming pattern of semiconductor device using double exposure |
| CN101436528A (en) * | 2007-11-16 | 2009-05-20 | 东部高科股份有限公司 | Method for fabricating semiconductor device |
| US20120135146A1 (en) * | 2010-11-30 | 2012-05-31 | Jsr Corporation | Methods of forming topographical features using segregating polymer mixtures |
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2014
- 2014-06-09 CN CN201410253948.8A patent/CN103996604B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20090049407A (en) * | 2007-11-13 | 2009-05-18 | 주식회사 하이닉스반도체 | Process for forming pattern of semiconductor device using double exposure |
| CN101436528A (en) * | 2007-11-16 | 2009-05-20 | 东部高科股份有限公司 | Method for fabricating semiconductor device |
| US20120135146A1 (en) * | 2010-11-30 | 2012-05-31 | Jsr Corporation | Methods of forming topographical features using segregating polymer mixtures |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106154743A (en) * | 2015-03-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Mask and forming method thereof |
| CN106154743B (en) * | 2015-03-24 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | Mask and forming method thereof |
| CN108807170A (en) * | 2018-06-11 | 2018-11-13 | 中国科学院微电子研究所 | A kind of production method of nano wire |
| CN108807170B (en) * | 2018-06-11 | 2021-10-22 | 中国科学院微电子研究所 | Method for manufacturing nano wire |
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| CN103996604B (en) | 2016-08-31 |
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