CN103943469A - Self-aligning forming method for figure - Google Patents
Self-aligning forming method for figure Download PDFInfo
- Publication number
- CN103943469A CN103943469A CN201410193181.4A CN201410193181A CN103943469A CN 103943469 A CN103943469 A CN 103943469A CN 201410193181 A CN201410193181 A CN 201410193181A CN 103943469 A CN103943469 A CN 103943469A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon dioxide
- characteristic size
- mask layer
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a self-aligning forming method for a figure. The self-aligning forming method for the figure includes: arranging a mask layer on a substrate; photoetching to enable the mask layer on the substrate to form a first figure with first feature size; depositing a silicon dioxide layer which serves as a conformal layer on the first figure, covering the substrate surface exposed by the first figure, and forming a side wall which uniformly covers the first figure; based on the side wall, depositing a silicon nitride layer which serves as a packing layer, and flattening the packing layer through chemical mechanical polishing to expose the mask layer; removing the silicon nitride layer and keeping the silicon dioxide layer and the mask layer through wet etching; ashing to selectively remove the mask layer and keep the side wall formed by silicon dioxide; using silicon dioxide as etching mask to perform etching to form a second figure with second feature size, wherein the second feature size is smaller than the first feature size.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of figure autoregistration formation method.
Background technology
The characteristic size of very lagre scale integrated circuit (VLSIC) is according to the development of Moore's Law, 20 nanometers and following characteristic size are developed into, to more increasing the capacity of semiconductor device and reducing costs on small size, form and there is better performance, the semiconductor device of lower power consumption.The contraction of the characteristic size of each device needs more complicated technology.
Photoetching process be commonly use device and circuit pattern are transferred to the method on substrate, the width of line and spacing are two parameters the most key in photoetching process.Spacing is defined as the distance between the identical point of two adjacent lines.Due to various factors, as the physical restriction such as optics and light wavelength, existing photoetching technique has minimum spacing and can not meet below 20 nanometers the demand of integrated circuit, can not form by existing photoetching technique lower than the figure of the characteristic size of this particular lithography technique limit.
Therefore, find a kind of method of utilizing existing photoetching technique can meet again characteristic size demand simultaneously just extremely important.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, and a kind of method that can utilize existing photoetching technique can meet again characteristic size demand is simultaneously provided.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, provide a kind of figure autoregistration formation method, comprising: first step, for arrange mask layer on substrate; Second step, for carrying out photoetching so that mask layer on substrate forms first figure with First Characteristic size; Third step, for deposit layer of silicon dioxide as conforma layer on this first figure, covers the substrate surface being come out by the first figure, and forms the side wall of uniform fold the first figure; The 4th step, for depositing one deck silicon nitride as packed layer on the basis forming at this side wall, and carries out planarization by cmp to packed layer, to expose mask layer; The 5th step, for removing silicon nitride by wet etching, leaves silicon dioxide and mask layer; The 6th step, optionally removes mask layer for carrying out cineration technics, only leaves the silicon dioxide of substrate surface and the side wall that silicon dioxide forms; The 7th step, for utilizing silicon dioxide, as etching mask, substrate is carried out to etching, forms and is less than the second graph with the Second Characteristic size that is less than First Characteristic size.
Preferably, Second Characteristic is of a size of the half of First Characteristic size.
Preferably, the thickness of conforma layer 4 90% and First Characteristic size between First Characteristic size 110% between.
Preferably, in the time packed layer being carried out to planarization by cmp, in the time detecting mask layer, stop grinding.
According to a second aspect of the invention, provide a kind of figure autoregistration formation method, having comprised: first step, for arrange mask layer on polysilicon layer; Second step, for carrying out photoetching so that mask layer on polysilicon layer forms first figure with First Characteristic size; Third step, for deposit layer of silicon dioxide on this first figure, covers the polysilicon layer surface of being come out by the first figure, and forms the side wall of uniform fold the first figure; The 4th step, for depositing one deck silicon nitride as packed layer on the basis forming at this side wall, and carries out planarization by cmp to packed layer, to expose mask layer; The 5th step, for removing silicon nitride by wet etching, leaves silicon dioxide and mask layer; The 6th step, optionally removes mask layer for carrying out cineration technics, only leaves the silicon dioxide on polysilicon layer surface and the side wall that silicon dioxide forms; The 7th step, for utilizing silicon dioxide, as etching mask, polysilicon layer is carried out to etching to form polysilicon gate, forms and is less than the second graph with the Second Characteristic size that is less than First Characteristic size.
Brief description of the drawings
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the flow chart of figure autoregistration formation method according to the preferred embodiment of the invention.
Fig. 2 to 9 schematically shows each step of figure autoregistration formation method according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 schematically shows the flow chart of figure autoregistration formation method according to the preferred embodiment of the invention.
Particularly, as shown in Figure 1, figure autoregistration formation method comprises and carries out successively following step according to the preferred embodiment of the invention:
First step S1, for arranging mask layer 2, as shown in Figure 2 on substrate 1;
Second step S2, for for example utilizing mask to carry out photoetching, so that the mask layer on substrate forms first figure 3 with First Characteristic size, as shown in Figure 3; For example, First Characteristic size is formed on or approaches the dimension limit by the optical resolution of high-resolution photomask etching system;
Third step S3, for deposit layer of silicon dioxide as conforma layer 4 on this first figure, covers the substrate surface being come out by the first figure, and forms the side wall of uniform fold the first figure, as shown in Figure 4; Preferably, the thickness of conforma layer 4 is at approximately between 110% of approximately 90% and First Characteristic size between First Characteristic size.
The 4th step S4, for depositing one deck silicon nitride as packed layer 5 (as shown in Figure 5) on the basis forming at this side wall, and carries out planarization by cmp to packed layer, to expose mask layer 2 (as shown in Figure 6); Preferably, can using plasma chemical vapour deposition (CVD) (PECVD) or atomic layer deposition (ALD) or SACVD form silicon nitride, characteristic is to have higher etching selection ratio with silicon dioxide, and thickness requirement covers the planarization that increases a graphics field and try one's best;
And, by cmp, packed layer is being carried out to planarization, preferably amorphous carbon is carried out to terminal detecting, be ground to amorphous carbon and stop grinding, finally make amorphous carbon, silicon nitride and silicon dioxide on a horizontal line.
The 5th step S5, for removing silicon nitride by wet etching, leaves silicon dioxide and mask layer (as shown in Figure 7); The consumption silicon dioxide of trying one's best few when wherein, wet etching is removed silicon nitride;
The 6th step S6, for example, optionally removes mask layer for carrying out cineration technics (, oxygen ashing process), only leaves the silicon dioxide of substrate surface and the side wall (as shown in Figure 8) that silicon dioxide forms; Now, can find out, the side wall that the silicon dioxide of substrate surface and silicon dioxide form has formed multiple U-shaped structures jointly;
The 7th step S7, for utilizing silicon dioxide (, multiple U-shaped structures), as etching mask, substrate is carried out to etching, forms and is less than the second graph (as shown in Figure 9) with the Second Characteristic size that is less than First Characteristic size.
Thus, the present invention only for example can form the figure for the Second Characteristic size of First Characteristic size half.By adopting said method of the present invention the physical restriction of photoetching can be broken, obtain the figure of smaller szie, the figure that meets 20 nanometers and following integrated circuit technology shifts demand.
And, although described principle of the present invention with silicon dioxide and silicon nitride, it may occur to persons skilled in the art that and adopt other materials to realize the present invention.And above-mentioned substrate can become polysilicon layer, to form polysilicon gate by said method.
The example of the embodiment of figure autoregistration formation method according to the preferred embodiment of the invention will be specifically described below.
First, first a substrate that forms figure will be provided, at integrated circuit manufacture field, preferred substrate is silicon chip, can deposition of silica on silicon chip, and polysilicon, other conventional semi-conducting material such as silicon nitride, mask layer is amorphous carbon film preferably, and the thickness of amorphous carbon layer is according to the degree of depth decision of the substrate of wanted etching, and that general is 1.5-2:1.Particularly, for example, can adopt thermal oxidation method on silicon substrate, to form the silicon nitride layer of 3 to 5 nanometers, adopt LPCVD to form the silicon dioxide layer of 50-80 nano thickness at silicon nitride layer.
Can adopt ALD (atomic layer deposition) to form silicon dioxide and carry out coverage mask layer, characteristic requirements is to have higher step coverage, silicon dioxide thickness in requirement mask sidewalls and the silicon dioxide thickness ratio at mask top are greater than 90%, requirement has lower etch rate, particularly compares and has higher etching selection ratio with silicon or polysilicon.
On silicon dioxide layer, deposit the amorphous carbon layer of 50-200 nano thickness by the method for PECVD, by decomposing C2H2, form amorphous carbon, technique initialization is: the flow of C2H2 is 1500sccm, temperature is 400C, buffer gas He flow is 300-1500sccm, and radio frequency is that 13.56Mhz power is 800-1200W, and hold in the palm pressure position 10; Photoetching etching amorphous carbon layer form the figure with First Characteristic size, and this example is of a size of 80 nanometers; The method growth layer of silicon dioxide layer that adopts ALD on above-mentioned figure, thickness is 14-30 nanometer, step coverage is 100%; On above-mentioned conforma layer, be used in and on above-mentioned figure, adopt the method for ald (ALD) to form silicon nitride cover layer, technique initialization is: 2Nte flow is 1mgm, and power is 2000-3000W, and the flow of Ar is 1000-2000sccm; The thickness of conforma layer is 200 nanometers; Adopt cmp to grind above-mentioned film, grind successively titanium dioxide SiClx cover layer, silicon dioxide conforma layer grinds and stops in the time detecting amorphous carbon sacrifice layer, and now three-layer thin-film in the same horizontal line; Adopt wet etching to remove silicon nitride, this example preferably hydrofluoric acid wet etching is removed silicon nitride; Adopt oxygen ashing process to remove amorphous carbon sacrifice layer, technique initialization is: the flow of O2 is 500-1500sccm, and temperature is 200 degree, and power is 300W; Taking residual silicon dioxide conforma layer as hard mask, substrate is carried out to dry etching, form shallow trench, this groove is of a size of the thickness of conforma layer, is about 14-30 nanometer.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as term " first " in specification, " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., instead of for representing logical relation or the ordinal relation etc. between each assembly, element, step.
Be understandable that, although the present invention discloses as above with preferred embodiment, but above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (7)
1. a figure autoregistration formation method, is characterized in that comprising:
First step, for arranging mask layer on substrate;
Second step, for carrying out photoetching so that mask layer on substrate forms first figure with First Characteristic size;
Third step, for deposit layer of silicon dioxide as conforma layer on this first figure, covers the substrate surface being come out by the first figure, and forms the side wall of uniform fold the first figure;
The 4th step, for depositing one deck silicon nitride as packed layer on the basis forming at this side wall, and carries out planarization by cmp to packed layer, to expose mask layer;
The 5th step, for removing silicon nitride by wet etching, leaves silicon dioxide and mask layer;
The 6th step, optionally removes mask layer for carrying out cineration technics, only leaves the silicon dioxide of substrate surface and the side wall that silicon dioxide forms;
The 7th step, for utilizing silicon dioxide, as etching mask, substrate is carried out to etching, forms and is less than the second graph with the Second Characteristic size that is less than First Characteristic size.
2. figure autoregistration formation method according to claim 1, is characterized in that, Second Characteristic is of a size of the half of First Characteristic size.
3. figure autoregistration formation method according to claim 1 and 2, is characterized in that, the thickness of conforma layer 90% and First Characteristic size between First Characteristic size 110% between.
4. figure autoregistration formation method according to claim 1 and 2, is characterized in that, in the time packed layer being carried out to planarization by cmp, stops grinding in the time detecting mask layer.
5. a figure autoregistration formation method, is characterized in that comprising:
First step, for arranging mask layer on polysilicon layer;
Second step, for carrying out photoetching so that mask layer on polysilicon layer forms first figure with First Characteristic size;
Third step, for deposit layer of silicon dioxide on this first figure, covers the polysilicon layer surface of being come out by the first figure, and forms the side wall of uniform fold the first figure;
The 4th step, for depositing one deck silicon nitride as packed layer on the basis forming at this side wall, and carries out planarization by cmp to packed layer, to expose mask layer;
The 5th step, for removing silicon nitride by wet etching, leaves silicon dioxide and mask layer;
The 6th step, optionally removes mask layer for carrying out cineration technics, only leaves the silicon dioxide on polysilicon layer surface and the side wall that silicon dioxide forms;
The 7th step, for utilizing silicon dioxide, as etching mask, polysilicon layer is carried out to etching to form polysilicon gate, forms and is less than the second graph with the Second Characteristic size that is less than First Characteristic size.
6. figure autoregistration formation method according to claim 5, is characterized in that, Second Characteristic is of a size of the half of First Characteristic size.
7. according to the figure autoregistration formation method described in claim 5 or 6, it is characterized in that, the thickness of conforma layer 90% and First Characteristic size between First Characteristic size 110% between.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410193181.4A CN103943469A (en) | 2014-05-08 | 2014-05-08 | Self-aligning forming method for figure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410193181.4A CN103943469A (en) | 2014-05-08 | 2014-05-08 | Self-aligning forming method for figure |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103943469A true CN103943469A (en) | 2014-07-23 |
Family
ID=51191083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410193181.4A Pending CN103943469A (en) | 2014-05-08 | 2014-05-08 | Self-aligning forming method for figure |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103943469A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107403719A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造(天津)有限公司 | The method for forming figure in the semiconductor device |
CN108321079A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN112462470A (en) * | 2020-10-27 | 2021-03-09 | 中国科学院微电子研究所 | Method for manufacturing silicon-based photonic device by side wall transfer and silicon-based photonic device |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
US20080090419A1 (en) * | 2006-10-17 | 2008-04-17 | Cha-Won Koh | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same |
US20080131793A1 (en) * | 2006-03-06 | 2008-06-05 | Samsung Electronics Co., Ltd. | Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same |
CN101471231A (en) * | 2007-12-27 | 2009-07-01 | 海力士半导体有限公司 | Method of forming a micro pattern of a semiconductor device |
US7935464B2 (en) * | 2008-10-30 | 2011-05-03 | Applied Materials, Inc. | System and method for self-aligned dual patterning |
CN102446703A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
US20130113085A1 (en) * | 2011-11-04 | 2013-05-09 | Applied Materials, Inc. | Atomic Layer Deposition Of Films Using Precursors Containing Hafnium Or Zirconium |
CN103367258A (en) * | 2012-04-06 | 2013-10-23 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
CN103594336A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Double patterning method |
-
2014
- 2014-05-08 CN CN201410193181.4A patent/CN103943469A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
US20080131793A1 (en) * | 2006-03-06 | 2008-06-05 | Samsung Electronics Co., Ltd. | Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same |
US20080090419A1 (en) * | 2006-10-17 | 2008-04-17 | Cha-Won Koh | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same |
CN101471231A (en) * | 2007-12-27 | 2009-07-01 | 海力士半导体有限公司 | Method of forming a micro pattern of a semiconductor device |
US7935464B2 (en) * | 2008-10-30 | 2011-05-03 | Applied Materials, Inc. | System and method for self-aligned dual patterning |
CN102446703A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Dual patterning method |
US20130113085A1 (en) * | 2011-11-04 | 2013-05-09 | Applied Materials, Inc. | Atomic Layer Deposition Of Films Using Precursors Containing Hafnium Or Zirconium |
CN103367258A (en) * | 2012-04-06 | 2013-10-23 | 力晶科技股份有限公司 | Semiconductor circuit structure and manufacturing process thereof |
CN103594336A (en) * | 2012-08-13 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Double patterning method |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107403719A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造(天津)有限公司 | The method for forming figure in the semiconductor device |
CN108321079A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US10825690B2 (en) | 2017-01-16 | 2020-11-03 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor structures |
CN108321079B (en) * | 2017-01-16 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN112462470A (en) * | 2020-10-27 | 2021-03-09 | 中国科学院微电子研究所 | Method for manufacturing silicon-based photonic device by side wall transfer and silicon-based photonic device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104733291B (en) | Method for integrated circuit patterns | |
US10170327B2 (en) | Fin density control of multigate devices through sidewall image transfer processes | |
CN105609421B (en) | Semiconductor device with self-aligned gate structure and method of manufacturing the same | |
US20200091336A1 (en) | Forming a sacrificial liner for dual channel devices | |
CN103943468A (en) | Self-aligning forming method for figure | |
US20140210004A1 (en) | Self-adjusting gate hard mask | |
CN105161450A (en) | Double-shallow-trench isolation forming method | |
CN103594337A (en) | A dual patterning method | |
CN103943469A (en) | Self-aligning forming method for figure | |
US9570358B2 (en) | Nano wire structure and method for fabricating the same | |
CN108155088A (en) | The method for removing etching mask | |
CN103456609A (en) | Method for forming nanowire through gate-all-around device | |
CN102760751A (en) | Structure of semiconductor device and formation method | |
CN102800576B (en) | The method of graphic diaphragm layer, the method for grid, MOS transistor of being formed | |
CN103996604B (en) | A kind of method using bilateral wall technique to form ultralow size figure | |
US10600687B2 (en) | Process integration techniques using a carbon layer to form self-aligned structures | |
US20130207168A1 (en) | Photodiode employing surface grating to enhance sensitivity | |
CN105304474A (en) | Formation method of multi-patterning mask layer | |
CN108091553B (en) | Method for forming mask pattern | |
CN105161409A (en) | Method for forming U-shaped gate | |
CN103996602B (en) | A kind of method using bilateral wall technique to form ultralow size figure | |
CN104916591A (en) | Manufacturing method of semiconductor device | |
CN104157553A (en) | Double patterning forming method | |
CN109427556A (en) | The fine island-shaped pattern forming method of semiconductor element | |
CN105789208B (en) | Memory element and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140723 |