CN103594337A - A dual patterning method - Google Patents
A dual patterning method Download PDFInfo
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- CN103594337A CN103594337A CN201210289337.XA CN201210289337A CN103594337A CN 103594337 A CN103594337 A CN 103594337A CN 201210289337 A CN201210289337 A CN 201210289337A CN 103594337 A CN103594337 A CN 103594337A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
Abstract
Provided is a dual patterning method. The method comprises providing a substrate on which an etching layer and a first mask layer arranged on the etching layer are successively formed; patterning the first mask layer and forming a first groove; forming first mask materials on the bottom and the sidewall of the first groove and forming a second groove between the first mask materials in the first groove; fully filling the second groove with second mask material; removing the second mask material and a part or all first mask materials between the first mask layer with first ashing technology; and etching the etching layer by using the patterned first mask layer and the second mask material as masks. The dual patterning method may achieve better pattern transfer effect.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of Double-patterning method.
Background technology
In order to improve the device density on chip, autoregistration Dual graphing technology has been used in nand flash memory manufacturing process.A kind of method of autoregistration Dual graphing that as open day has been August 27 in 2009 and the patent publication No. U.S. Patent Application Publication that is US2009/0215272A1.
Fig. 1 ~ 4 are the intermediate structure schematic diagram of Double-patterning method in prior art.Double-patterning method of the prior art comprises: as shown in Figure 1, substrate 10 is provided, on described substrate, form successively the first silicon nitride layer 20, oxide skin(coating) 30, the first polysilicon layer 40 and the second silicon nitride layer 50, wherein said the first silicon nitride layer 20 and oxide skin(coating) 30 are etch layer; As shown in Figure 2, take patterned photoresist as the first polysilicon layer 40 described in mask (not shown) etching and the second silicon nitride layer 50, form patterned the first polysilicon layer 40a, patterned the second silicon nitride layer 50a and a plurality of the first groove 51; As shown in Figure 3, form the second polysilicon layer 60, described the second polysilicon layer 60 covers the upper surface of described patterned the second silicon nitride layer 50a, bottom surface and the sidewall of described the first groove 51, and is formed with the second groove 52 between the second polysilicon layer 60 in described groove 51; As shown in Figure 4, in described the second groove 52, fill out silicon nitride material 70, described silicon nitride material 70 covers described the second polysilicon layer 60, and fills up described the second groove 52; As shown in Figure 5, grind described the second polysilicon layer 60 and described silicon nitride material 70, stop at the upper surface of described the second silicon nitride layer 50a after graphical; As shown in Fig. 6 and Fig. 5, remove the silicon nitride material 70 in patterned the second silicon nitride layer 50a and described the second groove 52; And second polysilicon layer 60 higher than the second bottom portion of groove of take after described polishing, second polysilicon layer 60 that is mask etching is positioned at described the second bottom portion of groove, described the first polysilicon layer 40a, described the first silicon nitride layer 20 and oxide skin(coating) 30 after graphical.
Yet, in said method, as shown in Figure 5 and Figure 6, during silicon nitride in the silicon nitride material 70 in removing patterned the second silicon nitride layer 50a and described the second groove 52, because the etching selection ratio between described silicon nitride and the second polysilicon layer 60 is not high, may make the shape of the second polysilicon layer 60 sustain damage, thus cause follow-up take higher than the second polysilicon layer 60 of the second bottom portion of groove as the effect that mask carries out figure transfer also undesirable.
Therefore, a kind of new Double-patterning method need to be proposed, better figure transfer effect can be realized.
Summary of the invention
The problem that the present invention solves is to provide a kind of new Double-patterning method, can avoid the figure of mask layer in figure transfer process to occur damage.
For addressing the above problem, the embodiment of the present invention provides a kind of Double-patterning method, comprising: substrate is provided, is formed with successively etch layer and is positioned at the first mask layer in etch layer on described substrate; Graphical described the first mask layer, forms the first groove; On the bottom of described the first groove and sidewall, form the first mask material, between the first mask material in described the first groove, form the second groove; In described the second groove, fill up the second mask material; Adopt the first cineration technics to remove part or all of the first mask material between described the second mask material and described the first mask layer; And to take described patterned the first mask layer and described the second mask material be mask, etch layer described in etching.
Alternatively, the first mask material is amorphous carbon.
Alternatively, between described etch layer and the first mask layer, be also formed with the second mask layer that can remove by cineration technics.
Alternatively, described Double-patterning method also comprises: after graphical described the first mask layer, continue graphical described the second mask layer, form the first groove.
Alternatively, the material of described the second mask layer is amorphous carbon.
Alternatively, on the bottom of described the first groove and sidewall, form the first mask material, and the method for filling up the second mask material in described the second groove comprises: deposit the first mask material, described the first mask material covers bottom and the sidewall of described patterned the first mask layer, the first groove, between the first mask material in described the first groove, forms the second groove; Deposit the second mask material, cover described the first mask material and fill up described the second groove; And the first mask material and described the second mask material described in planarization, stop at the upper surface of patterned the first mask layer.
Alternatively, described in planarization, the technique of the first mask material and described the second mask material is chemical mechanical milling tech or dry etch process.
Alternatively, described the first cineration technics carries out in inductively coupled plasma reaction chamber or capacitively coupled plasma reactor chamber, temperature is for being less than 300 degrees Celsius, and the gas of employing is mist, oxygen or the carbon monoxide of nitrogen and hydrogen and the mist of carbon dioxide.
Alternatively, described Double-patterning method also comprises: after etch layer described in etching, utilize the second cineration technics to remove the second mask layer, make between described etch layer and described patterned the first mask layer and the second mask material separated; And remove described patterned the first mask layer and the second mask material.
Alternatively, described the second cineration technics carries out in inductively coupled plasma reaction chamber or capacitively coupled plasma reactor chamber, temperature is for being less than 300 degrees Celsius, and the gas of employing is mist, oxygen or the carbon monoxide of nitrogen and hydrogen and the mist of carbon dioxide.
Alternatively, described etch layer is single layer structure or sandwich construction.
Alternatively, when described etch layer is double-layer structure, described etch layer comprises silicon oxide layer and is positioned at the silicon nitride layer on described silicon oxide layer.
Alternatively, described the first mask layer is antireflecting coating.
Alternatively, the material of described the first mask layer is silicon nitride or siliceous polymer.
Alternatively, described the second mask material is silicon nitride or siliceous polymer.
Alternatively, the material of described substrate is polysilicon.
Compared with prior art, embodiments of the invention have the following advantages:
In embodiments of the present invention, directly by cineration technics, remove the first mask material being clipped between patterned the first mask layer and the second mask material, on the one hand without the etching selection ratio of considering between the first mask material and the first mask layer and the second mask material, reduce the damage that figure is subject in transfer process, thereby obtain better figure transfer effect.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the intermediate structure schematic diagram of Double-patterning method in prior art;
Fig. 7 is the flow chart of the Double-patterning method of one embodiment of the invention; And
Fig. 8 to Figure 16 is the intermediate structure schematic diagram of Double-patterning method in one embodiment of the invention.
Embodiment
In existing Dual graphing technology, because the etching selection ratio between selected materials is not high, thereby in figure transfer process, occur that figure destroys and the problem of damage.
For the problems referred to above, embodiments of the invention provide a kind of Double-patterning method.Fig. 7 is the flow chart of the Double-patterning method of one embodiment of the invention.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Lower mask body is in conjunction with Fig. 8 to Figure 16, and the technical scheme that the embodiment of the present invention is provided is described in detail.
First, please refer to Fig. 8, execution step S1, provides substrate 100, is formed with successively etch layer 200 and the first mask layer 400 on described substrate 100.Wherein, described the first mask layer 400 is positioned in described etch layer 200.
In an embodiment of the present invention, the material of described substrate 100 can be polysilicon, but is not limited to this.
Described etch layer 200 can be single layer structure or the two-layer above two-layer sandwich construction that comprises, in an embodiment of the present invention, as shown in Figure 8, described etch layer 200 comprises double-layer structure, be respectively silicon nitride 201 and be positioned at the silicon oxide layer 202 on silicon nitride layer 201, below the described double-layer structure of all take is described as example, but is not limited to double-layer structure.
Described the first mask layer can be antireflecting coating, and the material of described the first mask layer can comprise silicon nitride or siliceous polymer, but is not limited to this.
In an embodiment of the present invention, please refer to Fig. 9, between described etch layer 200 and the first mask layer 400, can also be formed with the second mask layer 300, the material of described the second mask layer 300 can be the material that can remove by cineration technics, amorphous carbon for example, but be not limited to this.
It should be noted that, because the second mask layer 300 being between described etch layer 200 and the first mask layer 400 can be removed by ashing, therefore follow-uply after figure is transferred to described etch layer 200, can remove the separated described etch layer 200 of described the second mask layer 300 and described the first mask layer 400 by cineration technics, thereby can remove more easily described the first mask layer 400.The semiconductor structure that is formed with described the second mask layer 300 of all take below describes the technical scheme that the embodiment of the present invention was provided as example.
The formation technique of described etch layer 200, the first mask layer 400 and the second mask layer 300 can be chemical vapor deposition method respectively.
Then, please refer to Figure 10, execution step S2, graphical described the first mask layer 400, to form the first groove.In an embodiment of the present invention, also graphically described the first mask layer 400 and the second mask layer 300, to form the first groove 401.Below with graphical described the first mask layer 400 and the second mask layer 300, form the first groove 401 and technical scheme of the present invention is described for example.
As shown in Figure 9 and Figure 10, the method of graphical described the second mask layer 300 and the first mask layer 400 can comprise: the patterned photoresist (not shown) of take is mask, the first mask layer 400 and the second mask layer 300 described in etching, form patterned the first mask layer 400a, patterned the second mask layer 300a and the first groove 401, patterned the first mask layer 400a and patterned the second mask layer 300a define the first groove 401.Wherein, described in etching, the technique of the first mask layer 400 and the second mask layer 300 is dry etch process.
In other embodiments of the invention, also can adopt additive method or technique to come graphical described the first mask layer 400 and the second mask layer 300.
Then, please refer to Figure 11, execution step S3, form the first mask material, described the first mask material 500 covers the upper surface of described patterned the first mask layer 400a, bottom and the sidewall of described the first groove 401, described the first mask material 500 does not fill up described the first groove 401, and forms the second groove 501 between the first mask material 500 in the opposing sidewalls of described the first groove 401.Wherein, the formation technique of described the first mask material 500 can be chemical vapor deposition method.
In embodiments of the present invention, the material of described the first mask material 500 can be identical with described the second mask layer 300, for example, comprise amorphous carbon.In other embodiments of the invention, the material of described the first mask material 500 also can with described the second mask layer 300 differences, can be other materials applicatory that can remove by cineration technics.
Then, please refer to Figure 12, execution step S4, forms the second mask material 600, and described the second mask material 600 covers described the first mask material 500 and fills up described the second groove 501.Wherein, the formation technique of described the second mask material 600 can be chemical vapor deposition method.
In an embodiment of the present invention, the material of described the second mask material 600 can be identical with the first mask layer 400, for example, comprise silicon nitride or siliceous polymer.In other embodiments of the invention, the material of described the second mask material 600 also can with the first mask layer 400 differences, can be other hard mask materials applicatory.
Then, please refer to Figure 13, execution step S5, the first mask material 500 and described the second mask material 600 described in planarization, stop at the upper surface of described patterned the first mask layer 400a.
In embodiments of the present invention, described in described planarization, the technique of the second mask material 600 in the first mask material 500 and described the second groove 501 is chemical mechanical milling tech or dry etch process.
Then, please refer to Figure 14, execution step S6, removes and is clipped in part or all of the first mask material 500 between described patterned the first mask layer 400a and the second mask material 600.
In embodiments of the present invention, removing the technique be clipped in the first mask material 500 between described patterned the first mask layer 400a and the second mask material 600 is cineration technics.In an embodiment of the present invention, described cineration technics carries out in inductively coupled plasma reaction chamber or capacitively coupled plasma reactor chamber, temperature is for being less than 300 degrees Celsius, and the gas of employing is mist, oxygen or the carbon monoxide of nitrogen and hydrogen and the mist of carbon dioxide.
It should be noted that, the removal amount that is clipped in the first mask material 500 between described patterned the first mask layer 400a and the second mask material 600 can be controlled according to the time of cineration technics, can remainder the first mask material 500 between described patterned the first mask layer 400a and the second mask material 600.In order not destroy the first mask material below the second bottom portion of groove, and the figure transfer effect of having guaranteed, the selection of optimizing is only to remove the first mask material 500 higher than described the second bottom portion of groove, below describes to take only removal and describe as example higher than the first mask material 500 of described the second groove 501 bottoms.
In addition, it should be noted that, directly by cineration technics, remove the first mask material 500 being clipped between patterned the first mask layer 400a and the second mask material 600, without the etching selection ratio of considering between the first mask material 500 and patterned the first mask layer 400a and the second mask material 600, reduce the damage that figure is subject in transfer process, thereby obtain better figure transfer effect.
Then, please refer to Figure 15, execution step S7, described the first mask layer 400a and the second mask material 600 after graphical of take is mask, remaining the first mask material 500 of etching the second bottom portion of groove and etch layer 200, to be transferred to figure described etch layer 200.
As shown in Figure 15 and Figure 16, after figure being transferred to described etch layer 200, the Double-patterning method that the embodiment of the present invention provides can also comprise: utilize cineration technics to remove patterned the second mask layer 300a, thereby make separation between etch layer and described patterned the first mask layer 400a and the second mask material 600, so just can easily described patterned the first mask layer 400a and the second mask material 600 be removed again.The method is fairly simple, easily operation.In an embodiment of the present invention, described cineration technics carries out in inductively coupled plasma reaction chamber or capacitively coupled plasma reactor chamber, temperature is for being less than 300 degrees Celsius, and the gas of employing is mist, oxygen or the carbon monoxide of nitrogen and hydrogen and the mist of carbon dioxide.
In sum, embodiments of the invention have the following advantages:
In embodiments of the present invention, directly by cineration technics, remove the first mask material being clipped between patterned the first mask layer and the second mask material, on the one hand without the etching selection ratio of considering between the first mask material and the first mask layer and the second mask material, reduce the damage that figure is subject in transfer process, thereby obtain better figure transfer effect.
On the other hand, figure is being transferred to after described etch layer, can also recycle cineration technics and remove described patterned the second mask layer, thereby make separation between etch layer and described patterned the first mask layer and the second mask material, so just can easily described patterned the first mask layer and the second mask material be removed.The method is fairly simple, easily operation.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (16)
1. a Double-patterning method, is characterized in that, comprising:
Substrate is provided, on described substrate, is formed with successively etch layer and is positioned at the first mask layer in etch layer;
Graphical described the first mask layer, forms the first groove;
On the bottom of described the first groove and sidewall, form the first mask material, between the first mask material in described the first groove, form the second groove;
In described the second groove, fill up the second mask material;
Adopt the first cineration technics to remove part or all of the first mask material between described the second mask material and described the first mask layer; And
Take described patterned the first mask layer and described the second mask material is mask, etch layer described in etching.
2. Double-patterning method as claimed in claim 1, is characterized in that, the first mask material is amorphous carbon.
3. Double-patterning method as claimed in claim 1, is characterized in that, between described etch layer and the first mask layer, is also formed with the second mask layer that can remove by cineration technics.
4. Double-patterning method as claimed in claim 3, is characterized in that, after graphical described the first mask layer, continues graphical described the second mask layer, forms the first groove.
5. Double-patterning method as claimed in claim 3, is characterized in that, the material of described the second mask layer is amorphous carbon.
6. Double-patterning method as claimed in claim 1, is characterized in that, on the bottom of described the first groove and sidewall, forms the first mask material, and the method for filling up the second mask material in described the second groove comprises:
Deposit the first mask material, described the first mask material covers bottom and the sidewall of described patterned the first mask layer, the first groove, between the first mask material in described the first groove, forms the second groove;
Deposit the second mask material, cover described the first mask material and fill up described the second groove; And
The first mask material and described the second mask material described in planarization, stop at the upper surface of patterned the first mask layer.
7. Double-patterning method as claimed in claim 6, is characterized in that, the technique of the first mask material and described the second mask material is chemical mechanical milling tech or dry etch process described in planarization.
8. Double-patterning method as claimed in claim 1, it is characterized in that, described the first cineration technics carries out in inductively coupled plasma reaction chamber or capacitively coupled plasma reactor chamber, temperature is for being less than 300 degrees Celsius, and the gas of employing is mist, oxygen or the carbon monoxide of nitrogen and hydrogen and the mist of carbon dioxide.
9. Double-patterning method as claimed in claim 3, it is characterized in that, also comprise: after etch layer described in etching, utilize the second cineration technics to remove the second mask layer, make between described etch layer and described patterned the first mask layer and the second mask material separated; And remove described patterned the first mask layer and the second mask material.
10. Double-patterning method as claimed in claim 9, it is characterized in that, described the second cineration technics carries out in inductively coupled plasma reaction chamber or capacitively coupled plasma reactor chamber, temperature is for being less than 300 degrees Celsius, and the gas of employing is mist, oxygen or the carbon monoxide of nitrogen and hydrogen and the mist of carbon dioxide.
11. Double-patterning methods as claimed in claim 1, is characterized in that, described etch layer is single layer structure or sandwich construction.
12. Double-patterning methods as claimed in claim 11, is characterized in that, when described etch layer is double-layer structure, described etch layer comprises silicon oxide layer and is positioned at the silicon nitride layer on described silicon oxide layer.
13. Double-patterning methods as claimed in claim 1, is characterized in that, described the first mask layer is antireflecting coating.
14. Double-patterning methods as claimed in claim 1, is characterized in that, the material of described the first mask layer is silicon nitride or siliceous polymer.
15. Double-patterning methods as claimed in claim 1, is characterized in that, described the second mask material is silicon nitride or siliceous polymer.
16. Double-patterning methods as claimed in claim 1, is characterized in that, the material of described substrate is polysilicon.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104900495A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned double patterning method and fin field effect transistor manufacturing method |
CN106373880A (en) * | 2015-07-22 | 2017-02-01 | 联华电子股份有限公司 | Semiconductor element and formation method thereof |
CN106960784A (en) * | 2017-03-30 | 2017-07-18 | 合肥智聚集成电路有限公司 | Semiconductor devices and preparation method thereof |
CN109427578A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN112447603A (en) * | 2019-08-30 | 2021-03-05 | 长鑫存储技术有限公司 | Method for forming semiconductor memory |
CN112768351A (en) * | 2019-11-06 | 2021-05-07 | 长鑫存储技术有限公司 | Pattern forming method |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070148968A1 (en) * | 2005-12-26 | 2007-06-28 | Samsung Electronics Co., Ltd. | Method of forming self-aligned double pattern |
US20080090418A1 (en) * | 2006-10-17 | 2008-04-17 | Jeon Kyung-Yub | Method for forming fine patterns of a semiconductor device using double patterning |
US20090163030A1 (en) * | 2007-12-18 | 2009-06-25 | Mitsuhiro Omura | Semiconductor device manufacturing method |
-
2012
- 2012-08-14 CN CN201210289337.XA patent/CN103594337B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070148968A1 (en) * | 2005-12-26 | 2007-06-28 | Samsung Electronics Co., Ltd. | Method of forming self-aligned double pattern |
US20080090418A1 (en) * | 2006-10-17 | 2008-04-17 | Jeon Kyung-Yub | Method for forming fine patterns of a semiconductor device using double patterning |
US20090163030A1 (en) * | 2007-12-18 | 2009-06-25 | Mitsuhiro Omura | Semiconductor device manufacturing method |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104900495A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned double patterning method and fin field effect transistor manufacturing method |
CN104900495B (en) * | 2014-03-04 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of self-alignment duplex pattern method and fin formula field effect transistor |
CN106373880A (en) * | 2015-07-22 | 2017-02-01 | 联华电子股份有限公司 | Semiconductor element and formation method thereof |
CN106373880B (en) * | 2015-07-22 | 2021-05-25 | 联华电子股份有限公司 | Semiconductor device and method for forming the same |
CN106960784A (en) * | 2017-03-30 | 2017-07-18 | 合肥智聚集成电路有限公司 | Semiconductor devices and preparation method thereof |
CN109427578A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN112447603A (en) * | 2019-08-30 | 2021-03-05 | 长鑫存储技术有限公司 | Method for forming semiconductor memory |
CN112447603B (en) * | 2019-08-30 | 2023-12-19 | 长鑫存储技术有限公司 | Method for forming semiconductor memory |
CN112768351A (en) * | 2019-11-06 | 2021-05-07 | 长鑫存储技术有限公司 | Pattern forming method |
CN112768351B (en) * | 2019-11-06 | 2022-06-10 | 长鑫存储技术有限公司 | Pattern forming method |
CN113078105A (en) * | 2021-03-29 | 2021-07-06 | 长鑫存储技术有限公司 | Preparation method of mask structure, semiconductor structure and preparation method thereof |
CN113078105B (en) * | 2021-03-29 | 2022-07-05 | 长鑫存储技术有限公司 | Preparation method of mask structure, semiconductor structure and preparation method thereof |
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