CN103996604B - A kind of method using bilateral wall technique to form ultralow size figure - Google Patents
A kind of method using bilateral wall technique to form ultralow size figure Download PDFInfo
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- CN103996604B CN103996604B CN201410253948.8A CN201410253948A CN103996604B CN 103996604 B CN103996604 B CN 103996604B CN 201410253948 A CN201410253948 A CN 201410253948A CN 103996604 B CN103996604 B CN 103996604B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Abstract
A kind of method using bilateral wall technique to form ultralow size figure, including: utilize the mask layer that a layer mask version carries out in photoetching for the first time etched substrate to form the figure with fisrt feature size；Depositing thin film material layer on this figure, form the conforma layer of uniform fold mask graph, on side wall, the thickness of thin film is the first thickness；Carrying out second time photoetching and etch, wherein photoresist covers a part of thin-film material, and the thin-film material of the part exposed by photoresist is thinned to the side wall with the second thickness；Remove photoresist, form the figure with two kinds of thickness side walls；Anisotropically etch thin-film material, the thin-film material of mask layer top and bottom is removed, leaves behind the thin film on sidewall；Cineration technics optionally removes mask layer, leaves behind the side wall that thin-film material is formed；Thin-film material performs etching as the mask of etching, forms the hyperfine figure with two kinds of sizes, and the size of size corresponds to the first thickness and second thickness of side wall.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of self aligned formation hyperfine feature chi
The method of very little figure.Bilateral wall technique is used to form ultralow dimensional drawing it is more particularly related to a kind of
The method of shape.
Background technology
The characteristic size of super large-scale integration according to the development of Moore's Law, have evolved to 20 nanometers and
Following characteristic size, in order to increase the capacity of semiconductor device on less area and reduce cost, is formed
There is better performance, the semiconductor device of lower power consumption.The contraction of the characteristic size of each device needs
More complicated technology.Photoetching process is the conventional method transferring on substrate by device and circuit pattern, line
Width and spacing are two parameters the most key in photoetching process.Spacing is defined as the phase of two adjacent lines
With the distance between putting.Due to various factors, such as the physical restriction such as wavelength of optics and light, existing photoetching
Technology has minimum spacing can not meet the demand of integrated circuit below 20 nanometers, less than this specific photoetching
The figure of the characteristic size of technological limit can not be formed by existing photoetching technique.Therefore, one is found
The method that can meet again characteristic size demand while of utilizing existing photoetching technique is the most extremely important.
Self aligned secondary graphical method is to be widely studied in recent years and the figure of very likely large-scale production
Transfer techniques, with it, disclosure satisfy that the figure transfer demand of below 20 nanometers, not by photoetching work
The physics of skill and the restriction of the equipment limit.
But the width of the spacer that self aligned secondary graphical method obtains (thickness of conforma layer) is unique
, the size of the figure so obtained also is unique, but in actual Application of integrated circuit, especially
It is in logic circuit, SRAM circuit, it is desirable to have the active area of different characteristic size, different characteristic size
Grid etc..
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that Yi Zhongneng
Enough use the method that bilateral wall technique forms ultralow size figure.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of employing bilateral wall technique is formed super
First the method for low dimensional figure, comprising: carry out photoetching for the first time etch mask layer by a layer mask version
(amorphous carbon sacrifice layer) forms the figure with fisrt feature size (this is closely sized to the physics limit of photoetching)
Shape；Then on this figure, deposit thin film material layer, form the side wall of uniform fold mask graph, side wall
The thickness of upper thin film is the first thickness；Carrying out second time photoetching and etch, photoresist covers a part of material,
The thin-film material of the part of exposure is thinned to the side wall with the second thickness；Removing photoresist, formation has
The figure of two kinds of thickness side walls；Anisotropic etching thin-film material, by mask layer top and the thin film of bottom
Thin-film material is removed, and leaves behind the thin film on sidewall；Cineration technics optionally removes hard mask (sacrifice layer),
Leave behind the side wall that material is formed；Thin-film material performs etching as the mask of etching, is formed and has two kinds of chis
Very little hyperfine figure, and the size of size is close to the first thickness of side wall and the second thickness.
In one embodiment, the method for the shallow trench forming patterning in a silicon substrate includes: at silicon substrate
Upper formation silicon nitride, and form mask layer (sacrifice layer) on silicon nitride, and use photoetching process formation to have
The mask graph of fisrt feature size；The method further includes at covering layer of silicon dioxide on above-mentioned figure
Forming conforma layer, form the side wall of uniform fold mask graph, on side wall, the thickness of thin film is the first thickness；
Immediately row second time photoetching etching, photoresist covers a part of silicon dioxide conforma layer, the part that will expose
Conforma layer be thinned to the side wall with the second thickness；Anisotropic etching thin-film material, by sacrifice layer top
The thin-film material of portion and bottom is removed, and leaves behind the thin film on sidewall；Oxygen ashing process place to go is used to expose
Mask layer (sacrifice layer) on surface；Dry etching is used to etch the conforma layer carried over, and as firmly covering
Mould etch silicon nitride and silicon substrate, form shallow trench, the size of the active area of the shallow trench finally obtained isolation
Having two kinds, first size is close to the first thickness, and second is closely sized in the second thickness.
The method of the polysilicon gate forming patterning in another embodiment on substrate includes: form titanium dioxide
Silicon oxide gate dielectric layer, forms polysilicon gate, and forms mask layer (sacrifice layer) on polysilicon gate, and use light
Carving technology forms the mask graph with fisrt feature size；The method further includes at above-mentioned figure overlying
Lid layer of silicon dioxide forms conforma layer, forms the side wall of uniform fold mask graph, the thickness of thin film on side wall
Degree is the first thickness；Immediately row second time photoetching etching, photoresist covers a part of silicon dioxide conforma layer,
The conforma layer of the part of exposure is thinned to the side wall with the second thickness；Anisotropic etching silicon dioxide
Conforma layer, removes the silicon dioxide of sacrifice layer top and bottom, leaves behind the thin film on sidewall；Use oxygen
Gas cineration technics place to go is exposed to the mask layer (sacrifice layer) on surface；Dry etching etching is used to carry over
Conforma layer, and as hard mask etches polycrystalline Si-gate and gate dielectric layer, form grid structure, finally obtain
The size of grid structure has two kinds, and first size is close to the first thickness, and second is closely sized in the second thickness.
By the invention it is possible to be once lithographically formed the spacer with two kinds of thickness by increasing；And,
By this method, the figure of two kinds of characteristic sizes can disposably be etched, it might even be possible to unrestrictedly increase
Photoetching number of times forms the spacer spacer of various thickness, obtains the figure of more different characteristic size, full
The actual demand of foot integrated circuit, significant to the large-scale application of SADP.
The present invention uses advanced photoetching process to form the figure with fisrt feature size, and fisrt feature size connects
It is bordering on the physics limit of photoetching, can be by the physics of photoetching by the method using double spacer double patterning molding
Restriction is broken, and forms the figure much smaller than fisrt feature size, obtains two kinds of ultralow sizes by Twi-lithography
Figure, meet the figure transfer demand of 20 nanometers and following integrated circuit technology.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete
Understand and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 to Figure 10 schematically show employing bilateral wall technique according to the preferred embodiment of the invention
Form sectional view or the top view of each step of the method for ultralow size figure.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent structure
Accompanying drawing may be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicate identical or
The label that person is similar to.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings to this
Bright content is described in detail.
Fig. 1 to Figure 10 schematically show employing bilateral wall technique according to the preferred embodiment of the invention
Form sectional view or the top view of each step of the method for ultralow size figure.
As shown in Figures 1 to 10, bilateral wall technique is used to form ultralow chi according to the preferred embodiment of the invention
The method of very little figure includes:
Silicon substrate 1 is formed silicon nitride (not shown), and forms amorphous carbon layer (mask layer) on silicon nitride
2 (as shown in Figure 1), and use photoetching process formation to have the mask graph of fisrt feature size (such as Fig. 2
Sectional view shown in)；Wherein fisrt feature size is formed at or close high-resolution photomask etching system
The limit of optical resolution, the size at the resolution limit of present stage state-of-the-art immersed photoetching machine is
20-28 nanometer.
Aforementioned mask figure covers layer of silicon dioxide conforma layer (such as the top view of Fig. 3 and cutting of Fig. 4
Shown in the figure of face), after this conforma layer, extended meeting forms side wall (the sectional view institute such as Fig. 5 of uniform fold mask graph
Show), on side wall, the thickness of thin film is the first thickness；
Immediately performing second time photoetching and etch, photoresist 4 covers a part of silicon dioxide conforma layer (such as Fig. 6
Top view shown in), the conforma layer of the part 5 of exposure is thinned to have the side wall of the second thickness (such as Fig. 7
Top view shown in)；
Remove all photoresists, anisotropically etching silicon dioxide conforma layer, by mask layer top and bottom
Silicon dioxide remove, leave behind the silica membrane (as shown in plan view in figure 8) on sidewall；
Oxygen ashing process place to go is used to be exposed to the mask layer (sacrifice layer) on surface；Employing dry etching etches
The silicon dioxide conforma layer carried over, and as hard mask etch silicon nitride and silicon substrate, form shallow trench
(as shown in the sectional view of Fig. 9 and the top view of Figure 10), the active area of the shallow trench finally obtained isolation
Size has two kinds, and first size is close to the first thickness, and second is closely sized in the second thickness.
In the present invention, the size of the figure obtained as silicon dioxide or the silicon nitride of final etching mask
Having two kinds, two kinds of sizes are not limited by the physics limit of photoetching, are only determined by the thickness of side wall.
Using bilateral wall technique to form the method for ultralow size figure according to the preferred embodiment of the invention can be favourable
Apply in 20 nanometers and following IC manufacturing lithographic etch process.Such as, said method can conduct
The method forming the shallow trench of patterning in a silicon substrate or the polysilicon gate forming patterning on substrate
Method.
<concrete technology example>
Describe concrete technology example according to embodiments of the present invention below, can perform following step successively:
Use thermal oxidation method to form the silicon dioxide layer of 3 to 5 nanometers on a silicon substrate, adopt at silicon dioxide layer
The silicon nitride layer of 50-80 nano thickness is formed with LPCVD；
With the amorphous carbon layer of the method deposition 50-200 nano thickness of PECVD on silicon nitride layer, by decomposing
C2H2, forming amorphous carbon, technique initialization is: C2H2Flow be 1500sccm, temperature is 400C, cushion gas
Body He flow is 300-1500sccm, radio frequency be 13.56Mhz power be 800-1200W, pressure is 10 torr；
Photoetching also etches amorphous carbon layer and is formed and have the figure of fisrt feature size, and the size of this example is 80 nanometers；
The method using ald (ALD) on above-mentioned figure forms silicon dioxide conforma layer, and technique sets
Being set to: 2Nte flow is 1mgm, power is 2000-3000W, O2Flow be 3000-4000sccm, Ar
Flow be 1000-2000sccm；The thickness of conforma layer is 15-35 nanometer, and step coverage is 100%；
Carry out second time photoetching: spin coating gel method forms one layer of positive photoresist, carries out the second device area
Development, retains the first device area photoresist, and this example is that the drop-down metal-oxide-semiconductor region in 6T-SRAM region is carried out
Development, retains the photoresist in transmission metal-oxide-semiconductor region；
The conforma layer using the dry etching drop-down metal-oxide-semiconductor region to coming out carries out thinning, is thinned to 10
To 25 nanometers, step coverage be 80% and more than；
The anisotropic silicon dioxide getting rid of amorphous carbon top and bottom of using plasma etching is conformal
Layer, only leaves the silicon dioxide on side wall；
Using oxygen ashing process to remove amorphous carbon sacrifice layer, technique initialization is: the flow of O2 is
500-1500sccm, temperature is 200 degree, and power is 300W；
For hard mask, substrate is carried out dry etching with the silicon dioxide conforma layer of residual, form shallow trench isolation
Active area, the size of this active area is the thickness of conforma layer, the first device area (transmission metal-oxide-semiconductor)
A size of 15-35 nanometer；The size of the second device area (drop-down metal-oxide-semiconductor) is 10-25 nanometer.
The present invention uses advanced photoetching process to form the figure with fisrt feature size, and fisrt feature size connects
It is bordering on the physics limit of photoetching, the physics of photoetching can be limited by the method using double isolation double patterning molding
System is broken, and forms the figure much smaller than fisrt feature size, obtains two kinds of ultralow sizes by Twi-lithography
Figure, meets the figure transfer demand of 20 nanometers and following integrated circuit technology.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, the otherwise term in description " the
One " each assembly during, the description such as " second ", " the 3rd " is used only for differentiation description, element, step
Deng rather than for representing the logical relation between each assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is also
It is not used to limit the present invention.For any those of ordinary skill in the art, without departing from skill of the present invention
In the case of art aspects, technical solution of the present invention is made many by the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from this
The content of bright technical scheme, according to the present invention technical spirit to any simple modification made for any of the above embodiments,
Equivalent variations and modification, all still fall within the range of technical solution of the present invention protection.
Claims (6)
1. one kind uses the method that bilateral wall technique forms ultralow size figure, it is characterised in that including: first
The mask layer carried out in photoetching for the first time etched substrate first with a layer mask version has fisrt feature to be formed
The figure of size；Then on this figure, deposit thin film material layer, form being total to of uniform fold mask graph
Shape layer, on side wall, the thickness of thin film is the first thickness；Carrying out second time photoetching and etch, wherein photoresist covers
Cover a part of thin-film material, and the thin-film material of the part exposed by photoresist is thinned to have the second thickness
Side wall；Remove photoresist, form the figure with two kinds of thickness side walls；Anisotropically etching thin film material
Material, removes the thin-film material of mask layer top and bottom, leaves behind the thin film on sidewall；Cineration technics selects
The removal mask layer of selecting property, leaves behind the side wall that thin-film material is formed；Thin-film material enters as the mask of etching
Row etching, forms the hyperfine figure with two kinds of sizes, and the size of size is corresponding to the first of side wall
Thickness and the second thickness.
The method that employing bilateral wall technique the most according to claim 1 forms ultralow size figure, its
Being characterised by, mask layer is amorphous carbon film.
Employing bilateral wall technique the most according to claim 1 and 2 forms the side of ultralow size figure
Method, it is characterised in that fisrt feature size is equal to the optical resolution of high-resolution photomask etching system
Dimension limit 20 nanometer.
Employing bilateral wall technique the most according to claim 1 and 2 forms the side of ultralow size figure
Method, it is characterised in that thin-film material is silicon dioxide or silicon nitride.
5. one kind uses the method that bilateral wall technique forms ultralow size figure, it is characterised in that including:
Form silicon nitride on silicon substrate, and form mask layer on silicon nitride, and use photoetching process to be formed to have the
The mask graph of one characteristic size；Mask graph covers layer of silicon dioxide and forms conforma layer, formed all
The side wall of even coverage mask figure, on side wall, the thickness of conforma layer is the first thickness；Immediately carry out second time light
Carving and etch, photoresist covers a part of conforma layer, and the conforma layer of the part of exposure is thinned to have second
The side wall of thickness；Anisotropic etching conforma layer, removes the conforma layer of mask layer top and bottom, only
Leave the conforma layer on sidewall；Oxygen ashing process is used to remove the mask layer being exposed to surface；Use dry method
The conforma layer that etching etching carries over, and as hard mask etch silicon nitride and silicon substrate, form shallow ridges
Groove, the size of the active area of the shallow trench finally obtained isolation has two kinds, and first size is equal to the first thickness,
Second size is equal to the second thickness.
6. one kind uses the method that bilateral wall technique forms ultralow size figure, it is characterised in that including: shape
Become silicon dioxide gate dielectric layer, form polysilicon gate, and on polysilicon gate, form the mask as sacrifice layer
Layer, and use photoetching process to form the mask graph with fisrt feature size；In aforementioned mask figure overlying
Lid layer of silicon dioxide forms conforma layer, forms the side wall of uniform fold mask graph, conforma layer on side wall
Thickness is the first thickness；Immediately row second time photoetching etching, photoresist covers a part of conforma layer, will be sudden and violent
The conforma layer of the part of dew is thinned to the side wall with the second thickness；Anisotropic etching conforma layer, by sacrificial
The silicon dioxide of domestic animal layer top and bottom is removed, and leaves behind the conforma layer on sidewall；Use oxygen ashing process
Remove the mask layer being exposed to surface；Dry etching is used to etch the conforma layer carried over, and as firmly covering
Mould etches polycrystalline Si-gate and gate dielectric layer, form grid structure, and the size of the grid structure finally obtained has two
Kind, first size is equal to the first thickness, and the second size is equal to the second thickness.
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| CN201410253948.8A CN103996604B (en) | 2014-06-09 | 2014-06-09 | A kind of method using bilateral wall technique to form ultralow size figure |
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| CN103996604B true CN103996604B (en) | 2016-08-31 |
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| CN106154743B (en) * | 2015-03-24 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | Mask and forming method thereof |
| CN108807170B (en) * | 2018-06-11 | 2021-10-22 | 中国科学院微电子研究所 | Method for manufacturing nano wire |
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| KR20090050699A (en) * | 2007-11-16 | 2009-05-20 | 주식회사 동부하이텍 | Forming method of fine pattern and method for fabricating semiconductor device |
| US8734904B2 (en) * | 2010-11-30 | 2014-05-27 | International Business Machines Corporation | Methods of forming topographical features using segregating polymer mixtures |
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