CN110556338B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN110556338B
CN110556338B CN201810558138.1A CN201810558138A CN110556338B CN 110556338 B CN110556338 B CN 110556338B CN 201810558138 A CN201810558138 A CN 201810558138A CN 110556338 B CN110556338 B CN 110556338B
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layer
forming
initial
side wall
gate
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CN110556338A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is adjacent to the second area and is positioned at two sides of the second area, fin parts are respectively arranged on the first area and the second area, an initial opening is arranged between every two adjacent fin parts, and a barrier layer is arranged at the top of each fin part; forming side walls on the fin part and the side walls of the barrier layer, and enabling the initial opening to form an opening; forming an isolation layer in the opening of the second area, wherein the top of the isolation layer is higher than the surface of the top of the fin part; after the isolation layer is formed, removing the side wall and the barrier layer; and after the side walls and the barrier layer are removed, a grid electrode structure crossing the fin part is formed, the grid electrode structure covers partial side walls and the top surface of the fin part, and the grid electrode structure covers the side walls of the isolation layer. The method improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, the performance of the semiconductor device formed by the prior art is poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is adjacent to the second area and is positioned at two sides of the second area, fin parts are respectively arranged on the first area and the second area, an initial opening is arranged between every two adjacent fin parts, and a barrier layer is arranged at the top of each fin part; forming side walls on the fin part and the side walls of the barrier layer, and enabling the initial opening to form an opening; forming an isolation layer in the opening of the second area, wherein the top of the isolation layer is higher than the surface of the top of the fin part; after the isolation layer is formed, removing the side wall and the barrier layer; and after the side walls and the barrier layer are removed, a grid electrode structure crossing the fin part is formed, the grid electrode structure covers partial side walls and the top surface of the fin part, and the grid electrode structure covers the side walls of the isolation layer.
Optionally, the method for forming the side wall includes: forming a side wall material layer on the substrate, wherein the side wall material layer covers the side wall of the fin part, the top of the barrier layer and the side wall of the barrier layer; and etching the side wall material layer until the top surface of the barrier layer is exposed, and forming a side wall on the fin part and the side wall of the barrier layer.
Optionally, the method further includes: before forming the side wall, forming a protective layer on the side wall of the fin part and the side wall of the barrier layer, wherein the side wall covers the side wall of the protective layer; removing the protective layer after removing the side wall and the barrier layer; and after removing the side wall, the barrier layer and the protective layer, forming a gate structure crossing the fin part.
Optionally, the forming method of the protective layer includes: forming an initial protection layer on the substrate, wherein the initial protection layer covers the side wall of the fin part, the top of the barrier layer and the side wall of the barrier layer; and etching the initial protective layer back until the top surface of the barrier layer is exposed, and forming a protective layer on the fin part and the side wall of the barrier layer.
Optionally, the material of the sidewall includes: amorphous carbon, amorphous silicon, or amorphous germanium.
Optionally, the process for removing the sidewall includes: and (5) ashing.
Optionally, the thickness of the side wall is 10nm to 40 nm.
Optionally, the material of the protective layer includes: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
Optionally, the forming method of the isolation layer includes: forming an initial mask material layer in the opening, wherein the initial mask material layer covers the fin part, the barrier layer and the top surface of the side wall; etching back the initial mask material layer, and forming an initial isolation layer in the opening, wherein the top surface of the initial isolation layer is higher than the top surface of the fin part; and removing the initial isolation layer in the opening of the first region, and forming an isolation layer in the opening of the second region.
Optionally, the initial isolation layer top surface is lower than or flush with the barrier layer top surface.
Optionally, the method of removing the initial isolation layer in the opening of the first region includes: after the initial isolation layer is formed, forming a first graphical layer on the fin part, the barrier layer, the side wall and the surface of the initial isolation layer, wherein the first graphical layer exposes the position and the shape of the initial isolation layer in the first area; and etching and removing the initial isolation layer of the first region by taking the first patterning layer as a mask so as to form an isolation layer in the opening of the second region.
Optionally, the material of the isolation layer includes: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
Optionally, the forming process of the initial mask material layer includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the thickness of the isolation layer is 60nm to 100nm, and the width of the isolation layer is 40nm to 60 nm.
Optionally, the material of the barrier layer includes: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
Optionally, the thickness of the barrier layer is 30nm to 50 nm.
Optionally, the gate structure includes a gate oxide layer covering the sidewall and the top surface of the fin portion and a gate layer located on the surface of the gate oxide layer, and the top of the gate layer is flush with the top of the isolation layer.
Optionally, after the gate layer is formed, a gate protection layer is formed on the surfaces of the gate layer and the isolation layer, and the gate protection layer covers the top surface of the gate layer and the top surface of the isolation layer.
Optionally, the forming method of the gate structure includes: forming an initial gate oxide layer covering the side wall and the top surface of the fin part on the fin part; after the initial gate oxide layer is formed, forming an initial gate material layer on the surfaces of the fin part and the isolation layer, wherein the initial gate material layer covers the top surfaces of the fin part and the isolation layer; flattening the initial grid electrode material layer until the top surface of the isolation layer is exposed to form an initial grid electrode layer; forming an initial gate protection layer on the surfaces of the initial gate layer and the isolation layer; after the initial gate protection layer is formed, forming a second patterning layer on the surface of the initial gate protection layer, wherein the second patterning layer exposes the shape and the position of a gate structure to be formed; and after a second patterning layer is formed, etching the initial gate protection layer, the initial gate electrode layer and the initial gate oxide layer by taking the second patterning layer as a mask to form a gate structure.
The invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor device, provided by the technical scheme of the invention, the distances between the fin parts are equal, side walls are formed on the side walls of the fin parts, the isolation layers are positioned between the side walls between the adjacent fin parts, and the distances between the isolation layers and the adjacent fin parts are equal if the thicknesses of the side walls are the same; the thickness of the isolation layer can be controlled by controlling the thickness of the side wall; removing the side wall, and forming a gate opening between the isolation layer and the adjacent fin part, wherein the size of the gate opening is also determined by the thickness of the side wall; the thickness of the side wall is the same, the distance between the isolation layer and the adjacent fin portion is the same, the size of a gate opening formed between the subsequently formed isolation layer and the adjacent fin portion is the same, when a gate layer is formed in the gate opening in a deposition mode, the effect of depositing the gate layer is good, the formed gate structure is good in appearance, the performance of a device is favorably improved, and therefore the performance of a semiconductor device is improved.
Drawings
Fig. 1 to 4 are schematic structural views of a semiconductor device formation process;
fig. 5 to 12 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the prior art semiconductor devices is poor.
Fig. 1 to 4 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1 and 2, fig. 1 is a top view of a semiconductor device with a patterned layer omitted, and fig. 2 is a schematic cross-sectional view of fig. 1 along cut line a-a 1. Providing a semiconductor substrate 100, wherein the semiconductor substrate 100 is provided with a fin 110, an isolation structure 101, a dielectric layer 102 and a dummy gate structure 120, the dummy gate structure 120 spans the fin 110 to cover part of the sidewall and part of the top surface of the fin 110, the isolation structure 101 covers part of the sidewall of the fin 110, and the dielectric layer 102 is located on the isolation structure 101 to cover the sidewall of the dummy gate structure 120; the dielectric layer 102 and the dummy gate structure 120 have a patterned layer 130 on top thereof, the patterned layer 130 exposes an opening 140 in the dielectric layer 102, and the opening 140 exposes a portion of the top surface of the isolation structure 101.
Referring to fig. 3, an isolation layer 150 is formed in the opening 140, the top of the isolation layer 150 is flush with the top of the dielectric layer 102, the dummy gate structure is removed, and a gate opening 160 is formed between the isolation layer 150 and the adjacent fin 110.
Referring to fig. 4, a gate dielectric layer 161 and a gate layer 162 on the surface of the gate dielectric layer 161 are formed on the sidewalls and bottom of the gate opening 160.
The patterning layer 130 is formed by a photolithography process, and an error exists in the photolithography process, which easily causes that the distances between the opening 140 and the two adjacent fins 110 are unequal, one is close, and the other is far, the isolation layer 150 formed in the opening 140, the gate opening 160 formed between the isolation layer 150 and the two adjacent fins 110 are smaller and larger, and when the gate layer 162 is deposited in the smaller gate opening 160, the gate opening is difficult to deposit to the bottom of the gate opening, and the cavity 170 is easily formed between the gate dielectric layer 161 and the gate layer 162, so that the performance of the formed semiconductor device is poor.
According to the invention, the side walls are formed on the side walls of the fin parts, and the isolation layers are formed in the openings between the side walls, so that the distances from the isolation layers to the adjacent fin parts are equal, the thickness of the isolation layers is easy to control, and the method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 12 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 5, a substrate is provided.
In this embodiment, the substrate includes: a semiconductor substrate 200 and a fin 210 on a surface of the semiconductor substrate 200. In other embodiments, the base may also be a planar substrate.
In this embodiment, the semiconductor substrate 200 includes a first region a and a second region B, the first region a and the second region B are adjacent to each other and located at two sides of the second region B, and the first region a and the second region B have a fin portion 210 on the semiconductor substrate 200 respectively.
In this embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon. The semiconductor substrate 200 may also be polysilicon or amorphous silicon. The material of the semiconductor substrate 200 may also be germanium, silicon germanium, gallium arsenide, or other semiconductor materials. The semiconductor substrate 200 can also be a semiconductor-on-insulator structure including an insulator and a semiconductor material layer on the insulator, wherein the semiconductor material layer includes a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or indium gallium arsenide.
In this embodiment, the fins 210 are formed by patterning the semiconductor substrate 200. In other embodiments, it may be: a fin material layer is formed on the semiconductor substrate and then patterned to form a fin 210.
In this embodiment, the material of the fin portion 210 is monocrystalline silicon. In other embodiments, the material of the fin 210 is single crystal silicon germanium or other semiconductor materials.
In this embodiment, the semiconductor substrate 200 further has an isolation structure 201 thereon, the isolation structure 201 covers a portion of the sidewall surface of the fin 210, and the surface of the isolation structure 201 is lower than the top surface of the fin 210. The material of the isolation structure 201 includes silicon oxide.
In this embodiment, an initial opening is formed between adjacent fins 210, which exposes the top surface of isolation structure 201 and the sidewall surfaces of fins 210.
The initial opening provides space for a subsequently formed opening.
In this embodiment, the top surface of the fin 210 has a barrier layer 202, and the barrier layer 202 protects the fin 210 and defines the thickness of the isolation layer when the isolation layer is formed later.
The material of the barrier layer 202 includes silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
The thickness of the barrier layer 202 includes: 30nm to 50 nm.
The thickness of the barrier layer 202 determines the thickness of a subsequently formed isolation layer, the thickness of the barrier layer 202 is too thick, the thickness of the subsequently formed isolation layer is too thick, the thickness of a subsequently formed gate layer is too thick, material waste is serious, the thickness of the barrier layer 202 is too thin, and the thickness of the subsequently formed gate layer is too thin, so that the performance of a semiconductor device is affected.
Referring to fig. 6, a protection layer 203 is formed on the sidewalls of the fin 210 and the sidewalls of the barrier layer 202.
The protective layer 203 is located within the initial opening.
The protective layer 203 protects the fin 210 during subsequent sidewall formation and removal.
The forming method of the protective layer 203 comprises the following steps: forming an initial protection layer (not shown) on the fin 210, the isolation structure 201, and the barrier layer 202 and within the initial opening, the initial protection layer covering a portion of the top surface of the isolation structure 201, sidewalls of the fin 210, and top and sidewalls of the barrier layer 202; the initial passivation layer is etched back until the top surface of the barrier layer 202 is exposed, and a passivation layer is formed on the sidewalls of the fin 210 and the sidewalls of the barrier layer 202.
The forming process of the initial protective layer comprises the following steps: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the forming process of the initial protection layer is an atomic layer deposition process.
The material of the protective layer 203 includes: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the protection layer 203 is silicon nitride.
In this embodiment, the thickness of the protective layer 203 is 2nm to 6 nm.
The protective layer 203 is too thin, so that the protection of the fin part is limited; the protective layer 203 is too thick, and the subsequent removal process is long, which easily causes material waste and process waste.
Referring to fig. 7, after forming the protection layer 203, a sidewall material layer 204 is formed on the fin 210, the barrier layer 202 and the protection layer 203.
In this embodiment, the sidewall material layer 204 is located at the bottom and the sidewall of the initial opening, and covers the sidewall of the protection layer 203, the top surface of the barrier layer 202, and a portion of the top surface of the isolation structure 201.
The sidewall material layer 204 provides a material layer for the subsequent formation of a sidewall.
The forming process of the side wall material layer 204 comprises the following steps: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the forming process of the sidewall material layer 204 is a chemical vapor deposition process.
The material of the sidewall material layer 204 includes: amorphous carbon, amorphous silicon, or amorphous germanium.
The material of the side wall material layer 204 is amorphous carbon, and the subsequent process for removing the side wall is simple.
The amorphous carbon can be removed by an ashing process, the ashing process removes the amorphous carbon, the removal is thorough, and the corrosion to peripheral materials is small.
In this embodiment, the material of the sidewall material layer 204 is amorphous carbon.
Referring to fig. 8, after forming the spacer material layer 204, the spacer material layer 204 is etched back until the top surface of the barrier layer 202 is exposed, and a spacer 205 is formed on the sidewalls of the fin 210 and the barrier layer 202, and an opening 206 is formed in the initial opening.
The openings 206 are located between adjacent sidewalls 205 between adjacent fins 210.
In this embodiment, the sidewall spacers 205 cover the sidewalls of the protection layer 203.
The spacers 205 define the position and shape of the subsequently formed isolation layer. The distance between the adjacent fins 210 is constant, and the side walls 205 are located on the side walls of the fins 210, so that the distance between the side walls between the adjacent fins 210 determines the width of the opening 206 between the adjacent side walls. Subsequently, an isolation layer is formed in the opening 206, and the thickness of the isolation layer depends on the thickness of the sidewall.
The thickness of the side wall 205 is 10nm to 40 nm.
The side wall is too thick, the thickness of the subsequently formed isolation layer is too small, the isolation layer is used for isolating the adjacent grid electrode structures, the probability of electric leakage between the adjacent grid electrode structures is increased, and the performance of the semiconductor device is not facilitated. The side wall is too thin, the distance between the isolation layer and the adjacent fin portion is short, a gate opening between the isolation layer and the adjacent fin portion is small, and the deposition difficulty of a subsequent gate layer is high.
The opening 206 provides space for subsequent formation of isolation layers.
The opening 206 exposes a portion of the top surface of the isolation structure 201 and the sidewalls of the sidewall spacers 205.
The openings 206 are located between adjacent side walls 205, and the distances from adjacent fins 210 are the same, so that the distances between the subsequently formed fins 210 adjacent to the isolation layer in the openings 206 are the same.
Referring to fig. 9, after forming the opening 206, an initial isolation layer 207 is formed in the opening 206.
The initial spacer layer 207 provides a material layer for subsequently forming a spacer layer.
The method for forming the initial isolation layer 207 includes: a layer of initial masking material (not shown) within the opening 206, covering the fin 210, the barrier layer 202 and the top surface of the sidewall 205; the initial mask material layer is etched back to form an initial isolation layer 207 in the opening 206, wherein the top surface of the initial isolation layer 207 is higher than the top surface of the fin 210.
The initial isolation layer 207 top surface is below the barrier layer 202 top surface or flush with the barrier layer 202 top surface.
In this embodiment, the top surface of the initial isolation layer 207 is flush with the top surface of the barrier layer 202.
In other implementations, the top surface of the initial isolation layer 207 is lower than the top surface of the barrier layer 202.
The forming process of the initial mask material layer comprises the following steps: a fluid chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the forming process of the initial mask material layer is a Fluid Chemical Vapor Deposition (FCVD).
In one embodiment, the forming process of the initial mask material layer is a Deep Ultraviolet Oxidation (DUO).
In other embodiments, the initial masking material layer can also employ a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
The material of the initial spacer material layer comprises: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the initial mask material layer is silicon oxide.
The material of the initial mask material layer determines the material of the isolation layer, the protective layer 203 and the barrier layer 202 need to be removed subsequently, the protective layer 203 and the barrier layer 202 are made of silicon nitride, and the isolation layer is made of silicon oxide, so that loss during the removal of the protective layer 203 and the barrier layer 202 is relatively low.
Referring to fig. 10, after forming the initial isolation layer 207, the initial isolation layer 207 in the opening 206 of the first region a is removed, and an isolation layer 208 is formed in the opening 206 of the second region.
The spacers 208 subsequently act as spacers between adjacent gate structures.
The forming method of the isolation layer 208 includes: forming a first patterning layer (not shown) on the surfaces of the fin 210, the barrier layer 202, the sidewall spacers 205 and the initial isolation layer 207, wherein the first patterning layer exposes the position and the shape of the initial isolation layer 207 in the first region a; the initial isolation layer 207 of the first region a is etched away using the first patterned layer as a mask, thereby forming an isolation layer 208 within the opening 206 of the second region B.
In the technical scheme, the isolation layer 208 is formed by adopting a patterning layer process, but the position of the isolation layer 208 cannot be influenced, and the position of the isolation layer is mainly determined by the self-aligned side wall in the technical scheme, so that the position of the isolation layer cannot be influenced even if the position of the formed first patterning layer deviates.
The thickness of the isolation layer 208 is 60nm to 100nm, and the width is 40nm to 60 nm.
The thickness of the isolation layer 208 is too thick, the depth-to-width ratio of a subsequently formed gate opening is large, and the deposition effect of a subsequent gate layer is poor; the thickness of the isolation layer is too thin, and the height of the grid structure is too low, so that the performance of the semiconductor device is affected.
The isolation layer 208 is located between adjacent fins 210 in the second region B, the isolation layer 208 is isolated from the adjacent fins 210 by the side walls 205, distances between the isolation layer 208 and the adjacent fins 210 are equal, and the side walls 205 are removed subsequently to form corresponding gate openings between the isolation layer 208 and the adjacent fins 210, wherein the gate openings have the same size.
The distance between adjacent fins 210 is constant, and the width of the isolation layer 208 and the size of the gate opening formed between the isolation layer 208 and the adjacent fin 210 can be controlled by controlling the thickness of the sidewall 205.
The width of the isolation layer 208 is too wide, and the size of a gate opening formed between the isolation layer 208 and the fin portion 210 adjacent to the isolation layer is small, which is not beneficial to the deposition of a subsequent gate layer; the width of the isolation layer 208 is too narrow, which has a limited isolation effect on the adjacent gate structures, and is not favorable for the performance of the semiconductor device.
Referring to fig. 11, after forming the isolation layer 208, the spacers 205 and the barrier layer 202 are removed to expose the top and the sidewall surface of the fin 210.
In this embodiment, after removing the sidewall spacer 205, the protective layer 203 and the barrier layer 202 are removed; after the spacers 205, the barrier layer 202 and the protection layer 203 are removed, a gate structure crossing the fin 210 is formed, the gate structure covers part of the sidewalls and the top surface of the fin 210, and the gate structure covers the sidewalls of the isolation layer 208.
In this embodiment, the top surface of the gate structure is flush with the top surface of the isolation layer 208. The gate structure comprises a gate oxide layer covering part of the side wall and the top surface of the fin portion 210 and a gate layer located on the surface of the gate oxide layer, wherein the top of the gate layer is flush with the top of the isolation layer 208.
In one embodiment, the top of the gate structure is below the top surface of the isolation layer 208.
In this embodiment, the method for forming the gate structure includes: after removing the side walls 205, the protective layer 203 and the barrier layer 202, forming an initial gate structure covering the side walls and the top surface of the fin portion on the fin portion 210; after the initial gate structure is formed, the initial gate structure is etched, so that a gate structure is formed.
The initial gate structure includes an initial gate oxide layer 221 covering the fin sidewalls and top surface and an initial gate layer 222 on the surface of the initial gate oxide layer.
The initial gate structure further includes an initial gate protection layer on the surfaces of the initial gate layer 222 and the isolation layer 208.
In this embodiment, after removing the spacers 205, the protective layer 203 and the barrier layer 202, an initial gate oxide layer 221 is formed on the sidewalls and the top surface of the fin 210.
The process for removing the side wall comprises the following steps: and (5) ashing.
The ashing process removes amorphous carbon, the removal is thorough, and the corrosion to peripheral materials is small.
In this embodiment, the protective layer 203 and the barrier layer 202 are made of the same material, and are made of silicon nitride, and may be removed simultaneously or step by step.
The process of removing the protective layer 203 and the barrier layer 202 includes: a wet etching process or a dry etching process.
In this embodiment, the protective layer 203 and the barrier layer 202 are removed simultaneously by a wet etching process. The parameters of the wet etching process comprise: the phosphoric acid etching solution is formed by adopting a mixture of phosphoric acid and deionized water, wherein the phosphoric acid has the volume percentage concentration of 80-90 percent, such as 86-87 percent, and the process temperature is in the range of 90-180 ℃, such as 160 ℃.
The protective layer 203 and the barrier layer 202 are made of silicon nitride, and the isolation layer 208 is made of silicon oxide. The solvent of the wet etching is hot phosphoric acid etching liquid, so that the protective layer 203 and the barrier layer 202 can be removed, and the loss of the isolation layer 208 is small.
In one embodiment, the protective layer 203 and the barrier layer 202 are easily removed simultaneously using dry etching.
In other embodiments, the protective layer 203 and the barrier layer 202 are easily removed in steps by dry etching.
The material of the initial gate oxide layer 221 is silicon oxide. In the present embodiment, the formation process of the initial gate oxide layer 221 is an In-Situ Steam Generation (ISSG). The initial gate oxide layer 221 formed by the in-situ steam generation process has good step coverage capability, the formed initial gate oxide layer 221 can be tightly covered on the surface of the side wall of the fin portion 210, and the thickness of the formed initial gate oxide layer 221 is uniform.
In another embodiment, the formation process of the initial gate oxide layer 221 is a chemical oxidation process; the steps of the chemical oxidation process include: and oxidizing the exposed side wall and the top surface of the fin portion 210 by adopting an aqueous solution filled with ozone to form an initial gate oxide layer 221.
Referring to fig. 12, after forming an initial gate oxide layer 221, an initial gate layer 222 is formed on the surface of the initial oxide layer 221.
In this embodiment, the initial gate layer 222 is located on the initial gate oxide layer 221, and the material of the initial gate layer 222 includes silicon, amorphous silicon, polysilicon, or doped polysilicon.
In this embodiment, after the forming of the initial gate layer 222, an initial gate protection layer 223 is further formed on the surfaces of the initial gate layer 222 and the isolation layer 208, and the initial gate protection layer 223 covers the top surface of the initial gate layer 222 and the top surface of the isolation layer 208.
The initial gate oxide layer 221 and the initial gate layer 222 and the gate protection layer 223 constitute an initial gate structure.
The method for forming the initial gate layer 222 includes: forming an initial gate material layer (not shown) on the surfaces of the isolation layer 208 and the initial gate oxide layer 221, wherein the initial gate material layer covers the top surfaces of the fin portion 210 and the isolation layer 208; the initial gate material layer is planarized until the top surface of the isolation layer 208 is exposed, forming an initial gate layer 222.
The forming process of the initial grid material layer comprises a chemical vapor deposition process or a physical vapor deposition process.
In this embodiment, the method for forming the gate structure includes: after the initial gate structure is formed, a second patterned layer (not shown) is formed on the surface of the gate protection layer 223, and the second patterned layer exposes the shape and the position of the gate structure to be formed; and after a second patterning layer is formed, etching the initial gate layer and the initial gate oxide layer by taking the second patterning layer as a mask to form a gate structure.
The gate structure includes a gate oxide layer covering part of the sidewall and the top surface of the fin 210 and a gate layer on the surface of the gate oxide layer, and the top surface of the gate layer is flush with the top surface of the isolation layer 208.
The gate oxide layer is made of silicon oxide, the gate electrode layer is made of monocrystalline silicon, and the gate protection layer is made of silicon nitride.
In other embodiments, the method for forming the gate structure includes: after forming the isolation layer 208, forming a dummy gate structure crossing the fin portion 210 on the fin portion 210 and the isolation structure 201, wherein the dummy gate structure covers part of the sidewall and the top surface of the fin portion 210, and the dummy gate structure is located on two sides of the isolation layer 208; removing the pseudo gate structure to form a gate opening; after a gate opening is formed, a gate structure is formed in the gate opening, the gate structure comprises a gate oxide layer covering partial side wall and top surface of the fin portion 210 and a gate layer located on the surface of the gate oxide layer, the top surface of the gate layer is flush with the top surface of the isolation layer 208, and after the gate layer is formed, a gate protection layer is formed on the surfaces of the gate layer and the isolation layer 208.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, the first area is adjacent to the second area and is positioned at two sides of the second area, fin parts are respectively arranged on the first area and the second area, an initial opening is arranged between every two adjacent fin parts, and a barrier layer is arranged at the top of each fin part;
forming side walls on the fin part and the side walls of the barrier layer, and enabling the initial opening to form an opening;
forming an isolation layer in the opening of the second area, wherein the top of the isolation layer is higher than the surface of the top of the fin part; the isolation layer is used for isolating the adjacent grid electrode structures;
after the isolation layer is formed, removing the side wall and the barrier layer;
after the side walls and the barrier layer are removed, grid electrode structures crossing the fin parts are formed on two sides of the isolation layer respectively, the grid electrode structures cover partial side walls and the top surface of the fin parts, and the grid electrode structures cover the side walls of the isolation layer; the grid structure comprises a grid oxide layer covering the side wall and the top surface of the fin part and a grid layer located on the surface of the grid oxide layer, and the top of the grid layer is flush with the top of the isolation layer.
2. The method for forming the semiconductor device according to claim 1, wherein the method for forming the side wall comprises the following steps: forming a side wall material layer on the substrate, wherein the side wall material layer covers the side wall of the fin part, the top of the barrier layer and the side wall of the barrier layer; and etching the side wall material layer until the top surface of the barrier layer is exposed, and forming a side wall on the fin part and the side wall of the barrier layer.
3. The method for forming a semiconductor device according to claim 2, further comprising: before forming the side wall, forming a protective layer on the side wall of the fin part and the side wall of the barrier layer, wherein the side wall covers the side wall of the protective layer; removing the protective layer after removing the side wall and the barrier layer; and after removing the side wall, the barrier layer and the protective layer, forming a gate structure crossing the fin part.
4. The method for forming a semiconductor device according to claim 3, wherein the method for forming the protective layer comprises: forming an initial protection layer on the substrate, wherein the initial protection layer covers the side wall of the fin part, the top of the barrier layer and the side wall of the barrier layer; and etching the initial protective layer back until the top surface of the barrier layer is exposed, and forming a protective layer on the fin part and the side wall of the barrier layer.
5. The method for forming the semiconductor device according to claim 1, wherein the material of the side wall comprises: amorphous carbon, amorphous silicon, or amorphous germanium.
6. The method for forming the semiconductor device according to claim 5, wherein the step of removing the side wall comprises: and (5) ashing.
7. The method for forming the semiconductor device according to claim 1, wherein the thickness of the side wall is 10nm to 40 nm.
8. The method according to claim 3, wherein a material of the protective layer comprises: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
9. The method for forming a semiconductor device according to claim 1, wherein the method for forming the isolation layer comprises: forming an initial mask material layer in the opening, wherein the initial mask material layer covers the fin part, the barrier layer and the top surface of the side wall; etching back the initial mask material layer, and forming an initial isolation layer in the opening, wherein the top surface of the initial isolation layer is higher than the top surface of the fin part; and removing the initial isolation layer in the opening of the first region, and forming an isolation layer in the opening of the second region.
10. The method of claim 9, wherein the initial isolation layer top surface is lower than or flush with the barrier layer top surface.
11. The method of claim 9, wherein removing the initial isolation layer within the opening of the first region comprises: after the initial isolation layer is formed, forming a first graphical layer on the fin part, the barrier layer, the side wall and the surface of the initial isolation layer, wherein the first graphical layer exposes the position and the shape of the initial isolation layer in the first area; and etching and removing the initial isolation layer of the first region by taking the first patterning layer as a mask so as to form an isolation layer in the opening of the second region.
12. The method according to claim 9, wherein a material of the isolation layer includes: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
13. The method of claim 9, wherein the forming process of the initial mask material layer comprises: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
14. The method of claim 9, wherein the isolation layer has a thickness of 60nm to 100nm and a width of 40nm to 60 nm.
15. The method according to claim 1, wherein a material of the barrier layer comprises: silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
16. The method for forming a semiconductor device according to claim 1, wherein a thickness of the barrier layer is 30nm to 50 nm.
17. The method of claim 1, further comprising forming a gate protection layer on the surfaces of the gate layer and the isolation layer after forming the gate layer, wherein the gate protection layer covers the top surface of the gate layer and the top surface of the isolation layer.
18. The method for forming a semiconductor device according to claim 17, wherein the method for forming the gate structure comprises: forming an initial gate oxide layer covering the side wall and the top surface of the fin part on the fin part; after the initial gate oxide layer is formed, forming an initial gate layer on the surfaces of the fin portion and the isolation layer, wherein the initial gate layer covers the fin portion and the top surface of the isolation layer; planarizing the initial gate layer until the top surface of the isolation layer is exposed; forming a gate protection layer on the surfaces of the gate layer and the isolation layer; after the gate protection layer is formed, forming a second patterning layer on the surface of the gate protection layer, wherein the shape and the position of the gate structure to be formed are exposed by the second patterning layer; and after a second patterning layer is formed, etching the initial gate layer and the initial gate oxide layer by taking the second patterning layer as a mask to form a gate structure.
19. A semiconductor device formed according to the method for forming a semiconductor device of any one of claims 1 to 18.
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