CN102800576A - Method for graphing membrane layer and methods for forming gate and metal oxide semiconductor (MOS) transistor - Google Patents
Method for graphing membrane layer and methods for forming gate and metal oxide semiconductor (MOS) transistor Download PDFInfo
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- CN102800576A CN102800576A CN2011101394878A CN201110139487A CN102800576A CN 102800576 A CN102800576 A CN 102800576A CN 2011101394878 A CN2011101394878 A CN 2011101394878A CN 201110139487 A CN201110139487 A CN 201110139487A CN 102800576 A CN102800576 A CN 102800576A
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Abstract
The invention discloses a method for graphing a membrane layer and methods for forming a gate and a metal oxide semiconductor (MOS) transistor. The method for graphing the membrane layer comprises the following steps of: supplying a substrate; forming a graphing sacrificial layer on the substrate; forming the membrane layer to be graphed on the substrate, wherein the upper surface of the membrane layer is flush with the upper surface of the graphing sacrificial layer; forming a graphic layer on the membrane layer, wherein the graphic layer and the graphing sacrificial layer define a graphed graph for membrane layer together; etching the membrane layer by taking the graphic layer as a mask to form a graphed membrane layer; and removing the graphic layer and the graphing sacrificial layer. By the technical scheme, the membrane layer is etched by taking the graphic layer as the mask, so that the membrane layer is graphed, and the step of etching the membrane layer is eliminated.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method for graphic diaphragm layer, the method for formation grid.
Background technology
The method that forms grid in the traditional handicraft is: substrate is provided, and said substrate top layer is a gate dielectric layer; On said gate dielectric layer, form polysilicon layer; On said polysilicon layer, form photoresist layer, and photoresist layer made public, develops form patterned photoresist layer; With patterned photoresist layer is that the said polysilicon layer of mask etching forms grid.
Yet; More and more littler along with the semiconductor device critical size;, under 193nm (nanometer) depositing in water immersion lithography condition, utilize a mask to form graphical technology as mask and run into physical restriction during less than 32nm at the technology node (1/2nd pitch-rows) of semiconductor technology, adjacent figure pitch-row is too small; Owing to optical proximity effect, the phenomenon of adjacent pattern adhesion can appear.Therefore, semiconductor device critical size more and more littler during less than 32nm, utilizes the technology of traditional graphical polysilicon layer to form the phenomenon that the adjacent pattern adhesion can appear in grid at the technology node (1/2nd pitch-rows) of semiconductor technology.
In order to solve above technical problem; The technology of double-patternization has been proposed in the prior art; The figure that needs are transferred on the photoresist layer is divided into first figure and second graph; Just patterned photoresist layer is divided into the photoresist layer of the first patterned photoresist layer and second graphical, at twice polysilicon layer is carried out graphically.Be specially: substrate is provided, and said substrate top layer is a gate dielectric layer; On said gate dielectric layer, form polysilicon layer; On said polysilicon layer, form the first patterned photoresist layer; With patterned first photoresist layer is the said polysilicon layer of mask etching; Afterwards, on the polysilicon layer after the etching, forming the photoresist layer of second graphical, is that mask continues the said polysilicon layer of etching with the photoresist layer of second graphical, forms grid.
Also disclose many patterned methods in the prior art, for example the application number of on May 30th, 2008 application is the method for disclosed graphical substrate in 200810113985.3 the one Chinese patent application.
Summary of the invention
The problem that the present invention will solve is the method step complicacy of the double-patternization of prior art.
For addressing the above problem, the present invention provides a kind of method of graphic diaphragm layer, comprising:
Substrate is provided;
In said substrate, form patterned sacrifice layer;
In said substrate, form rete, the upper surface of said rete is equal with the upper surface of said patterned sacrifice layer;
On said rete, form graph layer, said graph layer and patterned sacrifice layer define the figure of membrane graphic jointly;
With said graph layer is the said rete of mask etching, forms patterned rete;
Remove said graph layer, patterned sacrifice layer.
Optional, said rete is a polysilicon layer;
The top layer of said substrate is a gate dielectric layer, and said polysilicon layer, patterned sacrifice layer are formed on the gate dielectric layer of said substrate;
Said patterned rete is a grid.
Optional, said rete is a hard mask layer;
The top layer of said substrate is followed successively by gate dielectric layer and pseudo-grid layer, and said pseudo-grid layer is formed on the said gate dielectric layer, and said hard mask layer is formed on the said pseudo-grid layer.
Optional, the material of said pseudo-grid layer is a polysilicon.
Optional, the material of said sacrifice layer is silicon nitride, metal, agraphitic carbon, carbon doped silicon or polymer.
Optional, in said substrate, form patterned sacrifice layer and comprise:
In said substrate, form sacrifice layer;
On said sacrifice layer, form photoresist layer;
Utilizing photoetching or impress said photoresist layer to form patterned photoresist layer, is the mask etching sacrifice layer with patterned photoresist layer afterwards, forms patterned sacrifice layer;
Remove patterned photoresist layer.
Optional, utilize wet etching to remove said patterned sacrifice layer.
Optional, said graph layer is patterned photoresist layer;
Comprise at formation graph layer on the said rete: on said rete, form photoresist layer, utilize exposure, the graphical said photoresist layer of developing process to form patterned photoresist layer.
Optional, utilize ashing to remove said graph layer.
Optional, the method for said formation rete comprises:
Utilize vapour deposition to form rete, cover said substrate and said patterned sacrifice layer;
Said rete is planarized to the upper surface that exposes said patterned sacrifice layer, makes the upper surface of rete equal with the upper surface of patterned sacrifice layer.
Optional, the material of said gate dielectric layer is a silica.
Optional, the material of said hard mask layer is a silicon nitride.
The present invention also provides a kind of method that forms grid, comprising:
Form patterned hard mask layer with above-described method;
With said patterned hard mask layer is the mask said pseudo-grid layer of etching, gate dielectric layer successively, and the pseudo-grid layer after the etching forms dummy grid;
Form interlayer dielectric layer, cover said substrate, the upper surface of said interlayer dielectric layer is equal with the upper surface of said dummy grid;
Remove said dummy grid and form the dummy grid groove;
The filled conductive material forms grid in said dummy grid groove.
Optional, said electric conducting material is a metal.
Optional, the material of said hard mask layer is a silicon nitride.
Optional, the material of said interlayer dielectric layer is low-k materials or ultralow k material.
Optional, said low-k materials is selected from SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON one of them or they combination in any.
Optional, said ultralow k material is a black diamond.
The embodiment of the invention also provides a kind of method that forms MOS transistor, comprises with above-described method forming grid.
Compared with prior art, technical scheme of the present invention has the following advantages:
The present technique scheme defines the figure of membrane graphic jointly through patterned sacrifice layer and graph layer; And the step that forms patterned sacrifice layer is before the step that forms rete, with existing after rete forms, to define two patterned photoresist layers more respectively different.And, accomplished graphical to rete when being the mask etching rete with the graph layer, saved the step of etched membrane layer, simplified the method for graphic diaphragm layer.
In the present invention's one specific embodiment, rete is a polysilicon layer, and the top layer of substrate is a gate dielectric layer, and graphical polysilicon layer has formed grid.
In another specific embodiment of the present invention, rete is a hard mask layer, and the top layer of substrate is gate dielectric layer and polysilicon layer, and graphic diaphragm layer has formed dummy grid.
Description of drawings
Fig. 1 is the schematic flow sheet of method of the graphic diaphragm layer of the specific embodiment of the invention;
Fig. 2 a, Fig. 2 b～Fig. 7 a, Fig. 7 b are the cross-sectional view and the schematic top plan view of method of the graphic diaphragm layer of the present invention's first specific embodiment;
The cross-sectional view and the schematic top plan view of the structure that Fig. 8 a, Fig. 8 b form for the method for the graphic diaphragm layer of the present invention's second practical implementation.
Embodiment
The present technique scheme defines the figure of membrane graphic jointly through patterned sacrifice layer and graph layer; And the step that forms patterned sacrifice layer is before the step that forms rete, with existing after rete forms, to define two patterned photoresist layers more respectively different.And, accomplished graphical to rete when being the mask etching rete with the graph layer, saved the step of etched membrane layer.
In order to make those skilled in the art can better understand the present invention, specify embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 1 is the flow chart of method of the graphic diaphragm layer of the specific embodiment of the invention, and with reference to figure 1, the method for the graphic diaphragm layer of the specific embodiment of the invention comprises:
Step S11 provides substrate;
Step S12 forms patterned sacrifice layer in said substrate;
Step S13 forms rete in said substrate, the upper surface of said rete is equal with the upper surface of said patterned sacrifice layer;
Step S14 forms graph layer on said rete, said graph layer and patterned sacrifice layer define the figure of membrane graphic jointly;
Step S15 is the said rete of mask etching with said graph layer, forms patterned rete;
Step S16 removes said graph layer, patterned sacrifice layer.
Fig. 2 a, Fig. 2 b～Fig. 7 a, Fig. 7 b are the cross-sectional view and the schematic top plan view of method of the graphic diaphragm layer of the present invention's first specific embodiment; In order to make those skilled in the art can better understand embodiment of the present invention, specify the method for the graphic diaphragm layer of embodiment of the present invention below in conjunction with specific embodiment and Fig. 1, Fig. 2 a, Fig. 2 b～Fig. 7 a, Fig. 7 b.
In the present invention's first specific embodiment, utilize the method for graphic diaphragm layer of the present invention to form grid.Specify first specific embodiment of the present invention below.
In conjunction with reference to figure 1 and Fig. 2 a, Fig. 2 b, Fig. 2 a is the cross-sectional view of Fig. 2 b along the a-a direction, and Fig. 2 b is the schematic top plan view of Fig. 2 a, and execution in step S11 provides substrate 20.In the present invention's first specific embodiment, the top layer of substrate 20 is a gate dielectric layer 21.The material of substrate 20 is the silicon or the SiGe of monocrystalline; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.In said substrate 20, be formed with (not shown) such as source region, drain region and isolation structure.The material of said gate dielectric layer 21 is a silica, also can be for well known to a person skilled in the art other materials.
In conjunction with reference to figure 1 and Fig. 3 a, Fig. 3 b, Fig. 3 a be the cross-sectional view of Fig. 3 b along the a-a direction, and Fig. 3 b is the schematic top plan view of Fig. 3 a, execution in step S12, the patterned sacrifice layer 22 of formation in said substrate 20.Because in the first embodiment of the invention, the top layer of substrate 20 is a gate dielectric layer 21, therefore in said substrate 20, forms patterned sacrifice layer 22 and just on gate dielectric layer 21, form patterned sacrifice layer 22.Method forming patterned sacrifice layer 22 in the said substrate 20 is: in said substrate 20, form sacrifice layer 22, in this specific embodiment, just on the gate dielectric layer 21 of substrate 20 top layers, form sacrifice layer 22; On said sacrifice layer 22, form the photoresist layer (not shown); Utilizing photoetching or impress said photoresist layer to form patterned photoresist layer, is the mask etching sacrifice layer with patterned photoresist layer afterwards, forms patterned sacrifice layer 22; Remove patterned photoresist layer.The material of sacrifice layer 22 is silicon nitride, metal, agraphitic carbon, carbon doped silicon or polymer.In practical implementation, need be with photoetching process or the graphical sacrifice layer of imprint process according to concrete selection of the material of sacrifice layer 22.
In conjunction with reference to figure 1 and Fig. 4 a, Fig. 4 b; Fig. 4 a is the cross-sectional view of Fig. 4 b along the a-a direction, and Fig. 4 b is the schematic top plan view of Fig. 4 a, execution in step S13; In said substrate 20, form rete 23; The upper surface of said rete 23 is equal with the upper surface of said patterned sacrifice layer 22, that is to say, rete 23 is formed in the substrate 20 of not graphical sacrifice layer 22 coverings.The method that forms rete 23 comprises: utilize vapour deposition to form rete 23, cover said substrate 20 and said patterned sacrifice layer 22; Said rete 23 is planarized to the upper surface that exposes said patterned sacrifice layer 22, makes the upper surface of rete 23 equal with the upper surface of patterned sacrifice layer 22.In this specific embodiment, rete 23 is a polysilicon layer.
In conjunction with reference to figure 1 and Fig. 5 a, Fig. 5 b; Fig. 5 a is the cross-sectional view of Fig. 5 b along the a-a direction; Fig. 5 b is the schematic top plan view of Fig. 5 a; Execution in step S14 forms graph layer 24 on said rete 23, said graph layer 24 defines rete 23 patterned figures jointly with patterned sacrifice layer 22.In this specific embodiment, graph layer 24 is patterned photoresist layer.On said rete 23, form photoresist layer, utilize exposure, the graphical said photoresist layer of developing process to form patterned photoresist layer.The figure of patterned photoresist layer and patterned sacrifice layer 22 both compositions has defined rete 23 graphical figures afterwards jointly.
In conjunction with reference to figure 1 and Fig. 6 a, Fig. 6 b, Fig. 6 a is the cross-sectional view of Fig. 6 b along the a-a direction, and Fig. 6 b is the schematic top plan view of Fig. 6 a, and execution in step S15 is the said rete 23 of mask etching with said graph layer 24, forms patterned rete 25.In this specific embodiment, rete 25 is a polysilicon layer, and patterned polysilicon layer is a grid.
In conjunction with reference to figure 1 and Fig. 7 a, Fig. 7 b, execution in step S16 removes said graph layer, patterned sacrifice layer.In the specific embodiment of the invention, graph layer 24 is patterned photoresist layer, utilizes ashing to remove patterned photoresist layer.In other embodiments, if the material of graph layer 24 is an other materials, then need change the corresponding method of removing graph layer according to the material of graph layer 24.Remove after the graph layer 24, utilize wet etching to remove said patterned sacrifice layer 22, the method for just utilizing selectivity to clean is removed patterned sacrifice layer 22, guarantees that cleaning and removing removes in the process of patterned sacrifice layer 22, does not damage substrate 20 basically.
More than in the graphic diaphragm layer of first embodiment, rete 25 is a polysilicon layer, graphical polysilicon layer has formed grid, so the method for the graphic diaphragm layer of this first embodiment also can be the method that forms grid.
In the present invention, rete 25 is not limited to polysilicon layer, can for example, can be to form the hard mask layer in the dummy grid process in the grid technique of back for needing the rete of patterned other materials in the semiconductor applications also.The cross-sectional view and the schematic top plan view of the structure that Fig. 8 a, Fig. 8 b form for the method for the graphic diaphragm layer of the present invention's second practical implementation; Wherein, Fig. 8 a is the cross-sectional view of Fig. 8 b along the a-a direction; Fig. 8 b is the schematic top plan view of Fig. 8 a, and this second specific embodiment is example explanation the present invention with the dummy grid that forms in the grid technique of back.
In second specific embodiment, the top layer of substrate 30 is followed successively by gate dielectric layer 31 and pseudo-grid layer 32, and said pseudo-grid layer 32 is formed on the said gate dielectric layer 31, and rete is a hard mask layer, and this hard mask layer is formed on the said pseudo-grid layer 32.The material of pseudo-grid layer 32 is a polysilicon among this second embodiment, but the material of pseudo-grid layer 32 is not limited to polysilicon, also can be for well known to a person skilled in the art other materials.The method of the graphical polysilicon layer of the method for the graphical hard mask layer of this second embodiment and first embodiment is basic identical, does not do at this and gives unnecessary details.Form patterned hard mask layer 33 through the graphical hard mask layer of method of the present invention, this patterned hard mask layer 33 has defined the figure that needs the dummy grid of formation.Grid technique forms in the process of grid after utilization, utilizes patterned hard mask layer 33 can form dummy grid for the pseudo-grid layer 32 of mask etching.In this second embodiment, the material of hard mask layer 33 is a silicon nitride, also can be for well known to a person skilled in the art other materials.
According to second embodiment, graphical hard mask layer defines the figure of dummy grid, and the present invention provides a kind of method that forms grid, forms patterned hard mask layer 33 with the method among second embodiment; With said patterned hard mask layer 33 is mask said pseudo-grid layer 32 of etching and gate dielectric layer 31 successively, and the pseudo-grid layer 32 after the etching forms dummy grid; Remove patterned hard mask layer 33, form interlayer dielectric layer, cover substrate, the upper surface of said interlayer dielectric layer is equal with the upper surface of said dummy grid; Remove said dummy grid and form the dummy grid groove; The filled conductive material forms grid in said dummy grid groove.
In this specific embodiment, the material of pseudo-grid layer 32 is a polysilicon layer, but the material of pseudo-grid layer 32 is not limited to polysilicon layer, also can be for well known to a person skilled in the art other materials.The material of gate dielectric layer 31 is a silica, but is not limited to silica.With patterned hard mask layer 33 is that mask utilizes dry etching etch polysilicon layer and gate dielectric layer 31 successively.
Behind etch polysilicon layer and the gate dielectric layer 31, remove patterned hard mask layer 33, utilize CVD method to form interlayer dielectric layer then; This interlayer dielectric layer covers polysilicon layer, gate dielectric layer 31 and the substrate 20 after the etching; Afterwards, utilize flatening process (can be chemical-mechanical planarization, CMP) the planarization interlayer dielectric layer; Remove interlayer dielectric layer on the polysilicon layer, make the upper surface of interlayer dielectric layer equal with the upper surface of polysilicon layer.The material of interlayer dielectric layer is low-k materials or ultralow k material, and wherein low-k materials is selected from SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON one of them or they combination in any.Ultralow k material is a black diamond.
After forming interlayer dielectric layer, utilize wet etching or dry etching, or both combinations are removed dummy grid, formation dummy grid groove.Utilize physical vapour deposition (PVD) or electric plating method filled conductive material in the dummy grid groove to form grid.This electric conducting material can be metal, also can be other electric conducting materials.
Based on the method for above-described formation grid, the present invention also provides a kind of method that forms MOS transistor, comprises that perhaps the method with above-described formation grid forms grid with the method formation grid of the graphical polysilicon layer of first embodiment.In the method for two kinds of formation MOS transistors, the method for the graphical polysilicon layer of first embodiment forms in the grid technology, before forming grid, in substrate, has formed source electrode, drain electrode; Form in the method for grid with the back grid technique, form after the grid, need be infused in ion and form source electrode and drain electrode in the grid substrate on two sides.
Need to prove, mention " equal " speech among the present invention, do not represent the surface of two kinds of materials equal fully, allow difference in height between them in certain error range.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (19)
1. the method for a graphic diaphragm layer is characterized in that, comprising:
Substrate is provided;
In said substrate, form patterned sacrifice layer;
In said substrate, form rete, the upper surface of said rete is equal with the upper surface of said patterned sacrifice layer;
On said rete, form graph layer, said graph layer and patterned sacrifice layer define the figure of membrane graphic jointly;
With said graph layer is the said rete of mask etching, forms patterned rete;
Remove said graph layer, patterned sacrifice layer.
2. the method for graphic diaphragm layer as claimed in claim 1 is characterized in that, said rete is a polysilicon layer;
The top layer of said substrate is a gate dielectric layer, and said polysilicon layer, patterned sacrifice layer are formed on the gate dielectric layer of said substrate;
Said patterned rete is a grid.
3. the method for graphic diaphragm layer as claimed in claim 1 is characterized in that, said rete is a hard mask layer;
The top layer of said substrate is followed successively by gate dielectric layer and pseudo-grid layer, and said pseudo-grid layer is formed on the said gate dielectric layer, and said hard mask layer is formed on the said pseudo-grid layer.
4. the method for graphic diaphragm layer as claimed in claim 3 is characterized in that, the material of said pseudo-grid layer is a polysilicon.
5. like the method for each described graphic diaphragm layer of claim 1～4, it is characterized in that the material of said sacrifice layer is silicon nitride, metal, agraphitic carbon, carbon doped silicon or polymer.
6. the method for graphic diaphragm layer as claimed in claim 5 is characterized in that, in said substrate, forms patterned sacrifice layer and comprises:
In said substrate, form sacrifice layer;
On said sacrifice layer, form photoresist layer;
Utilizing photoetching or impress said photoresist layer to form patterned photoresist layer, is the mask etching sacrifice layer with patterned photoresist layer afterwards, forms patterned sacrifice layer;
Remove patterned photoresist layer.
7. the method for graphic diaphragm layer as claimed in claim 6 is characterized in that, utilizes wet etching to remove said patterned sacrifice layer.
8. like the method for each described graphic diaphragm layer of claim 1～4, it is characterized in that said graph layer is patterned photoresist layer;
Comprise at formation graph layer on the said rete: on said rete, form photoresist layer, utilize exposure, the graphical said photoresist layer of developing process to form patterned photoresist layer.
9. the method for graphic diaphragm layer as claimed in claim 8 is characterized in that, utilizes ashing to remove said graph layer.
10. like the method for each described graphic diaphragm layer of claim 1～4, it is characterized in that the method for said formation rete comprises:
Utilize vapour deposition to form rete, cover said substrate and said patterned sacrifice layer;
Said rete is planarized to the upper surface that exposes said patterned sacrifice layer, makes the upper surface of rete equal with the upper surface of patterned sacrifice layer.
11. the method like claim 2 or 3 described graphic diaphragm layers is characterized in that, the material of said gate dielectric layer is a silica.
12. the method for graphic diaphragm layer as claimed in claim 3 is characterized in that, the material of said hard mask layer is a silicon nitride.
13. a method that forms grid is characterized in that, comprising:
Form patterned hard mask layer with claim 3 or 4 described methods;
With said patterned hard mask layer is the mask said pseudo-grid layer of etching, gate dielectric layer successively, and the pseudo-grid layer after the etching forms dummy grid;
Form interlayer dielectric layer, cover said substrate, the upper surface of said interlayer dielectric layer is equal with the upper surface of said dummy grid;
Remove said dummy grid and form the dummy grid groove;
The filled conductive material forms grid in said dummy grid groove.
14. the method for formation grid as claimed in claim 13 is characterized in that, said electric conducting material is a metal.
15. the method for formation grid as claimed in claim 14 is characterized in that, the material of said hard mask layer is a silicon nitride.
16. the method for formation grid as claimed in claim 13 is characterized in that, the material of said interlayer dielectric layer is low-k materials or ultralow k material.
17. the method for formation grid as claimed in claim 16 is characterized in that, said low-k materials is selected from SiO
2, SiOF, SiCOH, SiO, SiCO, SiCON one of them or they combination in any.
18. the method for formation grid as claimed in claim 16 is characterized in that, said ultralow k material is a black diamond.
19. a method that forms MOS transistor is characterized in that, comprises with claim 2,13～18 each described methods forming grid.
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| CN106158758A (en) * | 2015-04-08 | 2016-11-23 | 北大方正集团有限公司 | Mask plate assembly, the preparation method of surface-mounted integrated circuit and surface-mounted integrated circuit |
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