CN105914178A - Shallow trench isolation structure manufacturing method - Google Patents
Shallow trench isolation structure manufacturing method Download PDFInfo
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- CN105914178A CN105914178A CN201610307225.0A CN201610307225A CN105914178A CN 105914178 A CN105914178 A CN 105914178A CN 201610307225 A CN201610307225 A CN 201610307225A CN 105914178 A CN105914178 A CN 105914178A
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- Prior art keywords
- isolation structure
- layer
- manufacture method
- fleet plough
- plough groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a shallow trench isolation structure manufacturing method, comprising the steps of: successively depositing an oxide layer and a mask layer on a substrate; forming an opening at least located in the mask layer; forming a sidewall on the sidewall of the opening; employing the sidewall and the mask layer as a mask to etch the substrate, and forming a trench in the substrate; removing the sidewall; and filling insulating materials in the opening and the trench to form a shallow trench isolation structure. The method can change the shape of the shallow trench isolation structure in later etching processes through forming the sidewall, and reduce or eliminate side ditches of a shallow trench isolation region and an active region, thereby reducing reverse direction narrow channel effects and improving device performance.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to shallow trench isolation junction
The manufacture method of structure.
Background technology
At field of semiconductor manufacture, and the development of miniaturization, isolation of semiconductor device integrated along with semiconductor device
The size of the isolation structure of part reduces the most therewith.Therefore, current shallow trench isolation (Shallow Trench
Isolation, STI) structure becomes the CMOS complementary metal-oxide-semiconductor of deep sub-micron era
The main flow isolation work that (Complementary Metal-Oxide-Semiconductor, CMOS) device manufactures
Skill.
Fleet plough groove isolation structure is as a kind of device separation, and traditional concrete technology is as follows: with reference to Fig. 1,
One substrate 101 is provided, is sequentially formed pad oxide skin(coating) 102, silicon nitride layer 103 and on its surface
Photoresist layer 104；With reference to Fig. 2, in photoresist layer 104, after exposure imaging, form opening A, described opening
A has the shape corresponding with the isolation structure defining active area；With reference to Fig. 3, utilize have opening A (as
Shown in Fig. 1) photoresist layer 104 as mask, etching formation runs through described silicon nitride layer 103 and pad oxygen
Compound layer 102, until the isolated groove B in described substrate 101, removes photoresist layer 104, finally at Fig. 3
In isolated groove B in deposited oxide silicon materials, described silica material is filled full isolated groove B and is also covered
The silicon nitride layer 103 of isolated groove B both sides, removes oxygen unnecessary on silicon nitride layer 103 by CMP
Silicon nitride material, and in follow-up technique, also involve removal silicon nitride layer 103 and removal pad oxide skin(coating)
The step of 102, ultimately forms fleet plough groove isolation structure C, as shown in Figure 4.
The manufacture process of above-mentioned tradition sti structure can cause under the silicon oxide in fleet plough groove isolation structure C
Recessed, the shape of formation concave downward, referred to as gutter (divot) 105, as shown in Figure 4, meeting at gutter 105
Produce fringe field.Along with the size of semiconductor device is more and more less, the width of device active region will more come
The most shallow, add during tradition sti structure manufactures the gutter occurred, thus can cause threshold voltage decreasing,
Thus occur Inverse-Narrow-Width-Effect that device creepage increases (Inverse Narrow Width Effect,
INWE), this effect can produce the most serious impact to the characteristic of device and circuit.
Therefore, for above-mentioned technical problem, it is necessary to provide the manufacture method of new fleet plough groove isolation structure.
Summary of the invention
The technical problem to be solved be reduce in fleet plough groove isolation structure because of gutter cause the narrowest
Channelling effect, improves the performance of device.
For solving above-mentioned technical problem, the manufacture method of the fleet plough groove isolation structure that the present invention provides, including such as
Lower step:
Substrate is sequentially depositing oxide layer and mask layer；
Form an opening, be located at least in described mask layer；
The sidewall of described opening is formed side wall；
With described side wall and mask layer as mask, described substrate is performed etching, described substrate is formed one
Groove；
Remove described side wall；And
Fill insulant in described opening and groove, forms fleet plough groove isolation structure.
Optionally, described opening is positioned in described oxide layer.
Optionally, during described opening is positioned at described mask layer and oxide layer.
Optionally, forming a floating gate layer between described oxide layer and mask layer, described opening is also located at
In described floating gate layer.
Further, the step forming side wall on the sidewall of described opening includes: form a sacrifice layer；
Etching forms described side wall.
Further, described sacrifice layer is carried out an annealing process, it is also preferred that the left carry out institute in a nitrogen environment
State annealing process.
Further, the material of described sacrifice layer is oxide, it is also preferred that the left described sacrifice layer is positive silicic acid second
Ester (Tetraethyl Orthosilicate, TEOS) obtains with oxygen generation chemical reaction deposit.
Further, described sacrifice layer is etched to form described side wall by self-registered technology.
Further, wet-etching technology is used to remove described side wall.
Further, in described opening and groove after fill insulant, use chemically-mechanicapolish polish into
Row planarisation step eventually stops on described mask layer, finally, removes described mask layer final to be formed
Fleet plough groove isolation structure.
Compared with prior art, the method have the advantages that
The present invention by formed described side wall make sti structure can reduce or eliminate shallow channel isolation area with
The gutter (divot) of active-surface, improves the threshold value at isolation area and active-surface in semiconductor device
Voltage, reduces the electric leakage of edge's device, it is thus possible to reduce the Inverse-Narrow-Width-Effect of fleet plough groove isolation structure,
Improve the performance of device.
Accompanying drawing explanation
Fig. 1 to Fig. 4 be conventional shallow trench isolation structure manufacture method in structural representation corresponding to each step；
Fig. 5 is the flow chart of the manufacture method of fleet plough groove isolation structure in one embodiment of the invention；
Fig. 6 to Figure 13 is that in one embodiment of the invention, in the manufacture method of fleet plough groove isolation structure, each step is corresponding
Structural representation.
Figure 14 to Figure 15 is to walk accordingly in the manufacture method of fleet plough groove isolation structure in another embodiment of the present invention
Rapid corresponding structural representation.
Detailed description of the invention
Below in conjunction with flow chart and schematic diagram, the manufacture method of fleet plough groove isolation structure of the present invention is carried out more detailed
Thin description, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can repair
Change invention described herein, and still realize the advantageous effects of the present invention.Therefore, description below should be by
Be interpreted as those skilled in the art is widely known, and is not intended as limitation of the present invention.
Referring to the drawings the present invention the most more particularly described below in the following passage.According to following explanation and
Claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the simplest
The form changed and all use non-ratio accurately, only in order to convenient, aid in illustrating the embodiment of the present invention lucidly
Purpose.
The core concept of the present invention is, the present invention provides the manufacture method of a kind of fleet plough groove isolation structure, as
Shown in Fig. 5, comprise the steps:
S1, on substrate, it is sequentially depositing oxide layer and mask layer；
S2, form an opening, be located at least in described mask layer；
S3, on the sidewall of described opening formed side wall；
S4, with described side wall and mask layer as mask, described substrate is performed etching, shape in described substrate
Become a groove；
S5, remove described side wall；And
S6, in described opening and groove fill insulant, formed fleet plough groove isolation structure.
The present invention by formed described side wall make sti structure can reduce or eliminate shallow channel isolation area with
The gutter (divot) of active-surface, improves the threshold value at isolation area and active-surface in semiconductor device
Voltage, reduces the electric leakage of edge's device, it is thus possible to reduce the Inverse-Narrow-Width-Effect of fleet plough groove isolation structure,
Improve the performance of device.
It is exemplified below the embodiment of the manufacture method of described fleet plough groove isolation structure, to understand the explanation present invention's
Content, it is understood that, present disclosure is not restricted to following example, and other pass through this area
The improvement of the routine techniques means of those of ordinary skill is also within the thought range of the present invention.
Embodiment 1:
As it is shown in figure 5, first, step S1, described substrate 201 is sequentially depositing oxide layer 202, covers
Film layer 203, as shown in Figure 6, in embodiments of the present invention, described substrate 201 can include the most below
The material that material maybe can use, or any material of device, circuit or epitaxial layer can be formed thereon.
In other alternative embodiments, described substrate 201 can include such as doped silicon, GaAs, gallium arsenide-phosphide,
The Semiconductor substrate of indium phosphide, germanium or silicon-Germanium substrate.Such as, described substrate 201 can include except
Outside semiconductor substrate section, such as SiO2Or Si3N4The insulating barrier of layer etc.Therefore, described substrate
201 are positioned at the multilamellar key element of layer interested or beneath portions for usually definition.Equally, described substrate
201 can be cambial arbitrarily other substrates, such as glass or metal level on it.
Preferably, described mask layer 203 can include nitride, but in other embodiments, mask layer
203 can include other suitable materials, if its performance make its as the stop-layer for polishing step,
It is made to have corrosion stability, and its for subsequent etching (such as, side wall (as described below) wet etching)
Etching (such as, producing the self-registered technology etching of side wall (as described below)) tool for Anisotropic substrate
There is corrosion stability.
Perform step S2, form an opening D, be located at least in described mask layer 203.Described opening D can
To be realized by photoetching known to a person of ordinary skill in the art and etch process.Such as, photoetching and etching
Technique includes following consecutive steps.First, by spin coating, photoresist is coated in described mask layer 203
On, such as, photoresist oxidant layer can have the thickness of several microns, and can be by can serve as light
Cause polymer (the such as polyvinyl cinnamate or based on thermoplastic phenolic resin of any appropriate of resist
Polymer) constitute.Then, described photoresist oxidant layer is irradiated by UV light through the mask applied.
After illumination, to development of photoresist, depend on the type of used photoresist, cause photic
The irradiation part (positive resist) of resist or the removal of irradiated portion (negative resist).Then make
Described mask layer 203 is performed etching as mask by developed photoresist oxidant layer, the most logical
Cross the remainder using organic solvent to remove photoresist oxidant layer, form the institute running through described mask layer 203
State opening D, the most described opening D to be positioned in described oxide layer 202, as shown in Figure 7.
Perform step S3, the sidewall of described opening D is formed side wall.
First, described opening D forms a sacrifice layer 204, as shown in Figure 8, such as, described sacrifice
The material of layer 204 can be oxide, conventional obtains with oxygen generation chemical reaction deposit such as TEOS,
It is also preferred that the left described sacrifice layer 204 is carried out the annealing process under a nitrogen environment, make described sacrifice layer 204
Material compactness more preferable, in other embodiments, anneal environment can be other noble gases.
Then in described opening D, form the side wall with described sacrifice layer 204, as it is shown in figure 9, described
Side wall can be realized by self-registered technology known to a person of ordinary skill in the art etching, does not goes to live in the household of one's in-laws on getting married at this
State.
Perform step S4, with described side wall and mask layer 203 as mask, described substrate 201 performed etching,
Formed and run through described oxide layer 202 until a groove E in described substrate 201, as shown in Figure 10, this step
Can be realized by photoetching technique known to a person of ordinary skill in the art in Zhou, therefore not to repeat here.
Perform step S5, remove described side wall, use wet-etching technology to remove described side wall, grasp in reality
In work, etching while described side wall, be positioned at described oxide layer 202 below described side wall part and
All also can be etched away, as shown in figure 11.
Execution step S6, fill insulant 205 in described opening D and groove E, as shown in figure 12,
Conventional insulant is silicon dioxide.But in other description, insulant 205 is referred to as two
Silicon oxide layer 205, it should be understood that this is only for ease of understanding, and is not limited to.It follows that
Being planarized described silicon dioxide layer 205, such as, this is by for those of ordinary skill in the art
Known to the buffer of such as chemically mechanical polishing (Chemical Mechanical Polishing, CMP) etc
Skill realizes, and removes the unnecessary silicon dioxide layer 205 on described pad silicon nitride layer 203, finally, removes
Described mask layer 203 and described oxide layer 202, such as, use phosphoric acid to clean and remove described silicon nitride layer 203,
Using Fluohydric acid. wet etching to remove described oxide layer 202, these methods are all that those of ordinary skill in the art are public
Knowing, therefore not to repeat here, ultimately forms fleet plough groove isolation structure F, as shown in figure 13.
The fleet plough groove isolation structure F made in the embodiment of the present invention 1 compares traditional sti structure C, does not deposits
At gutter 105.
Embodiment 2:
Referring to Figure 14-Figure 15, wherein, in Figure 14-Figure 15, reference number represents and Fig. 6-Figure 13 phase
With the statement structure identical with the first embodiment.The manufacture method of described second embodiment and described first
The manufacture method of embodiment is essentially identical, and its difference is: in step s 2, as shown in figure 14, is formed
One opening G, described opening G are positioned in described mask layer 203 and oxide layer 202.Correspondingly, in step
In S3, the side wall formed on the sidewall of described opening G, as shown in figure 15.
Then, in succession perform with step S4 in described first embodiment, S5 and S6, the embodiment of the present invention 2
The final fleet plough groove isolation structure made is identical with the fleet plough groove isolation structure in embodiment 1, compares traditional
Sti structure C, does not haves gutter 105 yet.
It addition, when above-mentioned fleet plough groove isolation structure is applied in flush memory device, above-mentioned manufacture method also includes
A floating gate layer preparing memorizer is formed between described oxide layer 202 and mask layer 203, described floating
Putting the dielectric material of grid layer is polysilicon or silicon nitride or the nano crystal material with electric conductivity, above-mentioned
The opening formed in manufacture method is also located in described floating gate layer.
To sum up, the manufacture method of fleet plough groove isolation structure of the present invention can be changed by the described side wall of formation
Become the shape of sti structure in subsequent etching processes, it is possible to reduce or eliminate shallow channel isolation area and active area
The gutter (divot) at edge, improves the threshold voltage at isolation area and active-surface in semiconductor device,
Reduce the electric leakage of edge's device, it is thus possible to reduce the Inverse-Narrow-Width-Effect of fleet plough groove isolation structure, improve
The performance of device.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. the manufacture method of fleet plough groove isolation structure, it is characterised in that comprise the steps:
Substrate is sequentially depositing oxide layer and mask layer；
Form an opening, be located at least in described mask layer；
The sidewall of described opening is formed side wall；
With described side wall and mask layer as mask, described substrate is performed etching, formed in described substrate
One groove；
Remove described side wall；And
Fill insulant in described opening and groove, forms fleet plough groove isolation structure.
2. the manufacture method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that described in open
Interruption-forming is in described oxide layer.
3. the manufacture method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that described in open
Mouth is positioned in described mask layer and oxide layer.
4. the manufacture method of the fleet plough groove isolation structure as described in any one in claims 1 to 3, it is special
Levying and be, described manufacture method also includes:
A floating gate layer is formed between described oxide layer and mask layer；
Described opening is also located in described floating gate layer.
5. the manufacture method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that described
The step forming side wall on the sidewall of opening includes:
Form a sacrifice layer；
Etching forms described side wall.
6. the manufacture method of fleet plough groove isolation structure as claimed in claim 5, it is characterised in that described system
Make method also to include described sacrifice layer is carried out an annealing process.
7. the manufacture method of fleet plough groove isolation structure as claimed in claim 6, it is characterised in that at nitrogen
Described annealing process is carried out under environment.
8. the manufacture method of fleet plough groove isolation structure as claimed in claim 5, it is characterised in that described sacrificial
The material of domestic animal layer is oxide.
9. the manufacture method of fleet plough groove isolation structure as claimed in claim 8, it is characterised in that described sacrificial
The material of domestic animal layer is for by tetraethyl orthosilicate and oxygen generation chemical reaction deposit.
10. the manufacture method of fleet plough groove isolation structure as claimed in claim 5, it is characterised in that by certainly
Alignment Process etches described sacrifice layer to form described side wall.
The manufacture method of 11. fleet plough groove isolation structures as claimed in claim 1, it is characterised in that use wet
Method etching technics removes described side wall.
The manufacture method of 12. fleet plough groove isolation structures as claimed in claim 1, it is characterised in that described system
Make method also to include: in described opening and groove after fill insulant, use chemically-mechanicapolish polish into
Row planarisation step eventually stops on described mask layer.
The manufacture method of 13. fleet plough groove isolation structures as claimed in claim 1, it is characterised in that described system
Make method also to include: after described planarisation step, remove described mask layer to form final shallow trench
Isolation structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610307225.0A CN105914178B (en) | 2016-05-11 | 2016-05-11 | The production method of fleet plough groove isolation structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610307225.0A CN105914178B (en) | 2016-05-11 | 2016-05-11 | The production method of fleet plough groove isolation structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111192849A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
| CN111933568A (en) * | 2020-09-25 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Manufacturing method of shallow trench isolation structure |
| CN113140500A (en) * | 2021-04-19 | 2021-07-20 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
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| CN102263052A (en) * | 2010-05-24 | 2011-11-30 | 无锡华润上华半导体有限公司 | Forming method of STI (shallow trench isolation) |
| CN102468215A (en) * | 2010-11-19 | 2012-05-23 | 中国科学院微电子研究所 | Trench isolation structure and forming method thereof |
| CN102569166A (en) * | 2012-03-09 | 2012-07-11 | 上海宏力半导体制造有限公司 | Shallow groove isolation manufacturing method capable of improving stress and semiconductor device manufacturing method |
| CN102931125A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
| CN104425347A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of shallow trench isolation |
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| CN102263052A (en) * | 2010-05-24 | 2011-11-30 | 无锡华润上华半导体有限公司 | Forming method of STI (shallow trench isolation) |
| CN102468215A (en) * | 2010-11-19 | 2012-05-23 | 中国科学院微电子研究所 | Trench isolation structure and forming method thereof |
| CN102931125A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
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| CN111192849A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
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| CN111933568A (en) * | 2020-09-25 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Manufacturing method of shallow trench isolation structure |
| CN111933568B (en) * | 2020-09-25 | 2021-02-09 | 晶芯成(北京)科技有限公司 | Manufacturing method of shallow trench isolation structure |
| CN113140500A (en) * | 2021-04-19 | 2021-07-20 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
| CN113140500B (en) * | 2021-04-19 | 2023-08-22 | 上海积塔半导体有限公司 | Method for manufacturing semiconductor structure |
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| CN105914178B (en) | 2019-07-26 |
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