CN102931125A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102931125A CN102931125A CN2011102287248A CN201110228724A CN102931125A CN 102931125 A CN102931125 A CN 102931125A CN 2011102287248 A CN2011102287248 A CN 2011102287248A CN 201110228724 A CN201110228724 A CN 201110228724A CN 102931125 A CN102931125 A CN 102931125A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 120
- 230000003647 oxidation Effects 0.000 claims abstract description 120
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 120
- 238000000034 method Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 230000008569 process Effects 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 210000003323 beak Anatomy 0.000 abstract description 30
- 230000000694 effects Effects 0.000 abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 238000002955 isolation Methods 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 125000006239 protecting group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Local Oxidation Of Silicon (AREA)
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Abstract
The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the following steps of: providing a substrate, wherein the substrate is provided with a pad oxide layer; forming oxide barrier layers with isolation region patterns on the pad oxide layer; forming compensated side walls adjacent to the edges of the oxide barrier layers in the isolation region patterns of the oxide barrier layers with the isolation region patterns; and forming a field oxide layer in an isolation region of the substrate by using the oxide barrier layers with the isolation region patterns and the compensated side walls as masks. By the manufacturing method for the semiconductor device, the length of beaks which are formed when the field oxide layer is laterally diffused to positions near the edges of the oxide barrier layers in the local oxidation of silicon (LOCOS) process can be effectively controlled, and a beak effect can be reduced or avoided, so that the number of effective tube cores on the substrate can be increased.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of semiconductor device and manufacture method thereof.
Background technology
In fabrication of semiconductor device, general normal employing silicon selective oxidation (Local Oxidation ofSilicon, LOCOS) technique forms field oxide, and described field oxide plays buffer action to the active area of device.Existing LOCOS technical process generally comprises following several step:
1, at silicon substrate with the thermal oxidation mode thin silicon dioxide of one deck of growing, afterwards at silicon dioxide deposition one deck silicon nitride.The purpose of growth silicon dioxide is for fear of silicon nitride surface of silicon to be caused stress damage.
2, spin coating photoresist on silicon nitride, and expose with the mask plate of definition isolated area, develop afterwards, form the photoresist layer with isolated area pattern.
3, carry out etching with described photoresist layer with isolated area pattern as mask, will keep certain thickness silicon dioxide during etching, avoid silicon substrate to sustain damage.
4, utilize isolated area silicon nitride in addition as the mask growth field oxide of selective oxidation.The thickness of described field oxide can be chosen according to the characteristic of device.
With reference to figure 1, Fig. 1 shows the cross-sectional view of the semiconductor device that forms according to above-mentioned LOCOS processing step, and this semiconductor device comprises: silicon substrate 1; Be positioned at the thinner silicon dioxide 2 on described silicon substrate 1 surface; Be positioned at the silicon nitride 3 on the described silicon dioxide 2; Be positioned at described silicon substrate 1, be used for the field oxide 4 of isolation active area.According to above-mentioned LOCOS processing step, when carrying out selective oxidation in the 4th step, the field oxide 4 of growth is understood horizontal proliferation, thereby can be penetrated into the below of silicon nitride 3, forms " beak " zone 5 near the edge of silicon nitride 3 mask layers.Because the area of active area has been occupied in " beak " zone 5, therefore the effective area of active area has correspondingly reduced in the semiconductor device, thereby cause the effectively minimizing of tube core number on the silicon substrate.
Above-mentioned because occupying " beak effect " problem that active region area causes in " beak " zone in order to solve, the normal employing reduces the size that the thickness of silicon dioxide below the silicon nitride is controlled " beak " in the existing technique, in general, the thickness of silicon dioxide is thinner, and " beak " is less.But the thickness of silicon dioxide is subject to the restriction of silicon nitride; the too thin easy increase silicon nitride of silicon dioxide is applied to the stress on the surface of silicon; and then do not have the protection silicon substrate effect; therefore, the method that relies on the thickness that reduces silicon dioxide to control " beak " size in the traditional handicraft can not be implemented effectively.
Summary of the invention
In view of this, the invention provides a kind of semiconductor device and manufacture method thereof, the method can be controlled " beak " size effectively, and then reduces or avoid the generation of " beak effect ", so that can produce more effectively tube core on the silicon substrate.
For achieving the above object, the invention provides following technical scheme:
The invention provides a kind of method, semi-conductor device manufacturing method, the method comprises:
Substrate is provided, has pad oxide in the described substrate;
Form the oxidation barrier layer with isolated area pattern at described pad oxide;
In the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge;
Have the oxidation barrier layer of isolated area pattern and compensate side wall as mask take described, in the isolated area of described substrate, form field oxide.
Preferably, in the said method, in the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge, specifically comprise:
Form layer of compensation at described oxidation barrier layer with isolated area pattern;
For anti-carving the barrier layer, adopt dry etch process that described layer of compensation is anti-carved with described suprabasil pad oxide, in the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge.
Preferably, said method also comprises:
Remove described oxidation barrier layer and compensation side wall with isolated area pattern.
Preferably, in the said method, form the oxidation barrier layer with isolated area pattern at described pad oxide, specifically comprise:
Form oxidation barrier layer at described pad oxide;
Form the photoresist layer with isolated area pattern at described oxidation barrier layer;
As adopting etching technics, mask forms the oxidation barrier layer with isolated area pattern take described photoresist layer with isolated area pattern at described pad oxide;
Remove described photoresist layer with isolated area pattern.
Preferably, in the said method, the material of described compensation side wall is silicon nitride.
Preferably, in the said method, described oxidation barrier layer is silicon nitride layer.
Preferably, in the said method, in the isolated area of described substrate, form field oxide and adopt wet process oxidation technology.
The present invention also provides a kind of semiconductor device, and this semiconductor device comprises:
Substrate;
Be positioned at described suprabasil pad oxide;
Be positioned at the oxidation barrier layer with isolated area pattern on the described pad oxide;
Be arranged in described have the isolated area pattern of the oxidation barrier layer of isolated area pattern, the compensation side wall adjacent with described oxidation barrier layer edge;
Be positioned at the field oxide of described substrate isolated area.
Preferably, in the above-mentioned semiconductor device, the material of described oxidation barrier layer and compensation side wall is silicon nitride.
Preferably, in the above-mentioned semiconductor device, the material of described pad oxide and field oxide is silica.
Can find out from technique scheme, method, semi-conductor device manufacturing method provided by the present invention comprises: substrate is provided, has pad oxide in the described substrate; Form the oxidation barrier layer with isolated area pattern at described pad oxide; In the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge; Have the oxidation barrier layer of isolated area pattern and compensate side wall as mask take described, in the isolated area of described substrate, form field oxide.Method, semi-conductor device manufacturing method provided by the present invention, owing in the isolated area pattern of the oxidation barrier layer with isolated area pattern, having formed the compensation side wall adjacent with the oxidation barrier layer edge, therefore, when follow-up formation field oxide, described compensation side wall has played barrier effect, thereby so that near " beak " zone that described field oxide is penetrated into when spreading in the horizontal the oxidation barrier layer edge reduces, that is: so that described field oxide is occupied the area of active area has reduced, form the width of compensation side wall by control, can effectively control the length of described " beak ", and then can reduce or avoid the generation of " beak effect ", thereby can increase in the substrate the effectively number of tube core.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the cross-sectional view of a kind of semiconductor device of the prior art;
The schematic flow sheet of a kind of method, semi-conductor device manufacturing method that Fig. 2 provides for the embodiment of the invention;
The cross-sectional view of device in the method, semi-conductor device manufacturing method that Fig. 3～Fig. 9 provides for the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Just as described in the background section; by existing LOCOS technical process; often can near the edge of silicon nitride mask layer, form " beak " zone at the formation field oxide; be somebody's turn to do " beak " zone and will occupy the area of active area; and then so that the effective decreased number of tube core on the silicon substrate, Here it is so-called " beak effect ".Described in order to alleviate " beak effect ", the normal method that reduces silicon nitride below silicon dioxide thickness that adopts in the existing technique, the thickness of considering described silicon dioxide is original just thinner, therefore, if make its attenuation, the stress that then will cause silicon nitride to be applied on the silicon substrate is larger again, and then can cause defective at described silicon substrate, therefore, available technology adopting reduces silicon dioxide thickness and can not be implemented with the method that overcomes " beak effect ".
Based on this, the embodiment of the invention provides a kind of method, semi-conductor device manufacturing method, the method is under the prerequisite that does not reduce silicon dioxide thickness, realize reducing or avoiding the generation of " beak effect " by another new approach, the method specifically comprises: substrate is provided, has pad oxide in the described substrate; Form the oxidation barrier layer with isolated area pattern at described pad oxide; In the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge; Have the oxidation barrier layer of isolated area pattern and compensate side wall as mask take described, in the isolated area of described substrate, form field oxide.
Method, semi-conductor device manufacturing method provided by the present invention, owing in the isolated area pattern of the oxidation barrier layer with isolated area pattern, having formed the compensation side wall adjacent with the oxidation barrier layer edge, therefore, when in the isolated area of follow-up substrate, forming field oxide, described compensation side wall will play barrier effect, thereby so that near " beak " zone that described field oxide is penetrated into when spreading in the horizontal the oxidation barrier layer edge reduces, namely so that described field oxide is occupied the area of active area has reduced.Method, semi-conductor device manufacturing method provided by the present invention, by controlling the width of formed compensation side wall, can effectively control the length of described " beak ", and then can reduce or avoid the generation of " beak effect ", be conducive to increase the number of effective tube core in the substrate.
Describe semiconductor device provided by the present invention and manufacture method thereof in detail below in conjunction with drawings and Examples.
With reference to figure 2, the schematic flow sheet of a kind of method, semi-conductor device manufacturing method that Fig. 2 provides for the embodiment of the invention, the method specifically comprises:
Step S1: substrate is provided.
Described substrate also can be described as substrate or substrate etc., and substrate described in the present embodiment is silicon substrate, and certainly, among other embodiment, described substrate can also be other semi-conducting materials such as germanium, indium phosphide or GaAs.
Step S2: form pad oxide in described substrate.
With reference to figure 3, (thickness is about layer to adopt thermal oxidation technology to grow in described substrate 101 in the embodiment of the invention
) pad oxide 102, at the bottom of the effect of described pad oxide is protecting group, excessive and to the substrate injury with oxidation barrier layer (the being generally silicon nitride layer) stress of avoiding follow-up formation.
Step S3: form the oxidation barrier layer with isolated area pattern at described pad oxide.
This step can comprise again following several step:
Step S31: form oxidation barrier layer at described pad oxide.
With reference to figure 4, deposit one deck oxidation barrier layers 103 by chemical gaseous phase depositing process at described pad oxide 102 in this step, oxidation barrier layer described in the present embodiment 103 is silicon nitride layer.
Step S32: form the photoresist layer with isolated area pattern at described oxidation barrier layer.
With reference to figure 5, spin coating photoresist layer on described oxidation barrier layer 103 at first, then take mask plate with isolated area pattern as mask described photoresist layer is exposed, develop afterwards, form the photoresist layer 104 with isolated area pattern at described oxidation barrier layer 103.
Step S33: form the oxidation barrier layer with isolated area pattern at described pad oxide as mask adopts etching technics take described photoresist layer with isolated area pattern.
With reference to figure 6, has the photoresist layer 104 of isolated area pattern as mask take described, adopt etching technics that described oxidation barrier layer is carried out etching, owing to there not being photoresist to hide on the oxidation barrier layer at corresponding isolated area position, therefore the oxidation barrier layer at corresponding isolated area position is etched away, thereby formed the oxidation barrier layer 105 (can be called for short oxidation barrier layer 105) with isolated area pattern.Described oxidation barrier layer 105 with isolated area pattern will play barrier effect in the subsequent oxidation technical process, that is: there is not the ground of oxidation barrier layer can carry out oxidation growth in the corresponding isolated area, therefore existence owing to oxidation barrier layer beyond the isolated area can not carry out oxidation growth, thereby so that oxidizing process is the selective oxidation growth.
Step S34: remove described photoresist layer with isolated area pattern.
Step S4: in the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge.
With reference to figure 7 and Fig. 8, at first form layer of compensation 106 at described oxidation barrier layer 105 with isolated area pattern, the thickness of layer of compensation described in the present embodiment 106 is
Then with the pad oxide 102 in the described substrate 101 for anti-carving barrier layer (or anti-carving cutoff layer), adopt dry etch process that described layer of compensation 106 is anti-carved, final result is: anti-carved most layers of compensation (comprise on the oxidation barrier layer 105 and pad oxide 102 on layer of compensation 106), the edge of oxidation barrier layer 105 in described isolated area pattern (or claiming on side wall) has kept the partial-compensation layer.Partial-compensation layer with oxidation barrier layer 105 edges in the described isolated area pattern in the embodiment of the invention is called compensation side wall 107, this compensation side wall 107 has identical effect with described oxidation barrier layer 105 with isolated area pattern, and both all play barrier oxidation in the subsequent oxidation technical process.
Because described pad oxide 102 is for anti-carving the barrier layer, therefore, when etching into described pad oxide 102, just stop, but because the thinner thickness of described pad oxide 102, therefore, can etch away unavoidably the part pad oxide (as shown in Figure 8) at corresponding isolated area position in the etching process, the part pad oxide at described corresponding isolated area position is etched away, and the formation of subsequent fields oxide layer be there is no impact.
The material of layer of compensation described in the embodiment of the invention and oxidation barrier layer is identical, also is silicon nitride layer.
Step S5: have the oxidation barrier layer of isolated area pattern and compensate side wall as mask take described, in the isolated area of described substrate, form field oxide.
With reference to figure 9, have the oxidation barrier layer 105 of isolated area pattern and compensate side wall 107 as mask take described, adopt wet process oxidation technology in the isolated area of described substrate 101, to form field oxide 108.The thickness of formed field oxide 108 exists
Between.
In the embodiment of the invention, owing in the isolated area pattern of the oxidation barrier layer 105 with isolated area pattern, having the compensation side wall 107 adjacent with described oxidation barrier layer 105 edges, and described compensation side wall 107 can not be oxidized with oxidation barrier layer 105, therefore, both all play the effect of barrier oxidation, thereby only do not have the position growth field oxide 108 that compensates side wall 107 in isolated area.Described field oxide 108 all has diffusion in the horizontal and vertical directions, its diffusion in a lateral direction will make it extend to the bottom (even can extend to oxidation barrier layer 105 bottoms) of compensation side wall 107, and because the barrier oxidation effect of described compensation side wall 107, therefore, described field oxide 108 diffuse in a lateral direction oxidation barrier layer 105 edges " beak " zone greatly weakened.By controlling the width of described compensation side wall 107, can reduce the length of " beak " or avoid the generation of " beak ".
Step S6: remove described oxidation barrier layer and compensation side wall with isolated area pattern.
As from the foregoing, method, semi-conductor device manufacturing method provided by the present invention, after substrate formation has the oxidation barrier layer of isolated area pattern, not directly to carry out the growth of field oxide as mask take the oxidation barrier layer with isolated area pattern, but in the isolated area of described oxidation barrier layer with isolated area pattern, form the compensation side wall, and the edge of oxidation barrier layer is adjacent in described compensation side wall and the isolated area, and then carries out the growth of field oxide as mask take described oxidation barrier layer and compensation side wall with isolated area pattern.Among the present invention owing in described isolated area, there being the compensation side wall adjacent with the oxidation barrier layer edge, therefore described compensation side wall plays barrier effect to the growth of field oxide, this barrier effect can reduce or stop described field oxide to produce " beak " zone in vicinity, described oxidation barrier layer edge, and then can reduce or avoid described field oxide to occupy the area of active area, produce more effective tube core thereby can be beneficial in substrate.
The above describes method, semi-conductor device manufacturing method provided by the present invention in detail, and the below introduces semiconductor device provided by the present invention.
With reference to figure 9, semiconductor device provided by the present invention comprises: substrate 101; Be positioned at the pad oxide 102 in the described substrate 101; Be positioned at the oxidation barrier layer with isolated area pattern 105 on the described pad oxide 102; Be arranged in described have the isolated area pattern of the oxidation barrier layer 105 of isolated area pattern, the compensation side wall 107 adjacent with described oxidation barrier layer 105 edges; Be positioned at the field oxide 108 of the isolated area of described substrate 101.
The material of oxidation barrier layer described in the embodiment of the invention 105 and compensation side wall 107 is silicon nitride; The material of described pad oxide 102 and field oxide 108 is silica.
Semiconductor device provided by the present invention, owing in the isolated area pattern of the oxidation barrier layer 105 with isolated area pattern, there being the compensation side wall 107 adjacent with oxidation barrier layer 105 edges, and described compensation side wall 107 is identical with the effect of described oxidation barrier layer 105, both all have the effect of barrier oxidation, therefore when follow-up formation field oxide 108, described field oxide 108 is owing to being subject to compensating the barrier effect of side wall 107, it will be weakened to oxidation barrier layer 105 edges extension formed " beak " zone, even will can not form " beak " zone.Semiconductor device provided by the present invention, by controlling the width of described compensation side wall 107, can effectively control described field oxide 108 and extend to " beak " regional size that place, oxidation barrier layer 105 edge produces, and then can effectively reduce the area that described field oxide 108 is occupied active area, thereby can produce more effectively tube core in substrate.
Description to semiconductor device and method, semi-conductor device manufacturing method in this specification emphasizes particularly on different fields a little, relevant, mutually reference of similarity.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, in other embodiments realization.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a method, semi-conductor device manufacturing method is characterized in that, comprising:
Substrate is provided, has pad oxide in the described substrate;
Form the oxidation barrier layer with isolated area pattern at described pad oxide;
In the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge;
Have the oxidation barrier layer of isolated area pattern and compensate side wall as mask take described, in the isolated area of described substrate, form field oxide.
2. method according to claim 1 is characterized in that, forms the compensation side wall adjacent with the oxidation barrier layer edge in the isolated area pattern of described oxidation barrier layer with isolated area pattern, specifically comprises:
Form layer of compensation at described oxidation barrier layer with isolated area pattern;
For anti-carving the barrier layer, adopt dry etch process that described layer of compensation is anti-carved with described suprabasil pad oxide, in the isolated area pattern of described oxidation barrier layer with isolated area pattern, form the compensation side wall adjacent with the oxidation barrier layer edge.
3. method according to claim 1 is characterized in that, also comprises:
Remove described oxidation barrier layer and compensation side wall with isolated area pattern.
4. method according to claim 1 is characterized in that, forms the oxidation barrier layer with isolated area pattern at described pad oxide, specifically comprises:
Form oxidation barrier layer at described pad oxide;
Form the photoresist layer with isolated area pattern at described oxidation barrier layer;
As adopting etching technics, mask forms the oxidation barrier layer with isolated area pattern take described photoresist layer with isolated area pattern at described pad oxide;
Remove described photoresist layer with isolated area pattern.
5. each described method is characterized in that according to claim 1～4, and the material of described compensation side wall is silicon nitride.
6. each described method is characterized in that according to claim 1～4, and described oxidation barrier layer is silicon nitride layer.
7. each described method is characterized in that according to claim 1～4, forms field oxide and adopt wet process oxidation technology in the isolated area of described substrate.
8. a semiconductor device is characterized in that, comprising:
Substrate;
Be positioned at described suprabasil pad oxide;
Be positioned at the oxidation barrier layer with isolated area pattern on the described pad oxide;
Be arranged in described have the isolated area pattern of the oxidation barrier layer of isolated area pattern, the compensation side wall adjacent with described oxidation barrier layer edge;
Be positioned at the field oxide of described substrate isolated area.
9. semiconductor device according to claim 8 is characterized in that, the material of described oxidation barrier layer and compensation side wall is silicon nitride.
10. semiconductor device according to claim 8 is characterized in that, the material of described pad oxide and field oxide is silica.
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| CN2011102287248A CN102931125A (en) | 2011-08-10 | 2011-08-10 | Semiconductor device and manufacturing method thereof |
| PCT/CN2012/079555 WO2013020476A1 (en) | 2011-08-10 | 2012-08-02 | Semiconductor device and method for preparing same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016119480A1 (en) * | 2015-01-29 | 2016-08-04 | 无锡华润上华半导体有限公司 | Method for preparing trench isolation structure |
| CN105914178A (en) * | 2016-05-11 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Shallow trench isolation structure manufacturing method |
| CN110943030A (en) * | 2018-09-21 | 2020-03-31 | 上海晶丰明源半导体股份有限公司 | Field oxide layer structure and manufacturing method thereof |
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| US5173444A (en) * | 1990-09-18 | 1992-12-22 | Sharp Kabushiki Kaisha | Method for forming a semiconductor device isolation region |
| US5972777A (en) * | 1997-07-23 | 1999-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming isolation by nitrogen implant to reduce bird's beak |
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| TW468236B (en) * | 1998-09-22 | 2001-12-11 | Nanya Technology Corp | Method for manufacturing an LOCOS isolation region |
| CN101131543A (en) * | 2006-08-23 | 2008-02-27 | 上海华虹Nec电子有限公司 | Manufacturing process method for partial silicon oxidization and isolation |
| CN101924059A (en) * | 2009-06-13 | 2010-12-22 | 无锡华润上华半导体有限公司 | Field insulation manufacturing method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016119480A1 (en) * | 2015-01-29 | 2016-08-04 | 无锡华润上华半导体有限公司 | Method for preparing trench isolation structure |
| US9972525B2 (en) | 2015-01-29 | 2018-05-15 | Csmc Technologies Fab2 Co., Ltd. | Method for preparing trench isolation structure |
| CN105914178A (en) * | 2016-05-11 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Shallow trench isolation structure manufacturing method |
| CN105914178B (en) * | 2016-05-11 | 2019-07-26 | 上海华虹宏力半导体制造有限公司 | The production method of fleet plough groove isolation structure |
| CN110943030A (en) * | 2018-09-21 | 2020-03-31 | 上海晶丰明源半导体股份有限公司 | Field oxide layer structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013020476A1 (en) | 2013-02-14 |
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