CN103107075B - The formation method of metal gates - Google Patents
The formation method of metal gates Download PDFInfo
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- CN103107075B CN103107075B CN201110358290.3A CN201110358290A CN103107075B CN 103107075 B CN103107075 B CN 103107075B CN 201110358290 A CN201110358290 A CN 201110358290A CN 103107075 B CN103107075 B CN 103107075B
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Abstract
A formation method for metal gates, comprising: provide Semiconductor substrate, and described Semiconductor substrate comprises the first transistor district and transistor seconds district; Form polysilicon membrane on the semiconductor substrate, ion implantation is carried out to the polysilicon membrane being positioned at described first crystal area under control; Remove part polysilicon membrane, form alternative gate structure, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously; Utilize tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of ion implantation, form the second groove, and form the second metal gates in described second groove; Removing, by the alternative gate structure in the first crystal area under control of ion implantation, forms the first groove, and form the first metal gates in described first groove.Because tetramethyl ammonium hydroxide solution can optionally etch alternative gate structure, and utilize ion implantation can realize vertical trenched side-wall, make the metal gates of follow-up formation to meet technological requirement.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of metal gates.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in MOS transistor.In order to avoid the metal material of metal gates is on the impact of other structures of transistor, the gate stack structure of described metal gates and high K gate dielectric layer adopts " rear grid (gatelast) " technique to make usually.
Publication number is that the american documentation literature of US2002/0064964A1 discloses a kind of method using " rear grid " technique to form metal gates, comprise: Semiconductor substrate is provided, described Semiconductor substrate be formed with alternative gate structure and be positioned at the interlayer dielectric layer described Semiconductor substrate covering described alternative gate structure; Using described alternative gate structure as stop-layer, chemical mechanical milling tech (CMP) is carried out to described interlayer dielectric layer; Groove is formed after removing described alternative gate structure; In described groove, metal is filled, to form metal gate electrode layer by PVD method; With chemical mechanical milling method abrasive metal gate electrode layer to exposing interlayer dielectric layer, form metal gates.Because metal gates makes after source-drain area has injected again, this makes the quantity of subsequent technique be reduced, and avoids the problem that metal material is unsuitable for carrying out high-temperature process.
At current static random access memory (StaticRandomAccessMemory, SRAM) in memory cell, the grid of a nmos pass transistor is electrically connected with the grid of a PMOS usually, please refer to Fig. 1, for the circuit diagram of the SRAM memory cell of prior art, described SRAM memory cell has four NMOS transistors 11,12,13,14 and two PMOS transistor 15,16, the grid of wherein said nmos pass transistor 11 and the grid electrical connection of PMOS transistor 15, the grid electrical connection of described nmos pass transistor 12 and PMOS transistor 16.In the prior art, the grid electrical connection of the nmos pass transistor in described SRAM memory cell and PMOS transistor needs to form conductive plunger in described gate surface, and utilizes the described conductive plunger grid realizing described nmos pass transistor and PMOS transistor that is connected with metal interconnecting layer to be electrically connected.But along with improving constantly of SRAM integrated level, grid structure is more and more less, conductive plunger is formed also more and more difficult on described grid structure surface, therefore proposed the fabrication of nmos pass transistor and PMOS transistor afterwards in same grid structure, can effectively improve SRAM integrated level, reduce process complexity.
But along with SRAM integrated level is more and more higher, the characteristic size of MOS transistor is also more and more less, the common grid of nmos pass transistor and PMOS transistor also needs to adopt metal gates to reduce the parasitic capacitance of MOS transistor grid, improves device speed.But because nmos pass transistor is different with the work function of PMOS transistor, therefore the materials and process of the metal gates of nmos pass transistor and the metal gates of PMOS transistor is all different, need to be formed respectively, this makes the metal gates of nmos pass transistor and PMOS transistor be difficult to reach technological requirement.
Summary of the invention
The formation method of the metal gates that the metal gates that the problem that the present invention solves is to provide a kind of nmos pass transistor and PMOS transistor links together, makes the final metal gates formed to meet technological requirement.
For solving the problem, technical solution of the present invention provides a kind of formation method of metal gates, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Form polysilicon membrane on the semiconductor substrate, ion implantation is carried out to the polysilicon membrane being positioned at described first crystal area under control;
Remove part polysilicon membrane, form alternative gate structure, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously;
Utilize tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of ion implantation, form the second groove, and form the second metal gates in described second groove;
Removing, by the alternative gate structure in the first crystal area under control of ion implantation, forms the first groove, and form the first metal gates in described first groove.
Optionally, the degree of depth of described ion implantation is equal to or greater than the thickness of described polysilicon membrane.
Optionally, described ion implantation is vertically injected in the polysilicon membrane in first crystal area under control, and the region that described polysilicon membrane intermediate ion is injected is not with vertical with semiconductor substrate surface by the border in the region of ion implantation.
Optionally, the foreign ion of described ion implantation be boron, indium, nitrogen, phosphorus, arsenic, antimony, carbon, fluorine, chlorine, helium, argon wherein one or more.
Optionally, form gate dielectric membrane at described semiconductor substrate surface, form polysilicon membrane on described gate dielectric membrane surface.
Optionally, described gate dielectric membrane is silicon oxide layer or high-K dielectric layer.
Optionally, also comprise, between described gate dielectric membrane and polysilicon membrane, be formed with barrier layer.
Optionally, the material on described barrier layer is TiN, TaN wherein a kind of or both laminated construction.
Optionally, after the alternative gate structure removing described first crystal area under control and transistor seconds district respectively, described barrier layer still covers the surface of the gate dielectric layer of described correspondence.
Optionally, the method for the alternative gate structure in described removing first crystal area under control comprises wet etching or dry etching.
Optionally, the wet etching solution of the alternative gate structure in described removing first crystal area under control is KOH solution.
Optionally, the dry etching of the alternative gate structure in described removing first crystal area under control is the coefficient dry etch process of physics and chemistry mechanism.
Optionally, when described first metal gates and the second metal gates are single coating, the material of described first metal gates and the second metal gates be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
Optionally, when described first metal gates and the second metal gates are multilayer lamination structure, described first metal gates and the second metal gates comprise functional layer and are positioned at the metal gate electrode layer on functional layer surface.
Optionally, described functional layer is barrier layer.
Optionally, described functional layer comprises: be positioned at the described barrier layer on gate dielectric layer surface, be positioned at the supplementary functions layer of described barrier layer surface.
Optionally, the material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
Optionally, the material of described metal gate electrode layer be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
Optionally, described first crystal area under control is PMOS transistor district, and described transistor seconds district is nmos pass transistor district.
Optionally, described first crystal area under control is nmos pass transistor district, and described transistor seconds district is PMOS transistor district.
Compared with prior art, the present invention has the following advantages:
In the forming process of the metal gates of the embodiment of the present invention, ion implantation is carried out to the polysilicon membrane in the first crystal area under control formed on a semiconductor substrate, after utilizing described polysilicon membrane to form alternative gate structure, by tetramethyl ammonium hydroxide solution etching not by the alternative gate structure in the transistor seconds district of ion implantation, because tetramethyl ammonium hydroxide solution can only etch the silicon with fixing crystal orientation, when ion implantation is in the polysilicon membrane in first crystal area under control, the crystal orientation of the alternative gate structure utilizing the polysilicon membrane in described first crystal area under control to be formed destroy by ion implantation, make tetramethyl ammonium hydroxide solution can not etch the alternative gate structure in first crystal area under control, the alternative gate structure in transistor seconds district can only be etched, and utilize ion implantation can realize vertical trenched side-wall easily, described trench fill can be expired by the metal gates of follow-up formation, hole can not be formed bottom metal gates, thus device performance and yield can not be affected.
Further; barrier layer is formed between described polysilicon membrane and gate dielectric membrane; described barrier layer can stop that the ion be injected in polysilicon membrane continues to be injected into gate dielectric membrane surface; and described barrier layer covers described gate dielectric membrane surface; the gate dielectric layer utilizing described gate dielectric membrane to be formed can not be contacted with the etching solution of the plasma of follow-up dry etching or wet etching; avoid described etching solution and plasma to the destruction of gate dielectric layer, further protect gate dielectric layer.
Further, the material on described barrier layer is TiN, TaN wherein a kind of or both laminated construction.Owing to also needing to form TiN, TaN wherein a kind of or both laminated construction in the metal gates of follow-up formation, utilize described TiN, TaN wherein a kind of or both laminated construction can avoid also needing to continue removing barrier layer after removing alternative gate structure as barrier layer, because the technique removing barrier layer also may damage gate dielectric layer, save processing step, avoid gate dielectric layer simultaneously and sustain damage.
Further, when etching the alternative gate structure in the described first crystal area under control of removing, can directly utilize wet etching or select the alternative gate structure of the coefficient dry etch process of physics and chemistry mechanism to described first crystal area under control to etch, do not need to form the step such as photoresist layer, exposure imaging, save processing step, improve process integration.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the SRAM memory cell of prior art;
Fig. 2 is the structural representation of nmos pass transistor and PMOS transistor common grid in the SRAM memory cell of prior art;
Fig. 3 is the schematic flow sheet of the formation method of the metal gates of the embodiment of the present invention;
Fig. 4 to Figure 15 is the structural representation of the forming process of the metal gates of the embodiment of the present invention.
Embodiment
In existing SRAM memory cell, the grid of a nmos pass transistor is electrically connected with the grid of a PMOS usually.In order to improve device integration, and avoid forming conductive plunger on grid structure surface, in layout design, usually a nmos pass transistor and a PMOS transistor are shared same grid structure, specifically please refer to Fig. 2, for the structural representation of nmos pass transistor and PMOS transistor common grid in the SRAM memory cell of prior art, comprising: Semiconductor substrate has nmos pass transistor district 01 and PMOS transistor district 02; Described common grid 21 is across the border in described nmos pass transistor district 01 and PMOS transistor district 02, and a part for described common grid 21 is positioned at nmos pass transistor district 01, and another part of described common grid 21 is positioned at PMOS transistor district 02; In nmos pass transistor district 01, the both sides of described common grid 21 are formed with N-type source/drain region 22; In PMOS transistor district 02, the both sides of described common grid 11 are formed with P type source/drain region 23.
But along with SRAM integrated level is more and more higher, the nmos pass transistor in SRAM and the common grid of PMOS transistor also need to adopt metal gates to reduce the parasitic capacitance of MOS transistor grid, improve device speed.But because nmos pass transistor is different with the work function of PMOS transistor, therefore the materials and process of the metal gates of nmos pass transistor and the metal gates of PMOS transistor is all different, need to be formed respectively.Namely first utilize dry etch process to remove the common grid part in nmos pass transistor district 01, in the groove that etching is formed, form the metal gates being applicable to nmos pass transistor; Then remove the common grid part in PMOS transistor district, in the groove that etching is formed, form the metal gates being applicable to PMOS transistor.But due to the result that dry etching majority is by physical bombardment and chemical etching immixture, and utilize chemical etching the sidewall of described groove and Semiconductor substrate plane can be made not to be vertical because of reasons such as crystal orientation, when the reacting gas of dry etching contains the atom such as carbon, hydrogen, described trenched side-wall also can form polymer, makes the sidewall of groove become inclination.And in order to remove alternative gate electrode completely, usually needing alternative gate electrode over etching, the described over etching also easy sidewall by groove becomes inclination, and can cause damage to gate dielectric layer.When the sidewall of described groove is what tilt, the groove that described nmos pass transistor district 01 is formed and one of them opening of groove that PMOS transistor district 02 is formed are up big and down small, and another opening is up-small and down-big.When described opening is up-small and down-big, utilizes metal sputtering processes to be difficult to channel bottom acute angular areas to fill completely completely, make to produce hole in metal gates, affect the yield of device.
For this reason, inventor is through research, and propose a kind of formation method of metal gates, comprising: provide Semiconductor substrate, described Semiconductor substrate comprises the first transistor district and transistor seconds district; Form polysilicon membrane on the semiconductor substrate, ion implantation is carried out to the polysilicon membrane being positioned at described first crystal area under control; Remove part polysilicon membrane, form alternative gate structure, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously; Utilize tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of ion implantation, form the second groove, and form the second metal gates in described second groove; Removing, by the alternative gate structure in the first crystal area under control of ion implantation, forms the first groove, and form the first metal gates in described first groove.Because tetramethyl ammonium hydroxide solution can only etch the silicon with fixing crystal orientation, when in the polysilicon membrane that ion implantation is corresponding to described first crystal area under control, make the crystal orientation of the alternative gate structure in the first crystal area under control of follow-up formation destroy by ion implantation, tetramethyl ammonium hydroxide solution can not etch the alternative gate structure in first crystal area under control, the alternative gate structure in transistor seconds district can only be etched, and utilize ion implantation can realize vertical trenched side-wall easily, described trench fill can be expired by the metal gates of follow-up formation, hole can not be formed bottom metal gates, thus device performance and yield can not be affected.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Please refer to Fig. 3, be the schematic flow sheet of the formation method of the metal gates of the embodiment of the present invention, specifically comprise:
Step S101, provides Semiconductor substrate, and described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Step S102, forms polysilicon membrane on the semiconductor substrate, carries out ion implantation to the polysilicon membrane being positioned at described first crystal area under control;
Step S103, removes part polysilicon membrane, and form alternative gate structure, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously;
Step S104, utilizes tetramethyl ammonium hydroxide solution to remove not by the alternative gate structure in the transistor seconds district of ion implantation, forms the second groove, and form the second metal gates in described second groove;
Step S105, removes by the alternative gate structure in the first crystal area under control of ion implantation, forms the first groove, and forms the first metal gates in described first groove.
Fig. 4 is the structural representation of overlooking visual angle of the embodiment of the present invention for the formation of the Semiconductor substrate 100 of SRAM memory cell, and Fig. 5 is the cross-sectional view of the Semiconductor substrate 100 along the hatching AA ' direction in Fig. 4.Due to described hatching AA ' cutting is the semiconductor structure being positioned at first crystal area under control I, and therefore Fig. 5 is the cross-sectional view of the Semiconductor substrate 100 of the first transistor.The forming process of described transistor seconds is identical with the forming process of the first transistor, and the cross-section structure of the Semiconductor substrate of described transistor seconds can obtain with reference to figure 4 and Fig. 5 in the lump.
In the lump with reference to figure 4 and Fig. 5, Semiconductor substrate 100 is provided, described Semiconductor substrate comprises the first transistor district I and transistor seconds district II, in described first crystal area under control I, utilize ion implantation technology to form the first well region 110, in described transistor seconds district II, utilize ion implantation technology to form the second well region 120, and form fleet plough groove isolation structure 130 around described first well region 110 and the second well region 120.
Described first crystal area under control I is adjacent with transistor seconds district II, and the second metal gates in the transistor seconds of the first metal gates in the first transistor of the described first crystal area under control I of follow-up formation and transistor seconds district II is connected to each other.In the present embodiment, described first crystal area under control I and transistor seconds district II is that band shape is spaced, and each first crystal area under control I and transistor seconds district II includes several transistors.
In the present embodiment, described first crystal area under control I is PMOS transistor district, and described transistor seconds district II is nmos pass transistor district.In other embodiments, described first crystal area under control I is nmos pass transistor district, and described transistor seconds district II is PMOS transistor district.
Described Semiconductor substrate 100 is silicon substrate, silicon-on-insulator substrate, silicon-Germanium substrate one wherein.In the present embodiment, because the transistor to be formed in described first crystal area under control I is PMOS transistor, the foreign ion that described first well region 110 injects is N-type impurity ion, because the transistor to be formed in described transistor seconds district II is nmos pass transistor, the foreign ion that described second well region 120 injects is p type impurity ion.
Fig. 6 is the formation gate dielectric membrane of the embodiment of the present invention and the structural representation overlooking visual angle of polysilicon membrane, and Fig. 7 is the cross-sectional view of the semiconductor structure along the hatching AA ' direction in Fig. 6.Due to described hatching AA ' cutting is the semiconductor structure being positioned at first crystal area under control I, and therefore Fig. 7 is the cross-sectional view of the first transistor forming process.Except not carrying out ion implantation, the forming process of described transistor seconds is identical with the forming process of the first transistor, and the cross-section structure of described transistor seconds forming process can obtain with reference to figure 6 and Fig. 7 in the lump.
In the lump with reference to figure 6 and Fig. 7, gate dielectric membrane 141 is formed on described Semiconductor substrate 100 surface, polysilicon membrane 151 is formed on described gate dielectric membrane 141 surface, polysilicon membrane 151 surface corresponding at described transistor seconds district II forms photoresist layer 160, carry out ion implantation to described polysilicon membrane 151, the polysilicon membrane 151 making the described first crystal area under control I that do not covered by photoresist layer 160 corresponding carries out ion implantation.Wherein, described gate dielectric membrane 141 is silicon oxide layer or high-K dielectric layer, and in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate dielectric membrane 141 of the embodiment of the present invention is high-K dielectric layer.
In the present embodiment, the region of described ion implantation not only comprises the corresponding region of the alternative gate structure of the first crystal area under control I of follow-up formation, also comprises the region that the first well region is corresponding with part fleet plough groove isolation structure.In other embodiments, the region of described ion implantation only comprises the corresponding region of the alternative gate structure of the first crystal area under control I of follow-up formation.
Described polysilicon membrane 151 in subsequent technique for the formation of alternative gate structure, after described polysilicon membrane 151 is by ion implantation, the ion that the crystal orientation of described polysilicon membrane 151 is injected into destroyed, make later use Tetramethylammonium hydroxide (TMAH) solution can not etch away the destroyed polysilicon in crystal orientation, and the etching polysilicon without ion implantation can fall by described TMAH solution, thus optionally can fall the alternative gate structure in transistor seconds district by wet etching.In order to make the alternative gate structure in first crystal area under control completely can not etch by TMAH solution, the crystal orientation of the polysilicon membrane 151 in described first crystal area under control needs the ion be all injected into destroy, therefore, the degree of depth of the ion of described injection at least equals the thickness of polysilicon membrane 151.In other embodiments, when being formed with barrier layer between described gate dielectric membrane and polysilicon membrane, the degree of depth of the ion of described injection can be a bit larger tham the thickness of polysilicon membrane, to ensure that the ion injected can destroy the crystal orientation of the polysilicon membrane in first crystal area under control completely.
In order to the crystal orientation of polysilicon membrane more effectively can be destroyed, improve the etching selection ratio of the alternative gate structure not injecting ion in subsequent technique and the alternative gate structure being filled with ion, by selecting higher Implantation Energy, injection ion that diameter is larger, the crystal orientation of the polysilicon membrane in first crystal area under control is destroyed more thorough.In embodiments of the present invention, the foreign ion of described ion implantation be boron, indium, nitrogen, phosphorus, arsenic, antimony, carbon, fluorine, chlorine, helium, argon wherein one or more, due to the Doped ions that above-mentioned foreign ion is all conventional in semiconductor technology, can production cost be reduced, improve the versatility of raw material.
In order to avoid the formation acute angular areas, bottom of the groove of follow-up formation, the final metal gates formed is made to there is hole, affect device performance and even may cause component failure, the direction of described ion implantation is vertical with polysilicon membrane surface, the region that described polysilicon membrane intermediate ion is injected is not with vertical with semiconductor substrate surface by the border in the region of ion implantation, and by improving the Implantation Energy of ion, can not change when making the injection direction of described ion in the lattice structure being injected into polysilicon, ensure that the sidewall of groove and the plane orthogonal of Semiconductor substrate of final formation.
In other embodiments, between described gate dielectric membrane and polysilicon membrane, also barrier layer is formed with.Due in order to make the crystal orientation of polysilicon membrane be totally disrupted, foreign ion is injected in the process of polysilicon membrane, the injection degree of depth of described foreign ion is suitable with the thickness of polysilicon membrane, but described foreign ion is still likely injected in gate dielectric membrane, and the ion being easy to be injected into due to the lattice structure of gate dielectric membrane destroyed, the final puncture voltage of gate dielectric layer, the threshold voltage of transistor formed is changed, affects device performance.Therefore between described gate dielectric membrane and polysilicon membrane, barrier layer is formed with; described barrier layer can stop that the ion be injected in polysilicon membrane continues to be injected into gate dielectric membrane surface; and described barrier layer covers described gate dielectric membrane surface; the described gate dielectric layer of follow-up formation can not be contacted with the etching solution of the plasma of follow-up dry etching or wet etching; avoid described etching solution and plasma to the destruction of gate dielectric layer, further protect gate dielectric layer.
In the present embodiment, the material on described barrier layer is TiN, TaN wherein a kind of or both laminated construction.Owing to also needing to be formed TiN, TaN wherein a kind of or both laminated construction in the metal gates of follow-up formation as functional layer, utilize described TiN, TaN wherein a kind of or both laminated construction can avoid also needing to continue removing barrier layer after removing alternative gate structure as barrier layer, because the technique removing barrier layer also may damage gate dielectric layer, save processing step, avoid gate dielectric layer simultaneously and sustain damage.
Fig. 8 be the embodiment of the present invention there is the nmos pass transistor of shared alternative gate structure and the structural representation overlooking visual angle of PMOS transistor, Fig. 9 is the cross-sectional view of the MOS transistor along the hatching AA ' direction in Fig. 8.Due to described hatching AA ' cutting is the semiconductor structure being positioned at first crystal area under control I, and therefore Fig. 9 is the cross-sectional view of the first transistor.The forming process of described transistor seconds is identical with the forming process of the first transistor, and the cross-section structure of described transistor seconds can obtain with reference to figure 8 and Fig. 9 in the lump.
In the lump with reference to figure 6 to Fig. 9, the described gate dielectric membrane 141 of part and polysilicon membrane 151 are etched, gate dielectric layer 140 is formed on described Semiconductor substrate 100 surface, form alternative gate structure 150 on described gate dielectric layer 140 surface, described gate dielectric layer 140 and alternative gate structure 150 are positioned at described first crystal area under control I and transistor seconds district II simultaneously.Around described gate dielectric layer 140, alternative gate structure 150, form side wall (not shown), form the first source/drain region 180, source/drain region 170, second respectively at the first well region 110, second well region 120 of the both sides being positioned at described alternative gate structure 150.
Concrete formation process comprises: form photoresist layer (not shown) on described polysilicon membrane 151 surface, carry out to described photoresist layer the figure that exposure imaging forms alternative gate structure; With the photoresist layer after described exposure for mask, dry etching is carried out to described polysilicon membrane 151, gate dielectric membrane 141, until expose Semiconductor substrate 100, form alternative gate structure 150 and the gate dielectric layer 140 of strip, the gate dielectric layer 140 of described strip and alternative gate structure 150 are positioned at described first crystal area under control I and transistor seconds district II simultaneously; Silicon oxide layer, silicon nitride layer or the laminated construction (not shown) of the two is formed on described Semiconductor substrate 100, alternative gate structure 150 surface, and described silicon oxide layer, silicon nitride layer or the laminated construction of the two are carried out without mask etching, until expose Semiconductor substrate 100, form side wall (not shown) in described alternative gate structure 150, gate dielectric layer 140 sidewall surfaces; Respectively ion implantation is carried out to described first well region 110, second well region 120 of the both sides being positioned at described alternative gate structure 150, forms the first source/drain region 170 and the second source/drain region 180.
The alternative gate structure 150 of described strip and gate dielectric layer 140 be both positioned at first well region 110 surface of first crystal area under control I, be positioned at again second well region 120 surface of transistor seconds district II, the grid of the grid and transistor seconds finally forming the first transistor is electrically connected.Because described the first transistor and transistor seconds share grid structure, the grid structure of the first transistor and transistor seconds is directly electrically connected, do not need to be electrically connected by metal interconnecting layer, can avoid forming conductive plunger on described grid structure surface, reduce technology difficulty and process complexity, improve the integrated level of device.In the present embodiment, transistor in described first crystal area under control I is PMOS transistor, the foreign ion that described first source/drain region is injected is p type impurity ion, transistor in described transistor seconds district II is nmos pass transistor, and the foreign ion that described second source/drain region is injected is N-type impurity ion.
Figure 10 is that the surface of the embodiment of the present invention is formed with the nmos pass transistor of interlayer dielectric layer 190 and the structural representation overlooking visual angle of PMOS transistor, and Figure 11 is the cross-sectional view of the MOS transistor along the hatching AA ' direction in Figure 10.
In the lump with reference to Figure 10 and Figure 11, interlayer dielectric layer 190 is formed in described Semiconductor substrate 100 and alternative gate structure 150 surface, chemico-mechanical polishing is carried out to described interlayer dielectric layer 190, until expose described alternative gate structure 150, make the height of described interlayer dielectric layer 190 equal with the height of alternative gate structure 150.
The material of described interlayer dielectric layer 190 is silica, tetraethoxysilane or low-K dielectric.The technique forming described interlayer dielectric layer 190 is chemical vapour deposition (CVD).
Figure 12 to Figure 15 is the cross-sectional view of the forming process of metal gates along the hatching BB ' direction in Figure 10.
In the lump with reference to Figure 10 and Figure 12, utilize Tetramethylammonium hydroxide (TMAH) solution to remove not by the alternative gate structure 150 of the transistor seconds district II of ion implantation, form the second groove 221.
Due to TMAH solution not metal ion, and utilizing that the etch rate of TMAH solution etches silicon is very fast, etching selection is higher, can not etch silica, silicon nitride, is a kind of ideal solution for wet etching silicon materials.Because polysilicon is shortrange order, the crystal orientation that described TMAH solution also constantly can change along described polysilicon etches, but inventor finds, after the crystal orientation of silicon materials is destroyed, the speed of TMAH solution etches silicon can significantly reduce.When foreign ion is injected in polysilicon membrane, regularly arranged lattice structure in the alternative gate structure utilizing described polysilicon membrane to be formed is destroyed, the crystal orientation of described alternative gate structure is destroyed, TMAH solution can not carry out along the crystal orientation of silicon etching, and the speed ratio that TMAH solution etches is injected with the alternative gate structure of foreign ion etches little one to three order of magnitude of speed of the alternative gate structure of non-implanting impurity ion.In the present embodiment, because the crystal orientation of the alternative gate structure in first crystal area under control is destroyed, the crystal orientation of the alternative gate structure in transistor seconds district is not destroyed, when TMAH solution spraying is immersed in TMAH solution at described alternative gate body structure surface or alternative gate structure, the alternative gate structure in described transistor seconds district can be etched away completely, and the alternative gate structure in first crystal area under control is not almost etched, thus form the second groove 221 in the position of the former alternative gate structure in transistor seconds district.Because the alternative gate structure utilizing described wet-etching technology to remove transistor seconds district does not need to form the step such as photoresist layer, exposure imaging, save processing step, improve process integration.
In the lump with reference to Figure 12 and Figure 13, in described second groove 221, form the second metal gates 222.
Described second metal gates 222 can be single coating or multilayer lamination structure.
When described second metal gates 222 is single coating, the material of described second metal gates 222 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
When described second metal gates 222 is multilayer lamination structure, described second metal gates 222 comprises: to be positioned at bottom the second groove 221 and sidewall functional layer 223, be positioned at the metal gate electrode layer 224 on described functional layer 223 surface, and described functional layer 223 and metal gate electrode layer 224 fill full described second groove 221.
For described second metal gates 222 for multilayer lamination structure, the concrete grammar forming described second metal gates 222 comprises: bottom the alternative gate structure 150 and the second groove 221 of described interlayer dielectric layer 190, first crystal area under control I and sidewall form functional layer and metal gate electrode layer, described functional layer and metal gate electrode layer fill full described second groove 221; Chemico-mechanical polishing is carried out to described functional layer and metal gate electrode layer, until the functional layer on described interlayer dielectric layer 190 surface and metal gate electrode layer are etched away completely, the functional layer 223 and the metal gate electrode layer 224 that are positioned at the second groove 221 form the second metal gates 222.
The material of described functional layer 223 be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the material of described metal gate electrode layer 224 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.Described functional layer 223 not only as the diffusion impervious layer of metal gate electrode layer 224, for the diffusion of the material of barrier metal gate electrode layer 224, can also regulate the work function of grid structure.The work function of the grid structure of described nmos pass transistor and PMOS transistor can be changed by the material and manufacture craft adjusting the functional layer of described nmos pass transistor and PMOS transistor.In the present embodiment, the transistor of described second metal gates 222 correspondence is nmos pass transistor, the technique forming described second metal gates comprises: utilize atom layer deposition process (AtomicLayerDeposition, ALD) TiAlN thin film is formed on described gate dielectric layer 140 surface, atom layer deposition process is utilized to form TaN film on described TiAlN thin film surface, physical gas-phase deposition (PhysicalVaporDeposition is utilized at described TaN film surface, PVD) TiAl film is formed, atom layer deposition process is utilized again to form TiAlN thin film at described TiAl film surface, utilize on described TiAlN thin film surface and form physical gas-phase deposition formation Ti film, physical gas-phase deposition is adopted to form Al metal level at described Ti film surface.Described TiAlN thin film, TaN film, TiAl film, Ti film form functional layer 223, and described Al metal level forms metal gate electrode layer 224.The thickness range of described Al metal level is
In one embodiment, when described functional layer is TiN, during the barrier layer of TaN wherein a kind of or both laminated construction, can directly adopt barrier layer as functional layer, after the alternative gate structure removing described transistor seconds district II, retain barrier layer, using the functional layer of described barrier layer as transistor seconds, directly form metal gate electrode layer at described barrier layer surface, the barrier layer formed in step before directly adopting in described embodiment is as functional layer, do not need extra deposition-etch technique, save processing step, avoid gate dielectric layer to sustain damage simultaneously.
In another embodiment, described functional layer can also be multilayer lamination structure, comprising: be positioned at the barrier layer on gate dielectric layer surface, be positioned at the supplementary functions layer of described barrier layer surface.Described supplementary functions layer can adopt deposition, etching technics is additionally formed, the material of described supplementary functions layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the present embodiment additionally forms supplementary functions layer again at the barrier layer surface formed before, thus the damage that the etching technics before can repairing causes described barrier layer, avoid only adopting barrier layer to regulate to regulate the work function of grid structure the defect that window is too narrow as functional layer.
In the lump with reference to Figure 13 and Figure 14, remove by the alternative gate structure 150 of the first crystal area under control I of ion implantation, form the first groove 211.
The method removing the alternative gate structure 150 of described first crystal area under control I comprises wet etching or dry etching one wherein.In the present embodiment, the technique removing the alternative gate structure 150 of described first crystal area under control I is wet etching, and etching solution is KOH solution.Described KOH solution only can etch polysilicon, and do not affect etch rate because polysilicon whether has ion implantation, final only the alternative gate structure 150 of first crystal area under control I to be removed, to form the first groove 211 in the position of the alternative gate structure being originally formed with first crystal area under control.Owing to utilizing KOH solution only can etch alternative gate structure, do not need to form the step such as photoresist layer, exposure imaging, saved processing step, improve process integration.
In other embodiments, when adopting the alternative gate structure of dry etch process to described first crystal area under control to etch, when selecting the coefficient dry etch process of physics and chemistry mechanism, photoresist mask can not be adopted, directly the alternative gate structure in first crystal area under control is carried out, form the first through hole, scope due to the etching selection ratio of the coefficient dry etching of physics and chemistry mechanism is 5: 1 ~ 100: 1, therefore, when removing the alternative gate structure in described first crystal area under control completely, the interlayer dielectric layer of very little thickness is only had to be etched away, do not affect the performance of the last semiconductor device formed, and the alternative gate structure utilizing described etching technics to remove first crystal area under control does not need to form photoresist layer, the steps such as exposure imaging, save processing step, improve process integration.
In other embodiments, patterned photoresist layer can also be formed on described interlayer dielectric layer, the second metal gates surface, described photoresist layer exposes the alternative gate structure in first crystal area under control, carries out dry etching, form the first groove to the alternative gate structure in described first crystal area under control.
In the lump with reference to Figure 14 and Figure 15, in described first groove 211, form the first metal gates 212.
Described first metal gates 212 can be single coating or multilayer lamination structure.
When described first metal gates 212 is single coating, the material of described first metal gates 212 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
When described first metal gates 212 is multilayer lamination structure, described first metal gates 212 comprises: be positioned at the functional layer 213 of the bottom of the first groove 211 and sidewall, be positioned at the metal gate electrode layer 214 on described functional layer 213 surface, and described functional layer 213 and metal gate electrode layer 214 fill full described first groove 211.
For described first metal gates 212 for multilayer lamination structure, the concrete grammar forming described first metal gates 212 comprises: bottom described interlayer dielectric layer 190, second metal gates 212 and the first groove 211 and sidewall form functional layer and metal gate electrode layer, described functional layer and metal gate electrode layer fill full described first groove 211; Chemico-mechanical polishing is carried out to described functional layer and metal gate electrode layer, until the functional layer on described interlayer dielectric layer 190 surface and metal gate electrode layer are etched away completely, are positioned at the bottom of the first groove 211 and the functional layer 213 of sidewall and metal gate electrode layer 214 and form the first metal gates 212.
The material of described functional layer 213 be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the material of described metal gate electrode layer 214 be Al, Cu, Ag, Au, Pt, Ni wherein one or more.Described functional layer 213 not only as the diffusion impervious layer of metal gate electrode layer 214, for the diffusion of the material of barrier metal gate electrode layer 214, can also regulate the work function of grid structure.The work function of the grid structure of described nmos pass transistor and PMOS transistor can be changed by the material and manufacture craft adjusting the functional layer of described nmos pass transistor and PMOS transistor.In the present embodiment, the transistor of described first metal gates 212 correspondence is PMOS transistor, the technique forming described first metal gates comprises: utilize atom layer deposition process to form TiAlN thin film on described gate dielectric layer 140 surface, atom layer deposition process is utilized to form TaN film on described TiAlN thin film surface, atom layer deposition process is utilized again to form TiAlN thin film at described TaN film surface, atom layer deposition process is utilized again to form TaN film on described TiAlN thin film surface, utilize at described TaN film surface and form physical gas-phase deposition formation Ti film, physical gas-phase deposition is adopted to form Al metal level at described Ti film surface.Described TiAlN thin film, TaN film, TiAl film, Ti film form functional layer 213, and described Al metal level forms metal gate electrode layer 214.The thickness range of described Al metal level is
because functional layer is also conduction, the first metal gates and the second metal gates are electrically connected by functional layer, and need not pass through conductive plunger, metal interconnecting layer electrical connection, effectively can improve SRAM integrated level, reduce process complexity.
In one embodiment, when described functional layer is the barrier layer of TiN, TaN wherein a kind of or both laminated construction, can directly adopt barrier layer as functional layer, after the alternative gate structure removing described first crystal area under control I, retain barrier layer, using the functional layer of described barrier layer as the first transistor, directly form metal gate electrode layer at described barrier layer surface, the barrier layer formed in step before directly adopting in the present embodiment is as functional layer, do not need extra deposition-etch technique, save processing step, avoided gate dielectric layer simultaneously and sustain damage.
In another embodiment, described functional layer can also be multilayer lamination structure, comprising: be positioned at the barrier layer on gate dielectric layer surface, be positioned at the supplementary functions layer of described barrier layer surface.Described supplementary functions layer can adopt deposition, etching technics is additionally formed, the material of described supplementary functions layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more, the present embodiment additionally forms supplementary functions layer again at the barrier layer surface formed before, thus the damage that the etching technics before can repairing causes described barrier layer, avoid only adopting barrier layer to regulate to regulate the work function of grid structure the defect that window is too narrow as functional layer.
Because the sidewall of the first groove of the first metal gates and the second groove of the second metal gates is vertical with Semiconductor substrate plane, utilize atom layer deposition process or metal level deposited by physical vapour deposition (PVD) can fill full first groove and the second groove completely, make not form hole between the first metal gates of final generation and the second metal gates, device performance and the yield of final generation can not be affected.
To sum up, in the forming process of the metal gates of the embodiment of the present invention, ion implantation is carried out to the polysilicon membrane in the first crystal area under control formed on a semiconductor substrate, after utilizing described polysilicon membrane to form alternative gate structure, by tetramethyl ammonium hydroxide solution etching not by the alternative gate structure in the transistor seconds district of ion implantation, because tetramethyl ammonium hydroxide solution can only etch the silicon with fixing crystal orientation, when ion implantation is in the polysilicon membrane in first crystal area under control, the crystal orientation of the alternative gate structure utilizing the polysilicon membrane in described first crystal area under control to be formed destroy by ion implantation, make tetramethyl ammonium hydroxide solution can not etch the alternative gate structure in first crystal area under control, the alternative gate structure in transistor seconds district can only be etched, and utilize ion implantation can realize vertical trenched side-wall easily, described trench fill can be expired by the metal gates of follow-up formation, hole can not be formed bottom metal gates, thus device performance and yield can not be affected.
Further; barrier layer is formed between described polysilicon membrane and gate dielectric membrane; described barrier layer can stop that the ion be injected in polysilicon membrane continues to be injected into gate dielectric membrane surface; and described barrier layer covers described gate dielectric membrane surface; the gate dielectric layer utilizing described gate dielectric membrane to be formed can not be contacted with the etching solution of the plasma of follow-up dry etching or wet etching; avoid described etching solution and plasma to the destruction of gate dielectric layer, further protect gate dielectric layer.
Further, the material on described barrier layer is TiN, TaN wherein a kind of or both laminated construction.Owing to also needing to form TiN, TaN wherein a kind of or both laminated construction in the metal gates of follow-up formation, utilize described TiN, TaN wherein a kind of or both laminated construction can avoid also needing to continue removing barrier layer after removing alternative gate structure as barrier layer, do not need extra deposition-etch technique, save processing step, avoided gate dielectric layer simultaneously and sustain damage.
Further, when etching the alternative gate structure in the described first crystal area under control of removing, can directly utilize wet etching or select the alternative gate structure of the coefficient dry etch process of physics and chemistry mechanism to described first crystal area under control to etch, do not need to form the step such as photoresist layer, exposure imaging, save processing step, improve process integration.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. a formation method for metal gates, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises the first transistor district and transistor seconds district;
Form polysilicon membrane on the semiconductor substrate, ion implantation is carried out to the polysilicon membrane being positioned at described first crystal area under control, make the crystal orientation of the polysilicon membrane in first crystal area under control all be injected into ion destroyed, described ion implantation is vertically injected in the polysilicon membrane in first crystal area under control, and the region that described polysilicon membrane intermediate ion is injected is not with vertical with semiconductor substrate surface by the border in the region of ion implantation;
Remove part polysilicon membrane, form continuous print alternative gate structure, described alternative gate structure is positioned at described first crystal area under control and transistor seconds district simultaneously;
Tetramethyl ammonium hydroxide solution is utilized to remove not by the alternative gate structure in the transistor seconds district of ion implantation, form the second groove, and in described second groove, form the second metal gates, described tetramethyl ammonium hydroxide solution to first crystal area under control by the etch rate comparison transistor seconds district of the alternative gate structure of ion implantation not by little one to three order of magnitude of the etch rate of the alternative gate structure of ion implantation;
Removing, by the alternative gate structure in the first crystal area under control of ion implantation, forms the first groove, and form the first metal gates in described first groove.
2. the formation method of metal gates as claimed in claim 1, it is characterized in that, the degree of depth of described ion implantation is equal to or greater than the thickness of described polysilicon membrane.
3. the formation method of metal gates as claimed in claim 1, is characterized in that, the foreign ion of described ion implantation be boron, indium, nitrogen, phosphorus, arsenic, antimony, carbon, fluorine, chlorine, helium, argon wherein one or more.
4. the formation method of metal gates as claimed in claim 1, is characterized in that, forms gate dielectric membrane at described semiconductor substrate surface, forms polysilicon membrane on described gate dielectric membrane surface.
5. the formation method of metal gates as claimed in claim 4, it is characterized in that, described gate dielectric membrane is silicon oxide layer or high-K dielectric layer.
6. the formation method of metal gates as claimed in claim 4, is characterized in that, also comprise, between described gate dielectric membrane and polysilicon membrane, be formed with barrier layer.
7. the formation method of metal gates as claimed in claim 6, is characterized in that, the material on described barrier layer is TiN, TaN wherein a kind of or both laminated construction.
8. the formation method of metal gates as claimed in claim 6, is characterized in that, after the alternative gate structure removing described first crystal area under control and transistor seconds district respectively, described barrier layer still covers the surface of corresponding described gate dielectric membrane.
9. the formation method of metal gates as claimed in claim 1, is characterized in that, the method for the alternative gate structure in removing first crystal area under control comprises wet etching or dry etching.
10. the formation method of metal gates as claimed in claim 9, it is characterized in that, the wet etching solution of the alternative gate structure in described removing first crystal area under control is KOH solution.
The formation method of 11. metal gates as claimed in claim 9, is characterized in that, the dry etching of the alternative gate structure in described removing first crystal area under control is the coefficient dry etch process of physics and chemistry mechanism.
The formation method of 12. metal gates as claimed in claim 1, it is characterized in that, when described first metal gates and the second metal gates are single coating, the material of described first metal gates and the second metal gates be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
The formation method of 13. metal gates as described in claim 1 or 7, it is characterized in that, when described first metal gates and the second metal gates are multilayer lamination structure, described first metal gates and the second metal gates comprise functional layer and are positioned at the metal gate electrode layer on functional layer surface.
The formation method of 14. metal gates as claimed in claim 13, it is characterized in that, described functional layer is barrier layer.
The formation method of 15. metal gates as claimed in claim 13, it is characterized in that, described functional layer comprises: be positioned at the described barrier layer on gate dielectric membrane surface, be positioned at the supplementary functions layer of described barrier layer surface.
The formation method of 16. metal gates as claimed in claim 13, is characterized in that, the material of described functional layer be Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN wherein one or more.
The formation method of 17. metal gates as claimed in claim 14, is characterized in that, the material of described metal gate electrode layer be Al, Cu, Ag, Au, Pt, Ni wherein one or more.
The formation method of 18. metal gates as claimed in claim 1, it is characterized in that, described first crystal area under control is PMOS transistor district, and described transistor seconds district is nmos pass transistor district.
The formation method of 19. metal gates as claimed in claim 1, it is characterized in that, described first crystal area under control is nmos pass transistor district, and described transistor seconds district is PMOS transistor district.
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| CN101924027A (en) * | 2009-06-12 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Metal gate transistor, integrated circuits, systems, and fabrication methods thereof |
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