CN102437048B - Method and device for improving etching of through holes in double-through-hole etching stop layer crossover region - Google Patents
Method and device for improving etching of through holes in double-through-hole etching stop layer crossover region Download PDFInfo
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- CN102437048B CN102437048B CN201110222089.2A CN201110222089A CN102437048B CN 102437048 B CN102437048 B CN 102437048B CN 201110222089 A CN201110222089 A CN 201110222089A CN 102437048 B CN102437048 B CN 102437048B
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Abstract
The invention discloses a method for improving etching of through holes in a double-through-hole etching stop layer crossover region and a CMOS (complementary metal oxide semiconductor) device provided with a double-through-hole etching stop layer so as to enhance the carrier migration rate. The width of the double-through-hole etching stop layer crossover region is changed to prevent the through holes in the double-through-hole etching stop layer crossover region from incapability of being completely opened. The invention provides a method capable of being perfectly combined with the prior art.
Description
Technical field
The present invention relates to technical field of semiconductor preparation, particularly relate to and a kind ofly improve the method for dual via etch stop-layer crossover region via etch and a kind of device on dual via etch stop-layer crossover region with through hole.
Background technology
Along with the development of semiconductor related manufacturing process and the integrated circuit (IC) chip proportionally trend that reduces of size, stress engineering role in semiconductor technology and performance of semiconductor device is more and more obvious, and stress engineering is widely used in improving on the semiconductor device of transistor carrier mobility.At present, some are just had to be applied on some special chip types, as complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal-Oxide-Semiconductor) device.
Usually, in complicated preparation technology's flow process of cmos device, there is various stress, due to progressively reducing of device size, and finally stay the performance of the stress in device channel region on device and have larger impact.The performance of a lot of stress to device is improved, and different types of stress has different influence to charge carrier (i.e. electronics and the hole) mobility in device.Such as, on cmos device channel direction, tensile stress is useful to NMOS electron mobility, and compression is useful to PMOS hole mobility.
Via etch stop-layer (Contact-Etch-Stop-Layer, i.e. CESL) stress engineering, in via etch stop-layer film deposition process, by adjustment sedimentary condition, adding stress in film inside (can be compression, also can be tensile stress), this stress is transmitted in cmos device raceway groove, can have an impact to the mobility of charge carrier.Such as nmos device (as shown in Figure 1), when depositing via etch stop-layer film, by adjustment sedimentary condition, compression is produced in film inside, this stress is transmitted in nmos device raceway groove, forms tensile stress to raceway groove, because the tensile stress on channel direction contributes to the electron mobility improving nmos device, so the inner via etch stop-layer keeping compression, useful to the electron mobility improving nmos device.
Because the stress in raceway groove can cause different impacts to NMOS and PMOS, such as, on cmos device channel direction, tensile stress is useful to NMOS electron mobility, and compression is useful to PMOS hole mobility.So while utilizing the stress engineering of single via etch stop-layer to improve the performance of a kind of device (such as NMOS), the performance of another kind of device (such as PMOS) always will be sacrificed.In order to improve this negative impact, dual via etch stop layer process can be adopted.The flow process of dual via etch stop layer process is as shown in Fig. 2 a ~ 2d.First layer of silicon dioxide film is deposited; as the first protective film 101 removing via etch stop-layer; then deposit silicon nitride film that one deck can form tensile stress in channels as the first via etch stop-layer 102(as Fig. 2 a); this is improved effect to the electron mobility of nmos device, but has reducing effect to the hole mobility of PMOS device.Then dry method of carving is adopted to remove the silicon nitride film in PMOS device region.Dry quarter can stop (as Fig. 2 b) when the first protective film 101 etching into silicon dioxide.Deposit layer of silicon dioxide protective film afterwards again as the second protective film 201; to protect the silicon nitride film of NMOS area in process at dry quarter afterwards; next be deposition one deck can form compression in channels silicon nitride film as the second via etch stop-layer 202(as Fig. 2 c), this is conducive to the hole mobility improving PMOS device.Finally, dry method of carving is utilized to remove the silicon nitride film (as Fig. 2 d) of NMOS area.In the device architecture of final formation, in NMOS raceway groove, form tensile stress, in PMOS raceway groove, form compression.Dual via etch stop-layer stress engineering, namely can improve the electron mobility in nmos device, can improve again the hole mobility in PMOS device.
In dual via etch stop layer process, bring the problem in follow-up via etch process in the overlap branch of (compression and tensile stress) etching stop layer of two kinds of stress, described by Fig. 3 a ~ 3b.In Fig. 3 a, completed dual via etch stop layer process, follow-up layer insulation medium 4(generally adopts phosphorosilicate glass, i.e. PSG) deposition and chemico-mechanical polishing also complete.Have overlapping above the silicon nitride film of the two kinds of different stress polysilicon on a shallow trench.Next via etch process can be carried out.
As shown in Figure 3 b; for through hole 302; because it is positioned at the crossover region of two kinds of different stress nitride silicon thin films; after carrying out second step via etch process; through hole to be only parked in above crossover region on layer of silicon dioxide protective film; this can cause the 3rd step etching to carve completely and wear a layer silicon nitride film, the first via etch stop-layer 102 namely in Fig. 3 b, causes final through hole 302 to open completely.
Therefore, provide one can improve dual via etch stop-layer crossover region via etch, and the method that the through hole be positioned at above dual via etch stop-layer overlapping region is opened completely is just seemed particularly important.
Summary of the invention
Object of the present invention is etching through hole on the device with dual via etch stop-layer crossover region, and through hole is opened completely, to avoid the problem can not opening through hole completely caused because overlapping region is narrow in prior art.
The present invention discloses a kind of method improving doubled via etching stop layer crossover region via etch, provides and has at least one the first transistor and at least one transistor seconds semiconductor substrate; First protective film, covers on described the first transistor and transistor seconds; First via etch stop-layer, cover on described first protective film, described first via etch stop-layer is positioned at the vertical top of described the first transistor, and described first via etch stop-layer and described transistor seconds in the vertical direction are without overlapping region; Second protective film, covers the upper surface of described first via etch stop-layer and sidewall and the first protective film not by part that described first via etch stop-layer covers; Second via etch stop-layer, covers on described second protective film, it is characterized in that, performs following steps:
Etching removal second via etch stop-layer is positioned at the part above described the first transistor vertical direction, the part that second protective film is positioned at above described the first transistor vertical direction exposes, overlapping at vertical direction of part second via etch stop-layer and part first via etch stop-layer, form the overlapping region of the first via etch stop-layer and the coincidence of the second via etch stop-layer in the vertical direction, described overlapping region is positioned at the vertical top of the shallow trench of described semiconductor substrate, the top of described shallow ditch groove structure is provided with polysilicon, the overlap width of described first via etch stop-layer and the second via etch stop-layer overlapping region is greater than the diameter of the follow-up through hole etched above described overlapping region,
Deposition forms the part of the second protective film exposure described in layer insulation dielectric overlay, the upper surface of described second via etch stop-layer remainder and sidewall;
Layer insulation medium described in chemical-mechanical planarization;
Be positioned at the position above described overlapping region at described layer insulation medium, adopt different Selection radio to etch described layer insulation medium, the second via etch stop-layer, the second protective film, the first via etch stop-layer and the first protective film successively to form the first through hole of a described polysilicon.
Above-mentioned method; wherein; described semiconductor substrate is formed with the first active area or the first polysilicon; described first active area or the first polysilicon and described second via etch stop-layer in the vertical direction zero lap, adopt different Selection radio to etch described layer insulation medium, the second protective film, the first via etch stop-layer and the first protective film successively to form the second through hole that contacts described first active area or the first polysilicon.
Above-mentioned method; wherein; described semiconductor substrate is formed with the second active area or the second polysilicon; described second active area or the second polysilicon and described first via etch stop-layer in the vertical direction zero lap, adopt different Selection radio to etch described layer insulation medium, the second via etch stop-layer, the second protective film and the first protective film successively to form the third through-hole that contacts described second active area or the second polysilicon.
Above-mentioned method, wherein, described first protective film and described second protective film are silicon dioxide.
Above-mentioned method, wherein, described the first transistor is NMOS tube, and described first via etch stop-layer is the silicon nitride film producing tensile stress in NMOS tube raceway groove.
Above-mentioned method, wherein, described transistor seconds is PMOS, and described second via etch stop-layer is the silicon nitride film producing compression in PMOS raceway groove.
Above-mentioned method, wherein, described layer insulation medium is phosphorosilicate glass.
Above-mentioned method, wherein, the etching of described first through hole comprises:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon nitride Selection radio between high level, first etching terminates in the second via etch stop-layer;
Second step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the second via etch stop-layer, etching terminates in the second protective film;
3rd step, adopt the lithographic method of high silicon dioxide/silicon nitride Selection radio to carve and wear the second protective film, etching terminates in the first via etch stop-layer;
4th step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the first via etch stop-layer, etching terminates in the first protective film;
5th step, adopt the lithographic method of high silicon dioxide/silicon Selection radio to carve and wear the first protective film, etching terminates in polysilicon, completes etching process to form the first through hole of contact polysilicon.
Above-mentioned method, wherein, the etching of described second through hole comprises:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon dioxide Selection radio between high level, first etching terminates in the second protective film;
Second step, adopt the lithographic method of high silicon dioxide/silicon nitride Selection radio to carve and wear the second protective film, etching terminates in the first via etch stop-layer;
3rd step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the first via etch stop-layer, etching terminates in the first protective film;
4th step, adopt the lithographic method of high silicon dioxide/silicon Selection radio to carve and wear the first protective film, etching terminates in the first active area or the first polysilicon, completes etching process to form the second through hole of contact first active area or the first polysilicon.
Above-mentioned method, wherein, the etching of described third through-hole comprises:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon nitride Selection radio between high level, etching terminates in the second via etch stop-layer;
Second step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the second via etch stop-layer, etching terminates in the second protective film;
3rd step, adopt the lithographic method of silica/silicon Selection radio to carve and wear the second protective film and the first protective film, etching terminates in the second active area or the second polysilicon, completes etching process to form the third through-hole of contact second active area or the second polysilicon.
According to another aspect of the present invention, also disclose and a kind ofly there is doubled via etching stop layer to improve the cmos device of carrier mobility speed, comprising:
There is at least one the first transistor and at least one transistor seconds semiconductor substrate;
First protective film, covers on described the first transistor and transistor seconds;
First via etch stop-layer, cover on described first protective film, described first via etch stop-layer is positioned at the vertical top of described the first transistor, and described first via etch stop-layer and described transistor seconds in the vertical direction are without overlapping region;
Second protective film, covers the upper surface of described first via etch stop-layer and sidewall and the first protective film not by part that described first via etch stop-layer covers;
Second via etch stop-layer, cover on described second protective film, described second via etch stop-layer is positioned at the vertical top of described transistor seconds, described second via etch stop-layer and described the first transistor in the vertical direction are without overlapping region, described second via etch stop-layer and described first via etch stop-layer in the vertical direction have overlapping region, and described overlapping region is positioned at the top of the shallow trench of described semiconductor substrate;
Layer insulation medium, covers on described second via etch stop-layer and the second protective film;
Wherein, the top of the shallow trench of described semiconductor substrate has polysilicon, and described overlapping region is positioned on described polysilicon;
First through hole; in the vertical direction overlaps with described overlapping region; the diameter of described first through hole is less than the overlap width of described first via etch stop-layer and the second via etch stop-layer overlapping region, and described first through hole runs through described layer insulation medium, the second via etch stop-layer, the second protective film, the first via etch stop-layer is with the first protective film and contact described polysilicon.
Above-mentioned cmos device, wherein, described semiconductor substrate is formed with the first active area or the first polysilicon, described first active area or the first polysilicon and described second via etch stop-layer in the vertical direction zero lap,
Second through hole, runs through described layer insulation medium, the second protective film, the first via etch stop-layer with the first protective film and contacts described first active area or the first polysilicon.
Above-mentioned cmos device, wherein, described semiconductor substrate is formed with the second active area or the second polysilicon, described second active area or the second polysilicon and described first via etch stop-layer in the vertical direction zero lap;
Third through-hole, runs through described layer insulation medium, the second via etch stop-layer, the second protective film with the first protective film and contacts described second active area or the second polysilicon.
Above-mentioned cmos device, wherein, described first protective film and described second protective film are silicon dioxide.
Above-mentioned cmos device, wherein, described the first transistor is NMOS tube, and described first via etch stop-layer is the silicon nitride film producing tensile stress in NMOS tube raceway groove.
Above-mentioned cmos device, wherein, described transistor seconds is PMOS, and described second via etch stop-layer is the silicon nitride film producing compression in PMOS raceway groove.
Above-mentioned cmos device, wherein, described layer insulation medium is phosphorosilicate glass.
The present invention is by widening the overlapping part of the via etch stop-layer of two kinds of stress, then on this basis, respectively the through hole being positioned at crossover region is etched with the through hole being positioned at normal areas, solve in prior art and there is the defect can not opening all through holes in the device of the etching stop layer of two kinds of stress completely.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.In the accompanying drawings, for cheer and bright, section components is exaggerated.
Fig. 1 shows in prior art, a kind of NMOS tube covers via etch stop-layer to produce the schematic diagram of tensile stress in raceway groove;
Fig. 2 a shows in prior art, a kind of cmos device covers via etch stop-layer to produce the schematic diagram of tensile stress in the raceway groove of NMOS tube and PMOS;
Fig. 2 b shows in prior art, in NMOS tube, only cover via etch stop-layer in a kind of cmos device only to produce the schematic diagram of tensile stress in the raceway groove of NMOS tube;
Fig. 2 c shows in prior art, in NMOS tube, only covers via etch stop-layer only to produce tensile stress in NMOS tube in raceway groove in a kind of cmos device, also covers a via etch stop-layer in addition to produce compression in the raceway groove of PMOS;
Fig. 2 d by Fig. 2 c for generation of cover in the via etch stop-layer of compression NMOS tube upper part remove after schematic diagram;
Fig. 3 a illustrates in prior art, is provided with the schematic diagram of polysilicon between shallow trench in the semiconductors and two through hole etching stop layer overlapping region;
Fig. 3 b illustrates the schematic diagram cannot opening overlapping region through hole in the prior art completely;
Fig. 4 a illustrates according to of the present invention, and a kind of shallow trench in the semiconductors has the schematic diagram of wider two through hole etching stop layer overlapping region;
Fig. 4 b illustrates according to of the present invention, at the schematic diagram of non-overlapping region etch through hole;
Fig. 4 c illustrates according to of the present invention, at the schematic diagram of the overlapping region etching through hole widened.
Embodiment
Below in conjunction with the drawings and the specific embodiments, the present invention is further elaborated.Embodiment described herein only for explaining the present invention, the protection range be not intended to limit the present invention.
Composition graphs 2c, shown in figure 4a to Fig. 4 c, a kind of method improving doubled via etching stop layer crossover region via etch disclosed in the present invention, the method is device fabrication for having doubled via etching stop layer overlapping region, as shown in Figure 2 c, described device has at least one the first transistor and at least one transistor seconds semiconductor substrate, preferably, described the first transistor is NMOS, and transistor seconds is PMOS; First protective film 101, covers on described the first transistor and transistor seconds; First via etch stop-layer 102, cover on described first protective film 101, described first via etch stop-layer 102 is positioned at the vertical top of described the first transistor, and described first via etch stop-layer 102 and described transistor seconds in the vertical direction are without overlapping region; Second protective film 201, covers the upper surface of described first via etch stop-layer 102 and sidewall and the first protective film 101 not by part that described first via etch stop-layer 102 covers; Second via etch stop-layer 202, covers on described second protective film 201, in conjunction with reference to figure 4a; Fig. 4 a is exaggerated the structure of shallow trench area; the first transistor on not shown described shallow trench both sides and transistor seconds, the feature of the inventive method is, performs following steps:
Etching removal second via etch stop-layer 202 is arranged in the part above described the first transistor (Fig. 4 a is not shown) vertical direction, the part that second protective film 201 is positioned at above described the first transistor vertical direction exposes, overlapping at vertical direction of part second via etch stop-layer 202 and part first via etch stop-layer 102, form the overlapping region 5 of the first via etch stop-layer 102 and the coincidence of the second via etch stop-layer 202 in the vertical direction, described overlapping region 5 is positioned at the vertical top of the shallow trench of described semiconductor substrate, the top of described shallow ditch groove structure is provided with polysilicon 601, the overlap width of described first via etch stop-layer and the second via etch stop-layer overlapping region 5 is greater than the diameter of the through hole of follow-up etching above described overlapping region 5,
Deposition forms layer insulation medium 4 and covers the described part of the second protective film 201 exposure, the upper surface of described second via etch stop-layer 202 remainder and sidewall;
Layer insulation medium 4 described in chemical-mechanical planarization;
With reference to figure 4c; be positioned at the position above described overlapping region 5 at described layer insulation medium 4, adopt different Selection radio to etch described layer insulation medium 4, second via etch stop-layer 202, second protective film 201, first via etch stop-layer 102 and the first protective film 101 successively to form the first through hole 304 of a described polysilicon 601.
Further; with reference to semiconductor substrate described in figure 4b and Fig. 4 c being formed with the first active area 602 or the first polysilicon (not shown); described first active area 602 or the first polysilicon and described second via etch stop-layer 202 in the vertical direction zero lap, adopt different Selection radio to etch described layer insulation medium 4, second protective film 201, first via etch stop-layer 102 successively with the first protective film 101 to form the second through hole 301 that contacts described first active area 602 or the first polysilicon.This step be applied in there is doubled via etching stop layer device in the method for normal areas except doubled via etching stop layer overlapping region, wherein, described first active area 602 or the first polysilicon are positioned on the first transistor.
In a change case, be different from the first active area 602 or the first polysilicon on the first transistor, described semiconductor substrate is formed with the second active area (not indicating in figure) or the second polysilicon (not indicating in figure), those skilled in the art understand, corresponding first active area 602 or the first polysilicon, described second active area or the second polysilicon are positioned on transistor seconds, described second active area or the second polysilicon and described first via etch stop-layer in the vertical direction zero lap, different Selection radio is adopted to etch described layer insulation medium 4 successively, second via etch stop-layer 202, second protective film and the first protective film are to form the third through-hole that contacts described second active area or the second polysilicon.
In a specific embodiment, the material of described first protective film 101 and described second protective film 201 is silicon dioxide.
In another specific embodiment, described the first transistor is NMOS tube, and described first via etch stop-layer 102 is the silicon nitride film producing tensile stress in NMOS tube raceway groove.
Further, described transistor seconds is PMOS, and described second via etch stop-layer 202 is the silicon nitride film producing compression in PMOS raceway groove.
Further, described layer insulation medium 4 is phosphorosilicate glass.
With reference to figure 4c, below illustrate the etching process of described first through hole 304, comprising:
The first step, dielectric 4 between the lithographic method etch layer adopting dielectric/silicon nitride Selection radio between high level, first etching terminates in the second via etch stop-layer 202;
Second step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the second via etch stop-layer 202, etching terminates in the second protective film 201;
3rd step, adopt the lithographic method of high silicon dioxide/silicon nitride Selection radio to carve and wear the second protective film 201, etching terminates in the first via etch stop-layer 102;
4th step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the first via etch stop-layer 102, etching terminates in the first protective film 101;
5th step, adopt the lithographic method of high silicon dioxide/silicon Selection radio to carve and wear the first protective film 101, etching terminates in polysilicon 601, completes etching process to form the first through hole 304 of contact polysilicon 601.In this step, the diameter of the first through hole 304 is less than the width 5 of described overlapping region.
For the described etching being positioned at the second through hole 301 of the first transistor side, carry out as follows:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon dioxide Selection radio between high level, first etching terminates in the second protective film 201;
Second step, adopt the lithographic method of high silicon dioxide/silicon nitride Selection radio to carve and wear the second protective film 201, etching terminates in the first via etch stop-layer 102;
3rd step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the first via etch stop-layer 102, etching terminates in the first protective film 101;
4th step, adopt the lithographic method of high silicon dioxide/silicon Selection radio to carve and wear the first protective film 101, etching terminates in the first active area or the first polysilicon, completes etching process to form the second through hole 301 of contact first active area or the first polysilicon.Because the second through hole 301 is common through holes, it does not contact with described overlapping region 5.
For the described etching being positioned at the third through-hole of transistor seconds side, carry out as follows:
The first step, dielectric 4 between the lithographic method etch layer adopting dielectric/silicon nitride Selection radio between high level, etching terminates in the second via etch stop-layer 202;
Second step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the second via etch stop-layer 202, etching terminates in the second protective film 201;
Wherein, second protective film 201 is the silicon dioxide that material is identical with the first protective film 101; therefore can etch the second protective film 201 and the first protective film 101 simultaneously; perform the 3rd step; adopt the lithographic method of silica/silicon Selection radio to carve and wear the second protective film and the first protective film; etching terminates in the second active area or the second polysilicon, completes etching process to form the third through-hole of contact second active area or the second polysilicon.Structure and second through hole of described third through-hole are similar, and those skilled in the art can make third through-hole in conjunction with the second through hole 301, therefore not shown in the accompanying drawings.
According to another aspect of the present invention, also disclose and a kind ofly there is doubled via etching stop layer to improve the cmos device of carrier mobility speed, comprising:
There is at least one the first transistor and at least one transistor seconds semiconductor substrate; With reference to figure 4c, in figure, be exaggerated shallow trench area, therefore not shown the first transistor and transistor seconds, these are prior art, are not technical characteristics of the present invention, the restriction of the accompanying drawing size of consideration, therefore do not show in same accompanying drawing, can understand by composition graphs 2d;
First protective film 101, covers on described the first transistor and transistor seconds;
First via etch stop-layer 102, cover on described first protective film 101, described first via etch stop-layer 102 is positioned at the vertical top of described the first transistor, and described first via etch stop-layer 102 and described transistor seconds in the vertical direction are without overlapping region;
Second protective film 201, covers the upper surface of described first via etch stop-layer 102 and sidewall and the first protective film 101 not by part that described first via etch stop-layer covers;
With reference to figure 4b and Fig. 4 c, second via etch stop-layer 202, cover on described second protective film 201, described second via etch stop-layer 202 is positioned at the vertical top of described transistor seconds, described second via etch stop-layer 202 and described the first transistor in the vertical direction are without overlapping region, described second via etch stop-layer 202 and described first via etch stop-layer 102 in the vertical direction have overlapping region 5, and described overlapping region 5 is positioned at the top of the shallow trench of described semiconductor substrate;
Layer insulation medium 4, covers on described second via etch stop-layer 202 and the second protective film 201;
Wherein, the top of the shallow trench of described semiconductor substrate has polysilicon 601, and described overlapping region 5 is positioned on described polysilicon 601;
First through hole 304; in the vertical direction overlaps with described overlapping region 5; the diameter of described first through hole 304 is less than the overlap width of described first via etch stop-layer 102 and the second via etch stop-layer 202 overlapping region 5, and described first through hole 304 runs through described layer insulation medium 4, second via etch stop-layer 202, second protective film 201, first via etch stop-layer 102 with the first protective film 101 and contacts described polysilicon 601.
Preferably, described semiconductor substrate is formed with the first active area 602 or the first polysilicon (not indicating in the accompanying drawings), described first active area 601 or the first polysilicon and described second via etch stop-layer 202 in the vertical direction zero lap;
Second through hole 301, runs through described layer insulation medium 4, second protective film 201, first via etch stop-layer 102 with the first protective film 101 and contacts described first active area 602 or the first polysilicon.
Further, described semiconductor substrate is formed with the second active area (not in the accompanying drawings indicate) or the second polysilicon (not indicating in the accompanying drawings), described second active area or the second polysilicon and described first via etch stop-layer in the vertical direction zero lap;
Third through-hole (not in the accompanying drawings indicate), runs through described layer insulation medium 4, second via etch stop-layer 202, second protective film 201 with the first protective film 101 and contacts described second active area or the second polysilicon.
In a specific embodiment, described first protective film 101 and described second protective film 201 are silicon dioxide.
In another preference, described the first transistor is NMOS tube, and described first via etch stop-layer 102 is the silicon nitride film producing tensile stress in NMOS tube raceway groove.
Further, described transistor seconds is PMOS, and described second via etch stop-layer 202 is the silicon nitride film producing compression in PMOS raceway groove.
Preferably, described layer insulation medium 4 is phosphorosilicate glass.
What above-mentioned explanation was detailed illustrates the etching method for forming through hole of doubled via etching stop layer overlapping configuration and has the device of this structure, those skilled in the art understand, the first transistor also can be PMOS, correspondingly, transistor seconds is NMOS tube, described first via etch stop-layer is for generation of device channel internal pressure stress, and described second via etch stop-layer is for generation of tensile stress in device channel, and such change does not affect enforcement of the present invention.
It should be appreciated by those skilled in the art that those skilled in the art can realize described change case in conjunction with prior art and above-described embodiment, such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (12)
1. improve a method for doubled via etching stop layer crossover region via etch, provide and there is at least one the first transistor and at least one transistor seconds semiconductor substrate; First protective film, covers on described the first transistor and transistor seconds; First via etch stop-layer, cover on described first protective film, described first via etch stop-layer is positioned at the vertical top of described the first transistor, and described first via etch stop-layer and described transistor seconds in the vertical direction are without overlapping region; Second protective film, covers the upper surface of described first via etch stop-layer and sidewall and the first protective film not by part that described first via etch stop-layer covers; Second via etch stop-layer, covers on described second protective film, it is characterized in that, performs following steps:
Etching removal second via etch stop-layer is positioned at the part above described the first transistor vertical direction, the part that second protective film is positioned at above described the first transistor vertical direction exposes, part second via etch stop-layer and part first via etch stop-layer overlapping at vertical direction, form the overlapping region of the first via etch stop-layer and the coincidence of the second via etch stop-layer in the vertical direction, described overlapping region is positioned at the vertical top of the shallow trench of described semiconductor substrate, the top of described shallow trench is provided with polysilicon, the overlap width of described first via etch stop-layer and the second via etch stop-layer overlapping region is greater than the diameter of the follow-up through hole etched above described overlapping region,
Deposition forms the part of the second protective film exposure described in layer insulation dielectric overlay, the upper surface of described second via etch stop-layer remainder and sidewall;
Layer insulation medium described in chemical-mechanical planarization;
Be positioned at the position above described overlapping region at described layer insulation medium, adopt different Selection radio to etch described layer insulation medium, the second via etch stop-layer, the second protective film, the first via etch stop-layer and the first protective film successively;
Wherein, described semiconductor substrate is formed with the first active area or the first polysilicon, described first active area or the first polysilicon and described second via etch stop-layer in the vertical direction zero lap, adopt different Selection radio to etch described layer insulation medium, the second protective film, the first via etch stop-layer and the first protective film successively to form the second through hole that contacts described first active area or the first polysilicon;
Described first protective film and described second protective film are silicon dioxide, and described first via etch stop-layer and described second via etch stop-layer are silicon nitride;
The etching of described first through hole comprises:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon nitride Selection radio between high level, first etching terminates in the second via etch stop-layer;
Second step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the second via etch stop-layer, etching terminates in the second protective film;
3rd step, adopt the lithographic method of high silicon dioxide/silicon nitride Selection radio to carve and wear the second protective film, etching terminates in the first via etch stop-layer;
4th step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the first via etch stop-layer, etching terminates in the first protective film;
5th step, adopt the lithographic method of high silicon dioxide/silicon Selection radio to carve and wear the first protective film, etching terminates in polysilicon, completes etching process to form the first through hole of contact polysilicon;
The etching of described second through hole comprises:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon dioxide Selection radio between high level, first etching terminates in the second protective film;
Second step, adopt the lithographic method of high silicon dioxide/silicon nitride Selection radio to carve and wear the second protective film, etching terminates in the first via etch stop-layer;
3rd step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the first via etch stop-layer, etching terminates in the first protective film;
4th step, adopt the lithographic method of high silicon dioxide/silicon Selection radio to carve and wear the first protective film, etching terminates in the first active area or the first polysilicon, completes etching process to form the second through hole of contact first active area or the first polysilicon.
2. method according to claim 1; it is characterized in that; described semiconductor substrate is formed with the second active area or the second polysilicon; described second active area or the second polysilicon and described first via etch stop-layer in the vertical direction zero lap, adopt different Selection radio to etch described layer insulation medium, the second via etch stop-layer, the second protective film and the first protective film successively to form the third through-hole that contacts described second active area or the second polysilicon.
3. method according to claim 2, is characterized in that, described the first transistor is NMOS tube, and described first via etch stop-layer is the silicon nitride film producing tensile stress in NMOS tube raceway groove.
4. method according to claim 3, is characterized in that, described transistor seconds is PMOS, and described second via etch stop-layer is the silicon nitride film producing compression in PMOS raceway groove.
5. method according to claim 4, is characterized in that, described layer insulation medium is phosphorosilicate glass.
6. method according to claim 2, is characterized in that, the etching of described third through-hole comprises:
The first step, dielectric between the lithographic method etch layer adopting dielectric/silicon nitride Selection radio between high level, etching terminates in the second via etch stop-layer;
Second step, adopt the lithographic method of high silicon nitride/silicon dioxide Selection radio to carve and wear the second via etch stop-layer, etching terminates in the second protective film;
3rd step, adopt the lithographic method of silica/silicon Selection radio to carve and wear the second protective film and the first protective film, etching terminates in the second active area or the second polysilicon, completes etching process to form the third through-hole of contact second active area or the second polysilicon.
7. there is doubled via etching stop layer to improve a cmos device for carrier mobility speed, comprising:
There is the semiconductor substrate of at least one the first transistor and at least one transistor seconds;
First protective film, covers on described the first transistor and transistor seconds;
First via etch stop-layer, cover on described first protective film, described first via etch stop-layer is positioned at the vertical top of described the first transistor, and described first via etch stop-layer and described transistor seconds in the vertical direction are without overlapping region;
Second protective film, covers the upper surface of described first via etch stop-layer and sidewall and the first protective film not by part that described first via etch stop-layer covers;
Second via etch stop-layer, cover on described second protective film, described second via etch stop-layer is positioned at the vertical top of described transistor seconds, described second via etch stop-layer and described the first transistor in the vertical direction are without overlapping region, described second via etch stop-layer and described first via etch stop-layer in the vertical direction have overlapping region, and described overlapping region is positioned at the top of the shallow trench of described semiconductor substrate;
Layer insulation medium, covers on described second via etch stop-layer and the second protective film;
It is characterized in that, the top of the shallow trench of described semiconductor substrate has polysilicon, and described overlapping region is positioned on described polysilicon;
First through hole, in the vertical direction overlaps with described overlapping region, the diameter of described first through hole is less than the overlap width of described first via etch stop-layer and the second via etch stop-layer overlapping region, and described first through hole runs through described layer insulation medium, the second via etch stop-layer, the second protective film, the first via etch stop-layer is with the first protective film and contact described polysilicon;
Wherein, described semiconductor substrate is formed with the first active area or the first polysilicon, described first active area or the first polysilicon and described second via etch stop-layer in the vertical direction zero lap;
Second through hole, runs through described layer insulation medium, the second protective film, the first via etch stop-layer with the first protective film and contacts described first active area or the first polysilicon.
8. cmos device according to claim 7, is characterized in that, described semiconductor substrate is formed with the second active area or the second polysilicon, described second active area or the second polysilicon and described first via etch stop-layer in the vertical direction zero lap;
Third through-hole, runs through described layer insulation medium, the second via etch stop-layer, the second protective film with the first protective film and contacts described second active area or the second polysilicon.
9. the cmos device according to claim 7 or 8, is characterized in that, described first protective film and described second protective film are silicon dioxide.
10. the cmos device according to claim 7 or 8, is characterized in that, described the first transistor is NMOS tube, and described first via etch stop-layer is the silicon nitride film producing tensile stress in NMOS tube raceway groove.
11. cmos devices according to claim 7 or 8, it is characterized in that, described transistor seconds is PMOS, and described second via etch stop-layer is the silicon nitride film producing compression in PMOS raceway groove.
12. cmos devices according to claim 7, is characterized in that, described layer insulation medium is phosphorosilicate glass.
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