CN101752408A - Structure of metal silicide buried layer and forming method thereof - Google Patents
Structure of metal silicide buried layer and forming method thereof Download PDFInfo
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- CN101752408A CN101752408A CN 200910201268 CN200910201268A CN101752408A CN 101752408 A CN101752408 A CN 101752408A CN 200910201268 CN200910201268 CN 200910201268 CN 200910201268 A CN200910201268 A CN 200910201268A CN 101752408 A CN101752408 A CN 101752408A
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- metal silicide
- layer
- silicide
- buried
- buried layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention belongs to the technical field of microelectronics and particularly discloses a structure of a metal silicide buried layer and a forming method thereof. The buried structure comprises at least one semiconductor substrate and a metal silicide buried layer which is arranged inside the semiconductor substrate. The metal silicide buried layer can be used as a source electrode or a drain electrode of the buried layer of a vertical channel transistor or be used for forming interconnection between devices, and is particularly suitable for forming interconnection between arrays of vertical channel devices. The metal silicide buried layer is formed by adopting self-aligned process, the method is simple, and the performance of a semiconductor chip can be enhanced.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of buried structure of semiconductor device, particularly a kind of structure of metal silicide buried layer the invention still further relates to the formation method of this kind metal silicide buried layer structure.
Background technology
In recent years, be that the microelectric technique of core has obtained development rapidly with the silicon integrated circuit, the development of integrated circuit (IC) chip is progressively dwindled in proportion, follows Moore's Law basically, and promptly the integrated level of semiconductor chip is with per speed increment of doubling in 18 months.Now, the research of integrated circuit has entered SOC (system on a chip) (SOC) epoch with application.The integrated level and the frequency of operation of single-chip are more and more higher, and integrated level has reached every chip the more than one hundred million transistor of the order of magnitude, and is improving constantly, and this has just caused the characteristic size of device constantly to reduce.Along with size of semiconductor device is more and more littler, the channel length of MOS transistor is also in continuous shortening, when the channel length of MOS transistor becomes very in short-term, short-channel effect all is common in all standard metal oxide semiconductor field effect transistors (MOSFET), and it makes, and transistorized leakage current rises, threshold voltage reduces.
Integrated circuit (IC)-components technology of today has been in the stage to 30 nanometer transition.Along with dwindling of grid length and channel length, the grid of metal-oxide-semiconductor to the control of raceway groove also worse and worse, thereby cause that leakage current rises rapidly between source-drain electrode, various short-channel effects are also more serious.Below 30 nanometers, be necessary to use new device architecture to improve the control of grid to raceway groove, to obtain less leakage current, reduce chip power-consumption.For addressing these problems, three-dimensional device architecture has become the focus of research, can improve the control of grid to raceway groove as FinFET and ring gate device, compares traditional two-dimensional plane type device architecture and has better miniature ability.But three-dimensional device architecture can not fundamentally solve channel length and dwindle along with device area and reduce and associated other problem.
For this reason, vertically channel transistor has been carried, and vertically channel transistor can increase channel length when not increasing the horizontal direction device area, so it can fundamentally solve the various short-channel effects that produce along with the miniature of device.But the vertical complicated process of preparation of channel transistor also has interconnected etc. between the formation of a lot of critical processes such as buried layer type electrode and separation and the device to need to break through.
Summary of the invention
The objective of the invention is to propose a kind of buried structure of semiconductor device, this buried structure can form by simple technical process, and this buried structure not only can be used as the buried regions source electrode of vertical channel transistor or the electrode of drain electrode, can also be used to forming interconnected between the device.
The structure of the metal silicide buried layer that the present invention proposes comprises that at least one Semiconductor substrate and is placed on the metal silicide buried layer of this Semiconductor substrate inside.Described Semiconductor substrate is monocrystalline silicon, polysilicon or silicon-on-insulator (SOI).Described metal silicide is titanium silicide, cobalt silicide, nickle silicide or platinum silicide, or several mixture among them.Described metal silicide buried layer can be to be interrupted discontinuous buried regions in the horizontal direction, also can be the continuous uninterrupted buried regions, when it is that it can be used as the buried regions source electrode of vertical channel transistor or the electrode of drain electrode when being interrupted discontinuous buried regions; When it was the continuous uninterrupted buried regions, it can be used for forming interconnected between the device, was particularly suitable for being used for forming interconnected between the vertical channel device array.
The present invention also provides a kind of formation method of metal silicide buried layer structure, and this method comprises the following steps:
A semiconductor integrated circuit substrate is provided;
Deposit one deck dielectric on described substrate;
Dielectric and substrate are carried out etching form one or more hatch frames; Form one deck etching barrier layer;
Etching barrier layer is carried out etching to expose the silicon area that is used to form silicide;
Deposit layer of metal layer and annealing, make it with described silicon area in silicon form metal silicide;
Remove metal remained.
Wherein, described dielectric is SiO
2, Si
3N
4The perhaps insulating material that mixes mutually between them; Described etching barrier layer is by SiO
2, Si
3N
4Perhaps the insulating material that mixes mutually between them constitutes; Described metal level is titanium, cobalt, nickel, platinum or the mixture between them.Metal silicide can be expanded to all directions when forming, and just can connect into a continuous uninterrupted metal silicide buried layer so in the horizontal direction, can be used for forming interconnected between the vertical channel transistor; If metal silicide is when expansion, the metal silicide of each window does not couple together and forms the discontinuous buried regions of interruption, then can be used as the buried regions source electrode of vertical channel transistor or the electrode of drain electrode.
Buried structure provided by the invention, it is simple to form technology, and this buried structure not only can be used as the buried regions source electrode of vertical channel transistor or the electrode of drain electrode, can also be used to forming interconnected between the device.
The present invention also provides a kind of integrated circuit (IC) chip, comprises an above-mentioned metal silicide buried layer structure on this chip at least.
Description of drawings
Fig. 1 is the sectional view behind deposit dielectric and photoresist layer on the substrate in example of the present invention.
Fig. 2 is continue the sectional view that behind Fig. 1 photoresist layer, dielectric and substrate is carried out after etching forms hatch frame.
Fig. 3 is for removing remaining photoresist layer and forming one deck etching barrier layer behind Fig. 2, then described etching barrier layer is carried out sectional view after the etching.
Fig. 4 is the sectional view after forming the layer of metal layer behind Fig. 3.
Fig. 5 is continue the sectional view that utilizes behind Fig. 4 after annealing technology forms the discontinuous metal silicide layer of interruption.
Fig. 6 is continue the sectional view that utilizes behind Fig. 4 after annealing technology forms the continuous uninterrupted metal silicide layer.
Embodiment
Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, amplified the thickness in layer and zone, shown in size do not represent actual size.Although these figure are not the actual size that reflects device of entirely accurate, their zones that still has been complete reflection and form mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.
Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term substrate can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.
As Fig. 1, a semiconductor integrated circuit substrate 100 is provided, form film 101 and film 102 then.Substrate 100 is monocrystalline silicon, polysilicon or silicon-on-insulator (SOI).Film 101 is a dielectric, can be SiO
2, Si
3N
4The perhaps insulating material that mixes mutually between them.Film 102 is a photoresist layer.
As Fig. 2, film 102, film 101 and substrate 100 are carried out anisotropic etching form opening 201,202,203 and 204.
Remove remaining film 102, deposit forms thin film 103 then, thereby and film 103 is carried out anisotropic etching exposes the silicon area that is used to form silicide in open bottom, as Fig. 3.
What deserves to be explained is, in above-mentioned opening forming process, after film 101 etchings are finished, also can remove film 102 earlier, in substrate, form opening 201,202,203 and 204 thereby utilize film 101 substrate 100 to be carried out anisotropic etching then as hard mask layer.
As Fig. 4, deposit forms layer of metal layer 104, and metal level 104 is titanium, cobalt, nickel or platinum, or several mixture among them.
Utilize annealing technology to form metal silicide, remove remaining metal then.During annealing, metal and pasc reaction form metal silicide, and metal and insulating barrier do not react or faint reaction only takes place.When the width of the thinner thickness of the metal silicide that forms or the silicon between the opening was big, metal silicide formed in the horizontal direction and is interrupted discontinuous metal silicide layer, shown in the 105a among Fig. 5,105b, 105c and 105d; The width of the silicon when the thickness of the metal silicide that forms between the thicker or opening hour, metal silicide forms the continuous uninterrupted metal silicide layer in the horizontal direction, shown in 106 among Fig. 6.In order more easily to form the continuous uninterrupted metal silicide layer, also can be in etching of after open bottom is exposed silicon area, carrying out isotropically shown in Figure 3 to silicon, thus further dwindle the width of the silicon that comes out between the opening.
When the metal silicide layer that forms was discontinuous for being interrupted, it can be used as the buried regions source electrode of vertical channel transistor or the electrode of drain electrode; When the metal silicide layer that forms be continuously uninterruptedly the time, it can be used for forming interconnected between the device, is particularly suitable for being used for forming interconnected between the vertical channel device array.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.
Claims (10)
1. a metal silicide buried layer structure is characterized in that, this buried structure comprises that at least one Semiconductor substrate and is placed on the metal silicide buried layer of this Semiconductor substrate inside.
2. structure according to claim 1 is characterized in that, described Semiconductor substrate is monocrystalline silicon, polysilicon or silicon-on-insulator.
3. structure according to claim 1 is characterized in that described metal silicide is titanium silicide, cobalt silicide, nickle silicide or platinum silicide, or several mixture among them.
4. structure according to claim 1 is characterized in that, described metal silicide buried layer is to be interrupted discontinuous buried regions in the horizontal direction, or the continuous uninterrupted buried regions.
5. the formation method of a metal silicide buried layer is characterized in that, this method comprises the following steps:
A semiconductor integrated circuit substrate is provided;
Deposit one deck dielectric on described substrate;
Dielectric and substrate are carried out etching form one or more hatch frames;
Form one deck etching barrier layer;
Etching barrier layer is carried out etching to expose the silicon area that is used to form metal silicide;
Deposit layer of metal layer and annealing, make it with described silicon area in silicon form metal silicide;
Remove metal remained.
6. method according to claim 5 is characterized in that, described dielectric is SiO
2, Si
3N
4The perhaps insulating material that mixes mutually between them.
7. method according to claim 5 is characterized in that described etching barrier layer is by SiO
2, Si
3N
4Perhaps the insulating material that mixes mutually between them constitutes.
8. method according to claim 5 is characterized in that described metal level is titanium, cobalt, nickel or platinum, or several mixture among them.
9. method according to claim 5 is characterized in that, metal silicide is expanded to all directions when forming, and connects into a continuous uninterrupted metal silicide layer in the horizontal direction; Perhaps form one in the horizontal direction and be interrupted discontinuous metal silicide layer.
10. an integrated circuit (IC) chip is characterized in that, has at least on this chip to contain metal silicide buried layer structure as claimed in claim 1 in the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910201268 CN101752408A (en) | 2009-12-17 | 2009-12-17 | Structure of metal silicide buried layer and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910201268 CN101752408A (en) | 2009-12-17 | 2009-12-17 | Structure of metal silicide buried layer and forming method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101752408A true CN101752408A (en) | 2010-06-23 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014089825A1 (en) * | 2012-12-14 | 2014-06-19 | 复旦大学 | Semiconductor device and manufacturing method thereof |
| WO2014089814A1 (en) * | 2012-12-14 | 2014-06-19 | 复旦大学 | Semiconductor device and manufacturing method thereof |
-
2009
- 2009-12-17 CN CN 200910201268 patent/CN101752408A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014089825A1 (en) * | 2012-12-14 | 2014-06-19 | 复旦大学 | Semiconductor device and manufacturing method thereof |
| WO2014089814A1 (en) * | 2012-12-14 | 2014-06-19 | 复旦大学 | Semiconductor device and manufacturing method thereof |
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Application publication date: 20100623 |