CN1299364C - A CMOS integrated circuit and method for making same - Google Patents
A CMOS integrated circuit and method for making same Download PDFInfo
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- CN1299364C CN1299364C CNB031377432A CN03137743A CN1299364C CN 1299364 C CN1299364 C CN 1299364C CN B031377432 A CNB031377432 A CN B031377432A CN 03137743 A CN03137743 A CN 03137743A CN 1299364 C CN1299364 C CN 1299364C
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Abstract
The present invention discloses a CMOS integrated circuit, and has the purpose of providing the technique of the CMOS integrated circuit which can increase the density of the integrated circuit and enhance the performance of the integrated circuit under the condition of the same device size. The CMOS circuit provided by the present invention comprises a semiconductor device body including an nMOS field effect transistor and a pMOS field effect transistor, wherein a pMOS device is positioned on an nMOS device, the pMOS device and the nMOS device share the same grid electrode, the pMOS device is in a self-aligned double-grid structure or a self-aligned annular grid structure, and channel regions of the pMOS device and the nMOS device are mutually self-aligned. The present invention also provides two preparation methods of the CMOS integrated circuit. The present invention provides a new technical approach for increasing the density of the integrated circuit and enhancing the performance of the integrated circuit.
Description
Technical field
The present invention relates to a kind of complementary mos integrated circuit structure and preparation method thereof in the semiconductor integrated circuit manufacturing technology field.
Background technology
Complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal Oxide Semiconductor) integrated circuit technique is the mainstream technology of current very lagre scale integrated circuit (VLSIC).Constantly increasing current densities and improving circuit performance is its technological development direction always.Usually, the raising of the increase of cmos circuit density and performance realizes by constantly dwindling the MOS size of devices.The characteristic size of MOS device has entered inferior 0.1 micron at present, and under this yardstick, the various basic restrictions with reality begin to occur, and the ability of dwindling that causes device size is near its limit.Cmos circuit always is made of nMOS and pMOS field-effect transistor.In routine techniques, nMOS transistor and pMOS transistor are plane distribution, take area separately respectively, thereby are unfavorable for the raising of current densities.
The innovation and creation content
The purpose of this invention is to provide a kind of complementary metal oxide semiconductors (CMOS) (CMOS) circuit structure that under the identity unit size, can increase integrated circuit density and improve performance of integrated circuits.
Complementary mos integrated circuit provided by the present invention comprises as the nMOS (N raceway groove (N Channel) MOS) that drives with as the semiconductor device body of pMOS (P raceway groove (P Channel) MOS) field-effect transistor of load; Described pMOS device is positioned on the described nMOS device and both sides share same gate electrode; Described pMOS device is autoregistration double grid or gate-all-around structure; Thick and the channel region of the source-drain area of described pMOS device is thin; The mutual autoregistration of channel region of described pMOS device and described nMOS device.
Described pMOS device is a SOI MOS field-effect transistor, and is double grid or ring grid SOI MOS field-effect transistor.
Second purpose of the present invention provides a kind of method for preparing above-mentioned complementary mos integrated circuit.
A kind of method for preparing complementary mos device may further comprise the steps:
1) on a silicon chip substrate, forms shallow trench isolation region; Form silicon dioxide, silicon and silicon dioxide trilamellar membrane again; Described trilamellar membrane is carried out photoetching and etching simultaneously, and formed figure will be determined the channel region length and the gate length of pMOS device and nMOS device;
2) the trilamellar membrane avris after described etching forms side wall, and the source-drain area to described nMOS device carries out oxidation and ion implantation doping then, forms the source region and the drain region of nMOS device, and the channel region of pMOS device is subjected to side wall protection not oxidized;
3) in the perforate of the drain region of described nMOS device, this hole links to each other the drain region of described nMOS device and pMOS device, remove described side wall then, the deposit polysilicon also injects doping, form the source-drain area of pMOS, remove polysilicon on the described silicon dioxide layer, carry out photoetching and etching again with CMP, form the source-drain area of described pMOS device, and erode described silicon dioxide layer; Make gate medium and gate electrode then, obtain described complementary metal oxide semiconductor.
The method that forms silicon dioxide, silicon and silicon dioxide trilamellar membrane in the described step 1) has two kinds, and a kind of is consecutive deposition silicon dioxide, amorphous silicon and silicon dioxide trilamellar membrane on described silicon chip substrate.The step of deposit silicon dioxide, amorphous silicon and silicon dioxide is on silicon chip substrate, consecutive deposition layer of silicon dioxide film and one deck amorphous silicon film on described silicon chip substrate, and described amorphous silicon film carried out crystallization treatment again, the film of deposit layer of silicon dioxide again on described amorphous silicon film then; Described two-layer silicon dioxide film up and down is a sacrifice layer, will be replaced to form the ring grid by polysilicon; The recrystallization method of described amorphous silicon is the laser annealing method.The another kind of method that forms silicon dioxide, silicon and silicon dioxide trilamellar membrane is growth one thermal oxide layer on a soi wafer, then described body silicon chip and described soi wafer is carried out thermal bonding; Erode the silicon substrate of described soi wafer and appear buried silicon dioxide layer, obtain silicon dioxide, silicon fiml and silicon dioxide trilamellar membrane.
In this method, described shallow slot supplement is oxygen-doped polysilicon; Described side wall is a silicon nitride, is returned to carve by LPCVD deposit and anisotropy to form; The thickness of the silicon nitride of described deposit is the 200-300 dust; Described step 2) injecting the ion that mixes in is arsenic ion, and the ion that mixes in the described step 3) is the boron ion; When described gate medium was silicon dioxide, described gate electrode was in-situ doped polysilicon; When described gate medium was the high-k material, described gate electrode was metal or metal silicide.
Stacked CMOS integrated circuit of the present invention, its notable attribute are that the pMOS device is positioned on the nMOS device, thereby occupied area no longer.Another notable attribute is to the invention provides self aligned technology of preparing, and this self-aligned technology makes this stacked CMOS technology and conventional planar CMOS technology have the dwindled ability that is equal to.This self-aligned technology is by at first forming self aligned sacrificial gate, going to replace sacrificial gate with real grid then and realize.
In addition, stacked cmos circuit of the present invention has following advantage:
(1) available nMOS technology realizes the CMOS integrated circuit, so the complexity that circuit is made reduces, and the ghost effect that causes of many conventional cmos technology, no longer exists as self-locking effect.
(2) because the pMOS device is double grid or multiple-grid SOI device, so it has stronger short-channel effect to suppress ability.And in the CMOS of routine technology, the pMOS device is compared with the nMOS device, under equal conditions, always presents worse short-channel effect.Therefore, this stacked cmos circuit is compared with the conventional cmos circuit, and itself has stronger dwindled ability device.
(3) in the conventional cmos circuit, be the balanced balanced current driving force, the area that the pMOS device takies usually is the twice of nMOS device, and in stacked cmos circuit, the pMOS device is double grid or multi-gate structure, satisfies the requirement of current drives balance naturally.Therefore, compare, only need 1/3 area with the conventional cmos circuit.
(4) because the pMOS device is the SOI device, so total parasitic capacitance is compared little with the body silicon CMOS circuit of routine.
(5) the pMOS device links to each other with the nMOS device is vertical, so line is apart from shortening.
The present invention provides a kind of new technological approaches for the performance that increases current densities and raising circuit.
Description of drawings
Fig. 1 is the vertical section structure schematic diagram of the stacked cmos circuit of autoregistration
Fig. 2 A-F is preparation method's schematic diagram of the stacked cmos circuit of autoregistration
Fig. 3 A-B is preparation method's schematic diagram of the stacked cmos circuit of autoregistration
Embodiment
Embodiment 1, the stacked cmos circuit of autoregistration
As shown in Figure 1, the stacked cmos device of autoregistration of the present invention comprises nMOS field-effect transistor and the position pMOS field-effect transistor thereon that is positioned at silicon substrate 1; Described pMOS device and nMOS device are shared same heavily doped polygate electrodes 3; The mutual autoregistration of channel region of described pMOS device and nMOS device; The nMOS device comprises heavily doped silicon source region 7, heavily doped silicon drain region 8, silicon dioxide gate dielectric layer 12 and oxygen-doped polysilicon shallow trench isolation region 2; The pMOS device comprises the silicon dioxide isolation side walls layer 13 of heavily doped polysilicon source region 10 and heavily doped polysilicon drain region 11, silicon dioxide gate dielectric layer 12 ', gate electrode, not or lightly doped silicon fiml channel region 4 and be surrounded on the heavily doped polysilicon double grid electrode 3 and 5 of this channel region; The drain region of nMOS device and pMOS device communicates by contact hole 9; The source region of nMOS device and pMOS device is isolated by silicon dioxide layer 6.
1) shown in Fig. 2 A, photoetching and etching form shallow slot on silicon substrate 1, and the oxygen-doped polysilicon of deposit is filled.Polish the surface with CMP then and form shallow trench isolation region 2.
2) shown in Fig. 2 B, consecutive deposition silicon dioxide 3 ' and amorphous silicon film 4, and amorphous silicon film is carried out laser recrystallization handle.And then deposit layer of silicon dioxide 5 '.Then carry out photoetching and etching.Formed figure will be determined the channel region length and the gate length of pMOS device and nMOS device, and make the up and down mutual autoregistration of doping of channel region and source-drain area.
3) shown in Fig. 2 C, LPCVD method deposit skim silicon nitride also returns and carves formation raceway groove oxidation protection side wall 21.After heat is grown a silicon dioxide separator 6, carry out arsenic ion and inject the source region 7 and the drain region 8 of mixing with formation nMOS device.Form the leakage/drain contact hole 9 of nMOS device and pMOS device at the drain region of nMOS device etching silicon dioxide.
4) shown in Fig. 2 D, erode raceway groove oxidation protection side wall 21 after, deposit one polysilicon layer also carries out boron ion implantation doping.Polish the surface with CMP then.Upper end silicon dioxide 5 ' serves as CMP from stopping layer.
5) shown in Fig. 2 E, photoetching and etching form the source region 10 and the drain region 11 of pMOS device, and bottom sacrificial silicon dioxide 3 ' is appeared, and erode all sacrificial silicon dioxide 3 ' and 5 ' with BOE then.
6) shown in Fig. 2 F, heat growth gate oxide 12 and side wall oxide layer 13.
7) the in-situ doped polysilicon of deposit, and polish the top with CMP.Photoetching and etching form top gate electrode 3 and bottom gate electrode 5 then.
8) subsequently routinely technology obtain complementary metal oxide semiconductor shown in Figure 1.
Embodiment 3, the stacked cmos circuit of preparation autoregistration
1) as shown in Figure 3A, initial silicon substrate 1 is a soi wafer for one silicon chip, another initial silicon substrate 1 '.Photoetching and etching form shallow slot on the body silicon chip, and the oxygen-doped polysilicon of deposit is filled.Polish the surface with CMP then and form shallow trench isolation region 2.Growth one thermal silicon dioxide 3 on soi wafer ", and carry out thermal bonding with the silicon substrate 1 that forms shallow slot.
2) shown in Fig. 3 B, behind the bonding, the substrate silicon 1 ' that erodes this soi wafer is exposed buried oxidation layer 5 ".Then to buried oxidation layer 5 ", amorphous silicon film 4 and silicon dioxide 3 " carry out photoetching and etching.Formed figure will be determined the channel region length and the gate length of pMOS device and nMOS device, and make the up and down mutual autoregistration of doping of channel region and source-drain area.
Among follow-up each step and the embodiment 2 the 3rd) go on foot the 8th) go on foot identical.
Claims (10)
1, a kind of complementary mos integrated circuit, the semiconductor device body that comprises nMOS field-effect transistor and pMOS field-effect transistor, it is characterized in that: described pMOS device is positioned on the described nMOS device, and both sides share same gate electrode; Described pMOS device is double grid or gate-all-around structure; The mutual autoregistration of channel region of described pMOS device and described nMOS device; Thick and the channel region of the source-drain area of described pMOS device is thin.
2, device according to claim 1 is characterized in that: described pMOS device is an autoregistration SOI MOS field-effect transistor.
3, device according to claim 1 and 2 is characterized in that: described pMOS device is double grid or multiple-grid SOI MOS field-effect transistor.
4, a kind of method for preparing the described complementary mos device of claim 1 may further comprise the steps:
1) on a silicon chip substrate, forms shallow trench isolation region; Form silicon dioxide, silicon and silicon dioxide trilamellar membrane again; Described trilamellar membrane is carried out photoetching and etching simultaneously, and formed figure will be determined the channel region length and the gate length of pMOS device and nMOS device;
2) the trilamellar membrane avris after described etching forms side wall, and the source-drain area to described nMOS device carries out oxidation and ion implantation doping then, forms the source region and the drain region of nMOS device, and the channel region of pMOS device is subjected to side wall protection not oxidized;
3) in the perforate of the drain region of described nMOS device, this hole links to each other the drain region of described nMOS device and pMOS device, remove described side wall then, the deposit polysilicon also injects doping, form the source-drain area of pMOS, remove polysilicon on the described silicon dioxide layer, carry out photoetching and etching again with CMP, form the source-drain area of described pMOS device, and erode described silicon dioxide layer; Make gate medium and gate electrode then, obtain described complementary metal oxide semiconductor.
5, method according to claim 4 is characterized in that: the method for the formation silicon dioxide in the described step 1), silicon and silicon dioxide trilamellar membrane is deposit silicon dioxide, amorphous silicon and a silicon dioxide trilamellar membrane on described silicon chip substrate.
6, method according to claim 5, it is characterized in that: the step of deposit silicon dioxide, amorphous silicon and silicon dioxide is on silicon chip substrate, consecutive deposition layer of silicon dioxide film and one deck amorphous silicon film on described silicon chip substrate, and described amorphous silicon film carried out crystallization treatment again, the film of deposit layer of silicon dioxide again on described amorphous silicon film then; Described two-layer silicon dioxide film up and down is a sacrifice layer, will be replaced to form the ring grid by polysilicon; The recrystallization method of described amorphous silicon is the laser annealing method.
7, method according to claim 4, it is characterized in that: the method for the formation silicon dioxide in the described step 1), silicon and silicon dioxide trilamellar membrane is growth one thermal oxide layer on a soi wafer, then described body silicon chip and described soi wafer is carried out thermal bonding; Erode the silicon substrate of described soi wafer and appear buried silicon dioxide layer, obtain silicon dioxide, silicon fiml and silicon dioxide trilamellar membrane.
8, according to claim 4 or 5 or 6 or 7 described methods, it is characterized in that: described shallow slot supplement is oxygen-doped polysilicon; Described side wall is a silicon nitride, is returned to carve by LPCVD deposit and anisotropy to form.
9, method according to claim 8 is characterized in that: the thickness of described silicon nitride is the 200-300 dust.
10, according to claim 4 or 5 or 6 or 7 described methods, it is characterized in that: injecting the ion that mixes described step 2) is arsenic ion, and the ion that mixes in the described step 3) is the boron ion; When described gate medium was silicon dioxide, described gate electrode was in-situ doped polysilicon; When described gate medium was the high-k material, described gate electrode was metal or metal silicide.
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CN100428476C (en) * | 2006-07-10 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | CMOS part |
CN108110049A (en) * | 2017-12-18 | 2018-06-01 | 深圳市晶特智造科技有限公司 | Metal oxide semiconductor transistor and preparation method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4555721A (en) * | 1981-05-19 | 1985-11-26 | International Business Machines Corporation | Structure of stacked, complementary MOS field effect transistor circuits |
US4651186A (en) * | 1981-11-18 | 1987-03-17 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with improved withstand voltage characteristic |
US4997785A (en) * | 1989-09-05 | 1991-03-05 | Motorola, Inc. | Shared gate CMOS transistor |
US5241193A (en) * | 1992-05-19 | 1993-08-31 | Motorola, Inc. | Semiconductor device having a thin-film transistor and process |
JPH08321617A (en) * | 1995-05-25 | 1996-12-03 | Citizen Watch Co Ltd | Method of manufacturing semiconductor device |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4555721A (en) * | 1981-05-19 | 1985-11-26 | International Business Machines Corporation | Structure of stacked, complementary MOS field effect transistor circuits |
US4651186A (en) * | 1981-11-18 | 1987-03-17 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with improved withstand voltage characteristic |
US4997785A (en) * | 1989-09-05 | 1991-03-05 | Motorola, Inc. | Shared gate CMOS transistor |
US5241193A (en) * | 1992-05-19 | 1993-08-31 | Motorola, Inc. | Semiconductor device having a thin-film transistor and process |
JPH08321617A (en) * | 1995-05-25 | 1996-12-03 | Citizen Watch Co Ltd | Method of manufacturing semiconductor device |
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