CN101930927B

CN101930927B - Self-aligned U-shaped groove manufacturing method

Info

Publication number: CN101930927B
Application number: CN2010102608244A
Authority: CN
Inventors: 王鹏飞; 臧松干; 张卫
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2010-08-24
Filing date: 2010-08-24
Publication date: 2012-01-18
Anticipated expiration: 2030-08-24
Also published as: CN101930927A

Abstract

The invention belongs to the technical field of semiconductor chips, and particularly relates to a self-aligned U-shaped groove manufacturing method. The method comprises the following steps of: etching a semiconductor substrate by using silicon oxide as a mask; forming a silicon nitride side wall; growing silicon oxide on the exposed semiconductor substrate; peeling the silicon nitride side wall; and etching a U-shaped groove of an exposed semiconductor substrate forming device by using the silicon oxide as the mask. The method for manufacturing the U-shaped groove by adopting self-aligned technology can reduce the alignment mismatch of graphs and improve the manufacturing yield of a product, and is particularly suitable for manufacturing a tunneling transistor.

Description

A kind of self aligned U type groove manufacturing method

Technical field

The invention belongs to technology of semiconductor chips field, be specifically related to a kind of manufacturing approach of U type groove, particularly a kind of manufacturing approach of self aligned U type groove.

Background technology

Along with the development of semiconductor integrated circuit technology, the size of Metal-oxide-silicon field-effect transistor (MOSFET) is more and more littler, and the transistor density that unit matrix lists is also increasingly high, and thing followed short-channel effect is also obvious further.How to reduce the power consumption of portable equipment, become a research focus of technical field of semiconductors.IC-components technology node of today has been in below 45 nanometers, and the leakage current between the MOSFET source-drain electrode rises rapidly along with dwindling of channel length.Particularly drop to 30 nanometers when following when channel length, be necessary to use novel device obtaining less leakage current, thereby reduce chip power-consumption.

Adopt U type channel structure can prolong transistorized channel length effectively, thereby can suppress the generation of leakage current in the transistor.The manufacturing approach of U type groove is in traditional device: at first, oxidation forms one deck silicon oxide film 102 on the Semiconductor substrate that provides 101, on silicon oxide film 102, forms the photoresist 103 that one deck has figure then, and is as shown in Figure 1.Next, the U type groove 104 of etching oxidation silicon thin film 102 and Semiconductor substrate 101 formation devices, as shown in Figure 2.

As stated, when making the U-shaped groove of device, can form the photoresist that one deck has figure, will introduce the alignment mismatch (misalignment) of figure like this, thereby the fine ratio of product of product is reduced.

Summary of the invention

To the problems referred to above, the objective of the invention is to propose a kind of manufacturing approach of new U type groove, when using this manufacturing technology to make the U type groove of device, can reduce the alignment mismatch of figure, improve the fine ratio of product of product.

The manufacturing approach of the self aligned U type groove that the present invention proposes, concrete steps comprise:

A Semiconductor substrate is provided;

Oxidation forms the ground floor silicon oxide film on said Semiconductor substrate;

On said ground floor silicon oxide film, form the photoresist that one deck has figure;

The said ground floor silicon oxide film of etching exposes Semiconductor substrate;

Continue the Semiconductor substrate that etching exposes;

Divest remaining photoresist;

Form the ground floor silicon nitride film;

The said silicon nitride film of etching forms side wall;

Carry out oxidation, oxidation forms silicon oxide film on the Semiconductor substrate that exposes, and silicon nitride does not have oxidized simultaneously;

Etching is removed described silicon nitride side wall;

With ground floor and second layer silicon oxide film is mask, the Semiconductor substrate of using isotropic lithographic technique etching to expose;

The Semiconductor substrate that continues the anisotropic lithographic technique etching exposure of use forms the U type groove of device.

Further, described ground floor, second layer silicon oxide film thickness range are the 20-100 nanometer.Described ground floor silicon nitride film thickness range is the 10-200 nanometer.

The manufacturing technology of U type groove provided by the present invention; Use the silicon nitride side wall as forming the hard mask that sacrifice layer is formed self-aligned etched features U type groove; Thereby adopt self aligned technology to make the U-shaped groove of device. can reduce the alignment mismatch of figure like this; Thereby improve the fine ratio of product of product, be specially adapted to the manufacturing of IC chips such as tunneling transistor.

Description of drawings

Fig. 1 to Fig. 2 is the manufacturing process flow diagram of the U type groove of prior art.

Fig. 3 to Fig. 5 is the manufacturing process flow diagram of U type groove provided by the invention.

Fig. 6 to Figure 12 makes the manufacturing process flow diagram of the tunneling transistor of U type raceway groove for the manufacturing technology that adopts U type groove provided by the invention.

Embodiment

Below with reference to accompanying drawings illustrative embodiments of the present invention is elaborated.In the drawings, the thickness in layer and zone has been amplified in explanation for ease, shown in size do not represent actual size.Reference diagram is the sketch map of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.Simultaneously in the following description, employed term substrate is appreciated that to be to comprise the just Semiconductor substrate in processes, possibly comprise other prepared thin layer above that.

At first; Through dry-oxygen oxidation technology; Growth one deck silicon oxide film 202 on the Semiconductor substrate that provides 201 then forms the photoresist 203 that one deck has figure on silicon oxide film 202, etching oxidation silicon thin film 202 forms structure as shown in Figure 3 with Semiconductor substrate 201 successively then.

Next, divest photoresist 203, deposit one deck silicon nitride film then, and this silicon nitride film returned to carve form silicon nitride side wall 204, continue oxidation growth silicon oxide films 205 on the substrate that exposes 201 surfaces then, as shown in Figure 4.This step oxidizing process in since silicon nitride film be difficult to oxidized, so the silicon oxide film on the silicon nitride side wall 204 is extremely thin.

After silicon oxide film 205 forms; Divest silicon nitride side wall 204; Be mask with silicon oxide film 202 with silicon oxide film 205 then; The Semiconductor substrate that adopts isotropic lithographic technique etching to expose, the Semiconductor substrate of then using anisotropic lithographic technique continuation etching to expose forms the U type groove 206 of device, and is as shown in Figure 5.

The manufacturing technology of U type groove provided by the present invention can be widely used in the manufacturing of IC chips such as tunneling transistor, below described be to adopt the manufacturing technology of U type groove provided by the invention to make a kind of embodiment manufacturing process flow of tunneling transistor of U type raceway groove.

Although these figure are not the actual size of this device of reflection of entirely accurate, the reflection that they are complete mutual alignment between zone and the various piece, particularly between the part about and neighbouring relations.

At first, on the silicon substrate 301 of the light dope p type that provides, carry out n type ion and inject formation n type doped region 302, the depth ratio of n type doped region 302 is as being 200 nanometers, and is as shown in Figure 6.

After n type doped region 302 forms; Through on silicon substrate 301, the grow silicon oxide film 304 of one deck 100 nanometers of dry-oxygen oxidation technology; Then on silicon oxide film 304, form the photoresist 305 that one deck has figure; The etching oxidation silicon thin film 304 then, and continue the silicon substrate 301 that etching exposes, and this moment, the etching depth of silicon substrate should be not less than 200 nanometers so that part n type doped region 302 is etched away in the vertical; As shown in Figure 7, rest parts n type doped region will be used as a drain region 303 of device.

Next, divest photoresist 305, follow deposit one deck 100 nanometer left and right sides silicon nitride materials, and this silicon nitride layer is returned formation at quarter silicon nitride side wall 306, form the p type source region 307 of device then through ion implantation technology or diffusion technology, as shown in Figure 8.

Next, utilize the superficial growth silicon oxide film 308 in dry-oxygen oxidation technology p type source region 307 in silicon substrate, and n type source region is expanded in the vertical through diffusion technology, as shown in Figure 9.

Next; Divest silicon nitride side wall 306; And be mask with silicon oxide film 308 with silicon oxide film 304; The silicon substrate that uses isotropic lithographic technique etching to expose then uses anisotropic lithographic technique to continue the silicon substrate formation device U type groove 309 that etching exposes, and is shown in figure 10.

After U type groove 309 forms; At surface deposition one deck high dielectric constant 310 of groove, such as being hafnium oxide, deposit layer of metal again 311; Such as TaN; Deposit one deck photoresist again forms the grid of device then through mask, exposure, etching, the structure behind the stripping photoresist is shown in figure 11.The thickness of high dielectric constant 310 is several nanometers to tens nanometer, and purpose is to reduce leakage current.

At last, deposit one insulating barrier 312, insulating material can or be a silicon nitride for silica; Deposit one deck photoresist again; Method through mask, exposure, etching forms through hole then, divests deposit layer of metal again behind the photoresist, can or be tungsten for aluminium; Etching sheet metal forms source electrode 313 and drain electrode 314 then, and the final device architecture that forms is shown in figure 12.

As stated, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the instantiation described in the specification.

Claims

1. self aligned U type trench fabrication methods, concrete steps comprise:

A Semiconductor substrate is provided;

The said ground floor silicon oxide film of etched portions exposes Semiconductor substrate, and continues the Semiconductor substrate that etching exposes;

Deposit one deck silicon nitride film;

The described silicon nitride film of etching forms the silicon nitride side wall, and exposes Semiconductor substrate;

Carry out oxidation, oxidation forms second layer silicon oxide film on the Semiconductor substrate of described exposure;

Remove described silicon nitride side wall;

Be mask with ground floor and second layer silicon oxide film then, the Semiconductor substrate that adopts isotropic lithographic technique etching to expose, the Semiconductor substrate of then using anisotropic lithographic technique continuation etching to expose forms the U type groove of device.

2. manufacturing approach according to claim 1 is characterized in that, described ground floor, second layer silica, and thickness is respectively the 20-100 nanometer.

3. manufacturing approach according to claim 1 is characterized in that, described silicon nitride film thickness is the 10-200 nanometer.