CN101866858B - Manufacture method of sinking channel type PNPN field effect transistor - Google Patents
Manufacture method of sinking channel type PNPN field effect transistor Download PDFInfo
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- CN101866858B CN101866858B CN2010101863734A CN201010186373A CN101866858B CN 101866858 B CN101866858 B CN 101866858B CN 2010101863734 A CN2010101863734 A CN 2010101863734A CN 201010186373 A CN201010186373 A CN 201010186373A CN 101866858 B CN101866858 B CN 101866858B
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Abstract
The invention discloses a manufacture method of a sinking channel type PNPN field effect transistor. A sinking channel structure ensures that the transistor increases the drive current while reducing the leakage current, i.e. improves the performance of a chip while reducing the power consumption of the chip. By adopting the manufacture method of the sinking channel type PNPN field effect transistor, the process is simple, the efficiency is high, and the production cost is lowered.
Description
Technical field
The invention belongs to the semiconductor device processing technology field, be specifically related to a kind of manufacturing approach of PNPN field-effect transistor, particularly a kind of manufacturing approach of recessed channel-type PNPN field effect transistor.
Background technology
Along with the continuous development of microelectronic integrated circuit technology, the size of Metal-oxide-silicon field-effect transistor (MOSFET) is more and more littler, and the transistor density that unit matrix lists is also increasingly high.IC-components technology node of today has been in below 45 nanometers, and the leakage current between the MOSFET source-drain electrode rises rapidly along with dwindling of channel length.Particularly drop to 30 nanometers when following when channel length, be necessary to use novel device to obtain less leakage current, thereby reduce chip power-consumption.Grid-control PNPN field-effect transistor is the very little transistor of a kind of leakage current, can reduce chip power-consumption greatly, and still, along with the PNPN field-effect transistor narrows down to below 20 nanometers, its leakage current is also dwindling and rise with device.The drive current of common PNPN field-effect transistor is than the low 2-3 one magnitude of MOSFET, therefore needs to improve its drive current, with the performance of the chip that improves integrated PNPN field-effect transistor.
In order to address the above problem, recessed channel-type PNPN field effect transistor has been proposed now, its structure is as shown in Figure 1, and it is the sectional view along this device channel length direction.Described recessed channel-type PNPN field effect transistor comprises a gate stack district, a source region, a drain region and a substrate zone.The gate stack district is made up of gate oxide 104, hafnium layer 105 and conductor layer 106, the polycrystalline silicon material that conductor layer 106 adopts metal gate material or mixes.The side wall 107 in gate stack district is that dielectric is such as being Si
3N
4Material, side wall 107 is isolated grid region conductor layer 106 and other conductor layer of this device.The doping type in source region 103 is opposite with the doping type of drain region 101 and depletion region 102 usually, and identical with the doping type of substrate 100c.The substrate surface of pressing close to gate oxide 104 between source region 103 and the drain region 101 is the current channel zone of device.Substrate 100a and 100b are the silicon layer that contains first kind or second kind impurity of light dope, or are insulating oxide.Insulating barrier 108 is this transistorized passivation layer, and it separates other device of said transistor AND gate.Conductor 109,110 and 111 is metallic aluminium or tungsten, is respectively the electrode of this transistor source, grid and drain electrode.The channel structure of umbilicate type makes transistor when reducing leakage current, increase drive current, just when reducing chip power-consumption, has improved the performance of chip.In the manufacturing process of present recessed channel-type PNPN field effect transistor; Normally form the drain region through ion implantation technology earlier; And form source region and depletion region through continuous twice epitaxy technique or twice ion injection technology; With recessed channel-type PNPN field effect transistor that Fig. 1 is provided is example, and its detailed step is:
A Semiconductor substrate that comprises substrate 100a, 100b and 100c is provided;
Inject the drain region 101 that forms second kind of doping type through ion;
Deposit forms one deck hard mask, such as being silicon nitride film;
Said hard mask and Semiconductor substrate are carried out the recess channel zone that etching forms device;
Divest remaining hard mask;
Form one deck gate oxide 104, one deck hafnium layer 105 and one deck conductive layer 106 successively;
Etching forms the grid structure of device;
Deposit forms first kind of insulation film;
Said ground floor insulation film, hafnium layer and Semiconductor substrate are carried out etching to be formed for forming the zone in source region;
Extension forms the depletion region 102 with second kind of doping type;
Extension forms the source region 103 with first kind of doping type;
First kind of insulation film of etching forms grid curb wall 107;
Etching hafnium layer 105 exposes drain region 101;
Deposit forms second kind of insulation film 108, and it is carried out etching formation through-hole structure;
First kind of conductive film of deposit forms source electrode 109, gate electrode 110 and drain electrode 111.
As stated; In the manufacturing process of traditional recessed channel-type PNPN field effect transistor; Be earlier to form the drain region through ion implantation technology, etching forms the recess channel zone then, forms source region and depletion region in the non-drain region side in recess channel zone through twice epitaxy technique or twice ion injection technology again; Its complex technical process, production cost is high.
Summary of the invention
The objective of the invention is to propose a kind of manufacturing approach of recessed channel-type PNPN field effect transistor, this method can be simplified the manufacturing process of traditional recessed channel-type PNPN field effect transistor, reduces production costs.
The manufacturing approach of the recessed channel-type PNPN field effect transistor that the present invention proposes, concrete steps are following:
Semiconductor substrate with first kind of doping type is provided;
Carry out ion and inject, in the Semiconductor substrate that provides, form the zone of first kind of doping type;
Deposit forms first kind of insulation film;
The semiconductor substrate region of carrying out follow-up doping is exposed in the zone of the said first kind of insulation film of etched portions and first kind of doping type;
Deposit forms second kind of insulation mask, and said second kind of insulation film carried out etching formation side wall;
In the Semiconductor substrate that provides, form the zone of second kind of doping type through diffusion technology;
Deposit forms the third insulation mask;
Etching forms the recess channel zone of device;
Form the 4th kind of insulation film;
Deposit forms first kind of conductive film;
Etching forms the grid structure of device;
Divest remaining first kind, the third insulation film;
Deposit forms the 5th kind of insulation film, and said the 5th kind of insulation film carried out etching formation through-hole structure;
Second kind of conductive film of deposit forms electrode.
Said Semiconductor substrate is the silicon (SOI) on monocrystalline silicon, polysilicon or the insulator.Said first kind, second kind, the third, the 5th kind of insulation film can be silicon dioxide, silicon nitride or the insulating material for mixing mutually between them.Said the 4th kind of insulation film can be SiO
2, HfO
2, HfSiO, HfSiON, SiON or Al
2O
3, perhaps be several kinds mixture among them.Said first kind of conductive film can be TiN, TaN, RuO
2, Ru or WSi alloy, perhaps be the polycrystalline silicon material of its doping.Described second kind of conductive film is metallic aluminium, tungsten or is other metallic conduction material.
Further, described first kind of doping type is the n type, second kind of doping type p type; Perhaps, described first kind of doping type is the p type, second kind of doping type n type.
Further, before said recess channel zone formed, the zone of said second kind of doping type extended to the below, zone of said first kind of doping type in the horizontal direction.Said recess channel zone is two parts with the region separation of said second kind of doping type, and the part in divided two parts is positioned at the below, zone of said first kind of doping type.
The manufacturing approach of the recessed channel-type PNPN field effect transistor that the present invention proposes; Be to form source region, depletion region and drain region through self-registered technology, only need carry out primary ions injection technology and a diffusion technology, technical process is simple; Efficient is high, has reduced production cost.
Description of drawings
Fig. 1 is the sectional view of existing a kind of recessed channel-type PNPN field effect transistor structure.
Fig. 2 a to Fig. 2 g is an embodiment process chart of the manufacturing approach of recessed channel-type PNPN field effect transistor provided by the invention.
Embodiment
Below with reference to accompanying drawings an illustrative embodiments of the present invention is elaborated.In the drawings, the thickness in layer and zone has been amplified in explanation for ease, shown in size do not represent actual size.Although these figure are not the actual size that reflects device of entirely accurate, their zones that still has been complete reflection and form the mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.
Reference diagram is the sketch map of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all representes with rectangle, and the expression among the figure is schematically, but this should not be considered to limit scope of the present invention.Simultaneously in the following description, employed term substrate is appreciated that to be to comprise the just Semiconductor substrate in processes, possibly comprise other prepared thin layer above that.
At first, on the Semiconductor substrate that provides, carry out p type ion and inject formation doped region 201a, shown in Fig. 2 a, wherein, substrate 200a is the silicon layer that contains light dope n type or p type impurity, or is insulating oxide; Substrate 200b is the silicon layer of light dope p type impurity.
Next, deposit forms one deck insulation film 202 and one deck photoresist 203, and etching insulation film 202 and doped region 201a form source region 201 and expose the semiconductor substrate region of carrying out follow-up doping, shown in Fig. 2 b then.Insulation film 202 can or be the insulating material that mixes mutually between them for silicon dioxide, silicon nitride.
Next, deposit forms one deck silicon nitride film, and silicon nitride film is carried out the side wall 204 that etching forms source region 201, shown in Fig. 2 c.
Next, utilize diffusion technology, form n type diffusion region 205, shown in Fig. 2 d, n type diffusion region 205 extends to the below in source region 201.
Next; Deposit forms one deck insulation film 206 such as being silicon dioxide or silicon nitride; Etching forms the recess channel zone 207 of device then, and in this step process, side wall 204 is etched away fully; N type diffusion region 205 also can be fallen and is separated into drain region 205a and depletion region 205b by recess channel zone 207 by partial etching, shown in Fig. 2 e.It is also to be noted that simultaneously in this step process, source region 201 can not be etched, and can be fallen by partial etching yet.
Next, form one deck insulation film 208, insulation film 208 comprises the silica membrane and a floor height k material layer of one deck heat growth.Deposit forms layer of conductive film 209 again, and conductive film 209 can be TiN, TaN, RuO
2, Ru, WSi alloy or polycrystalline silicon material for mixing, etching forms the grid structure of device then, shown in Fig. 2 f.In the insulation film 208, silicon dioxide is as insulating barrier, and thickness is several dusts, and purpose is to improve interfacial characteristics; The thickness of hafnium layer is several nanometers to tens nanometer, and purpose is to reduce leakage current.
At last, etch away unnecessary insulation film 208, and divest remaining insulation film 206 and insulation film 202; Then; Deposit forms one deck insulation film 210, then insulation film 210 is carried out etching and forms through-hole structure, and insulation film 210 can or be a silicon nitride for silica; Then deposit layer of metal again can or be a tungsten for aluminium.Etching forms source electrode 211, gate electrode 212 and drain electrode 213 then, finally forms the recess channel PNPN field-effect transistor shown in Fig. 2 g.
As stated, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the instantiation described in the specification.
Claims (9)
1. the manufacturing approach of a recessed channel-type PNPN field effect transistor is characterized in that concrete steps are:
Semiconductor substrate with first kind of doping type is provided;
Carry out ion and inject, in the Semiconductor substrate that provides, form the zone of first kind of doping type;
Deposit forms first kind of insulation film on the Semiconductor substrate that the step handles on the warp;
Through photoetching, the zone of said first kind of insulation film and first kind of doping type is etched away, expose the semiconductor substrate region of carrying out follow-up doping;
On the structure of last step formation, deposit forms second kind of insulation film; Carry out anisotropic etching then, form the side wall that constitutes by second kind of insulation film;
On the structure of last step formation, directly spread, form the zone of second kind of doping type;
Deposit forms the third insulation film on the structure that last walking becomes;
Form the recess channel zone of device through the Alignment Method etching; This recess channel is the U type; In this step, above-mentioned side wall is etched away fully;
On the structure that last walking becomes, form the 4th kind of insulation film;
Deposit forms first kind of conductive film on the structure that last walking becomes;
Etching forms the grid structure of device, promptly through photoetching, etches away not protected first kind of conductive film as grid, etches list structure; This grid is positioned at the recess channel top;
Divest remaining first kind, the third insulation film;
Deposit forms the 5th kind of insulation film on the structure that last walking becomes, and said the 5th kind of insulation film carried out etching formation through-hole structure; I.e. perforate above grid forms the grid contact hole, first kind of doped region and second kind of doped region perforate respectively in the grid both sides, the contact hole of formation source electrode and drain electrode;
Second kind of conductive film of deposit forms electrode.
2. manufacturing approach as claimed in claim 1 is characterized in that, described Semiconductor substrate is the silicon on monocrystalline silicon, polysilicon or the insulator.
3. manufacturing approach as claimed in claim 1 is characterized in that, described first kind of doping type is the n type; Second kind of doping type p type.
4. manufacturing approach as claimed in claim 1 is characterized in that, described first kind of doping type is the p type; Second kind of doping type n type.
5. manufacturing approach as claimed in claim 1 is characterized in that, said first kind, second kind, the third, the 5th kind of insulation film be silicon dioxide, silicon nitride or the insulating material for mixing mutually between them.
6. manufacturing approach as claimed in claim 1 is characterized in that, said first kind of conductive film is TiN, TaN, RuO
2, Ru or WSi alloy, perhaps polycrystalline silicon material for mixing.
7. manufacturing approach as claimed in claim 1 is characterized in that, described second kind of conductive film is metallic aluminium, tungsten.
8. manufacturing approach as claimed in claim 1 is characterized in that, before said recess channel zone formed, the zone of said second kind of doping type extended to the below, zone of said first kind of doping type in the horizontal direction.
9. manufacturing approach as claimed in claim 1; It is characterized in that; Said recess channel zone is two parts with the region separation of said second kind of doping type, and the part in divided two parts is positioned at the below, zone of said first kind of doping type.
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| CN2010101863734A CN101866858B (en) | 2010-05-27 | 2010-05-27 | Manufacture method of sinking channel type PNPN field effect transistor |
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| CN2010101863734A CN101866858B (en) | 2010-05-27 | 2010-05-27 | Manufacture method of sinking channel type PNPN field effect transistor |
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| CN101866858B true CN101866858B (en) | 2012-07-04 |
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| KR101583594B1 (en) * | 2010-12-17 | 2016-01-12 | 킹스톤 세미컨덕터 코.,엘티디. | Doping method, pn structure, method for fabricating solar cell, and solar cell |
| CN103413829B (en) * | 2013-08-06 | 2018-04-27 | 复旦大学 | One kind is U-shaped to enclose grid tunneling transistor device and its manufacture method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1726596A (en) * | 2002-12-12 | 2006-01-25 | 西利康尼克斯股份有限公司 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| US7465976B2 (en) * | 2005-05-13 | 2008-12-16 | Intel Corporation | Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions |
| CN101699617A (en) * | 2009-10-29 | 2010-04-28 | 复旦大学 | Preparation method of self-aligned tunneling field effect transistor |
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| US7880160B2 (en) * | 2006-05-22 | 2011-02-01 | Qimonda Ag | Memory using tunneling field effect transistors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1726596A (en) * | 2002-12-12 | 2006-01-25 | 西利康尼克斯股份有限公司 | Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
| US7465976B2 (en) * | 2005-05-13 | 2008-12-16 | Intel Corporation | Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions |
| CN101699617A (en) * | 2009-10-29 | 2010-04-28 | 复旦大学 | Preparation method of self-aligned tunneling field effect transistor |
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Granted publication date: 20120704 Termination date: 20190527 |