CN101789374B - Method for preparing plane collision ionizing field effect transistor in self-aligning manner - Google Patents
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Abstract
The invention discloses a method for preparing a plane collision ionizing field effect transistor (IMOS) in a self-aligning manner. The requirement for the photoetching technique is lowered in preparation of the plane IMOS. In the method, a source-drain area, a channel area and a collision ionizing area of the IMOS are defined by primary photoetching, and the impact of aligning deviation does not exist; a dielectric film above the source area, the drain area and the collision ionizing area is eroded by a selective wet method in the follow-up process; and then the source-drain area, the channel area and the collision ionizing area of the IMOS can be prepared in sequence in a self-aligning manner; therefore, the impact on the aligning deviation by multiple photoetching in the traditional preparation technique of the IMOS is eliminated so as to be beneficial for preparing a plane IMOS device with stable and reliable characteristics.
Description
Technical field
The present invention relates to a kind of semiconductor device fabrication processes, relate in particular to a kind of impact-ionization field effect transistor (Impact-Ionization MOS, preparation method IMOS).
Background technology
For the performance and the integrated level that improve very lagre scale integrated circuit (VLSIC), the characteristic size of cmos device is constantly being dwindled.Yet in the process of device dimensions shrink, but be faced with serious power problems.Along with reducing of device size, supply voltage V
DdWith threshold voltage V
ThConstantly reduce drive current I
OnConstantly increase, but (Subthreshold Swing SS) can't equal proportion reduce sub-threshold slope, can increase on the contrary, causes leakage current I
OffIndex rises, and device quiescent dissipation index increases.So, how to make sub-threshold slope SS reduce just to become a key point that solves power problems.In addition, because conventional MOS FET is subjected to source end heat emission to inject the restriction of charge carrier physical mechanism, the sub-threshold slope under the room temperature (SS) can not break through 60mV/dec.So based on the MOSFET of the extremely low sub-threshold slope (SS) of novel working mechanism acquisition, for example impact-ionization field effect transistor (IMOS) causes researcher's concern day by day.
Typical n ditch IMOS along the schematic cross-section of channel direction as shown in Figure 1.On structure, IMOS is actually a grid-control PIN diode.Compare with traditional MOSFET, mainly contain following two differences on the structure: the doping type of the source-drain area of (1) IMOS is opposite, wherein, and N
+Be doped to drain terminal, add forward bias, P during work
+Be doped to the source end, add the negative sense biasing during work; (2) only some is covered by grid in the intrinsic region of IMOS, and this part zone that is not covered by grid between source and the raceway groove is the ionization by collision district of IMOS, i.e. i district.Be the operation principle of example brief description IMOS with n ditch IMOS below.When IMOS was in OFF state, as shown in Figure 2, grid voltage was lower than threshold voltage, and the electrical potential difference between source and the raceway groove is enough not big, and the electric field in i district is not enough to trigger charge carrier avalanche breakdown, and flowing through the electric current composition that leaks in the source mainly is the reverse leakage current of PIN diode.When IMOS is in ON state, as shown in Figure 3, grid voltage is higher than threshold voltage, and the electrical potential difference between source and the raceway groove is enough big, and the electric field in i district is greater than the threshold field that triggers avalanche breakdown, the avalanche multiplication effect takes place in the i district, form a large amount of electron-hole pairs, under high field action, electronics flows into raceway groove, finally collected, formed drain current by the drain region.Just because of the change of source end injection mode, IMOS at room temperature can obtain extremely low sub-threshold slope (SS).
But, just as shown in fig. 1, the IMOS device exists i district that grid do not cover and the source-drain area that needs counter-doping, the method of traditional preparation process planar I MOS needs repeatedly photoetching to finish the preparation in these zones, because the influence of lithography alignment deviation is very high to the requirement of photoetching process when adopting conventional non-autoregistration to prepare planar I MOS.In order to overcome the non-autoregistration problem of IMOS, can be as document Ulrich Abelein.et al.Solid-State Electronics, vol.51, pp.1405-1411,2007. and such IMOS for preparing vertical stratification of being reported such as the publication number Chinese patent that is CN101542737A.In addition, document Woo Young Choi.et al.IEEE Int.Electron Devices Meeting (IEDM) Tech.Dig., pp.975-978,2005. have reported that also a kind of autoregistration prepares the method for IMOS based on side wall technology.But, the IMOS grid and the covering excessively between the leakage of preparing by above these methods are very big, can cause big covering electric capacity and grid leak electricity excessively, and the IMOS of vertical stratification and existing plane very lagre scale integrated circuit (VLSIC) poor compatibility, be unfavorable for that IMOS and conventional planar MOSFET are integrated.So be necessary to prepare the method for IMOS based on traditional CMOS planar technique exploitation one cover autoregistration.
Summary of the invention
The object of the present invention is to provide that a kind of autoregistration prepares the method for IMOS based on planar technique, eliminated in the traditional preparation process IMOS technology owing to repeatedly between the photoetching influence of deviation of the alignment cause the unsettled defective of device performance.
Purpose of the present invention is achieved by following technical solution:
A kind of autoregistration prepares the method for planar I MOS, may further comprise the steps:
1) on substrate, define active area by shallow-trench isolation, grow successively then gate medium, deposit polysilicon, and carry out polysilicon gate and inject;
2) the hard medium I of deposit and etching on polysilicon gate forms two parallel hard medium I masks, and wherein article one mask has defined channel region, and the interval region between second mask and two masks has defined the ionization by collision district;
The length L g of channel region is directly defined by the width of article one mask in this step, and the length L i in ionization by collision district comprises the width of second mask and the spacing between two masks, so there are not deviation of the alignment in the channel region of device and ionization by collision district by defining out accurately with a photoetching.
3) be coated with the hard medium II of source region deposit, and with the upper surface of hard medium I mask for stopping the hard medium II of stratification mechanical polishing (CMP);
In this step, the hard medium II mask of both sides (the hard medium II mask parts between non-two hard medium I masks) has defined drain region and source region respectively, it is the drain region that the hard medium II mask in (left side shown in Fig. 4 (c)) has defined device outside the hard medium I of article one mask, the hard medium II mask in the hard medium I of the second mask outside (right side shown in Fig. 4 (c)) has defined the source region of device, wherein hard medium I is different materials with hard medium II, require to have between this two media material very high wet etching to select ratio, for example silicon nitride and silica so just can carry out selective corrosion to the hard mask that they form by using different chemical reagent.
4) resist coating on the mask of hard medium I and II formation, be about to form lithographic definition one through hole above the zone in drain region, remove the hard medium II of this top, zone by this through hole wet etching, remove photoresist again, be etched away the polysilicon of this top, zone subsequently, carry out n type ion doping and inject the drain region that forms device;
5) the hard medium II of deposit above the drain region, and with the upper surface of hard medium I mask for stopping the hard medium II of stratification mechanical polishing, thereby on the drain region, form hard mask, the drain region is protected;
6) resist coating on the mask of hard medium I and II formation, be about to form lithographic definition one through hole above the zone in source region, remove the hard medium II of this top, zone by this through hole wet etching, remove photoresist again, be etched away the polysilicon of this top, zone subsequently, carry out p type ion doping and inject the source region that forms device;
7) deposit polysilicon above the source region, for stopping stratification mechanical polishing (CMP) polysilicon, the polysilicon that further etching should the zone is to the lower surface of hard medium I mask again with the upper surface of hard medium I mask;
8) the hard medium II of deposit above the source region, and with the upper surface of hard medium I mask for stopping the hard medium II of stratification mechanical polishing;
9) deposit one polysilicon thin layer on the mask that hard medium I and II form, purpose is to play protective action in the hard medium I of follow-up selective corrosion process, avoid owing to photoresist also be corroded cause to the not corrosion of the hard medium I of selection area;
10) resist coating on the polysilicon thin layer of step 9) deposit, lithographic definition one through hole above the source region, and via hole image is transferred on the polysilicon thin layer by dry etching, remove the hard medium II of top, source region, the hard medium I of top, ionization by collision district and the hard medium II of top, ionization by collision district successively by this through hole selective wet etching, remove photoresist then;
11) etching is removed the polysilicon of polysilicon thin layer and source region and top, ionization by collision district, the hard medium II of deposit again, and with hard medium I mask upper surface for stopping the hard medium II of stratification mechanical polishing, got up by hard mask protection in source region and ionization by collision district;
12) annealing activator impurity adopts conventional CMOS technology to carry out the later process of transistor fabrication at last, obtains described impact-ionization field effect transistor.
Preferably, in the said method, the deposit polysilicon adopts chemical vapour deposition technique, and etch polysilicon adopts the anisotropic etching technology, the deposition process of hard medium I and II generally also is to adopt chemical vapour deposition technique, and the hard mask of etching adopts the anisotropic dry etch technology.
In the step 1) of said method, can grow one deck silica as gate dielectric layer, on gate dielectric layer, adopt chemical vapour deposition (CVD) deposit polysilicon by dry-oxygen oxidation method.
Above-mentioned steps 2) and 3) in, hard medium I can select silicon nitride for use, hard medium II can select silica for use, vice versa.Preferably, step 2) defines channel region and ionization by collision district by photoetching and the hard mask of etching: after the hard medium I of deposit forms hard mask, be coated with one deck photoresist thereon, lithographic definition channel region and ionization by collision district, then by etching with the figure transfer on the photoresist to this hard mask, remove photoresist subsequently.
Above-mentioned steps 4), 6) and 10) in, if among hard medium I and the II one be silicon nitride, another is silica, can adopt the hydrofluoric acid wet etching to remove silica, the SPA wet etching is removed silicon nitride.
Above-mentioned steps 5), 8) and/or 11) in, preferably using plasma strengthens chemical vapour deposition technique (PECVD) and comes the hard medium II of deposit, to reduce the diffusion of impurity in the deposition process.
Further; in above-mentioned steps 11) and 12) between can increase following step: the hard medium I that removes the channel region top by wet etching; again in hard medium II of this regional deposit and planarization, the hard mask protection that whole active area is all formed by hard medium II.
Above-mentioned steps 12) rapid thermal annealing (RTP) activator impurity in nitrogen; Described later process comprises the fairlead that forms grid, source and leakage by photoetching and etching, the layer of conductive film of growing then, photoetching and etching conductive film form electrode and interconnection again, the conductive film of being grown wherein, be generally metal material, as aluminium, titanium, copper etc., or the lamination of multiple metal material, as one deck titanium of growing earlier, and then growth aluminium.
Because the IMOS device exists grid ionization by collision district that does not cover and the source-drain area that needs counter-doping, the method of traditional preparation process planar I MOS needs repeatedly photoetching to finish the preparation in these zones, and this non-self aligned prepared flow process has proposed very high requirement to photoetching process.And in the method for the invention, come out by a lithographic definition in the source-drain area of IMOS, channel region and ionization by collision district, do not have the influence of deviation of the alignment.Wherein ionization by collision district and source-drain area are not directly to define by photoetching, but define by the deielectric-coating above their, by the deielectric-coating above selective wet etching source region in subsequent technique, drain region and the ionization by collision district, can self aligned successively they be prepared, eliminated in the traditional preparation process IMOS technology instability owing to the device property that repeatedly influence of deviation of the alignment causes between the photoetching.The present invention has been alleviated in the planar I MOS preparation process the harsh requirement of lithography alignment deviation, helps preparing the reliable planar I MOS device of stability of characteristics.
Description of drawings
Fig. 1 is the schematic cross-section of n ditch IMOS along channel direction, among the figure:
The 1-substrate; The 2-gate dielectric layer; The 3-heavily doped polysilicon; 4-N
+The drain region; 5-P
+The source region.
Band structure schematic diagram when Fig. 2 is n ditch IMOS OFF state.
Band structure schematic diagram when Fig. 3 is n ditch IMOS ON state.
Fig. 4 (a)-4 (v) is the schematic flow sheet that embodiment of the invention autoregistration prepares n ditch IMOS.Among the figure: the layers of material situation is as follows:
1-body silicon substrate; The 2-gate medium; The 3-polysilicon; The 4-silicon nitride; The 5-silica; The 6-photoresist; 7-N
+Mix silicon, i.e. the device drain region; 8-P
+Doped silicon, i.e. device source region; The 9-metal lead wire.
The brief description of technological process is as follows:
Fig. 4 (a) prepares gate medium on the Si substrate, the deposit polysilicon, and polysilicon gate injects, deposit silicon nitride; Fig. 4 (b) defines channel region (Lg) and ionization by collision district (Li) of IMOS on silicon nitride; Fig. 4 (c) silicon oxide deposition, then with silicon nitride as stopping the stratification mechanical polishing silica; Fig. 4 (d) defines through hole by photoetching above the drain region; Fig. 4 (e) wet etching removes top, drain region silica; Fig. 4 (f) removes photoresist; Fig. 4 (g) removes by the polysilicon of etching with the top, drain region; Fig. 4 (h) leaks injection, silicon oxide deposition, then with silicon nitride as stopping the stratification mechanical polishing silica; Fig. 4 (i) defines through hole by photoetching above the source region; Fig. 4 (j) wet etching removes top, source region silica, and removes photoresist; Fig. 4 (k) source is injected, the deposit polysilicon, then with silicon nitride as stopping stratification mechanical polishing polysilicon; Fig. 4 (l) etch polysilicon; Fig. 4 (m) silicon oxide deposition, then with silicon nitride as stopping the stratification mechanical polishing silica; Fig. 4 (n) deposit skim polysilicon; Fig. 4 (o) defines through hole by photoetching above the source region, etch polysilicon, wet etching remove the silica of top, source region; Fig. 4 (p) wet etching removes the silicon nitride of top, ionization by collision district (Li); Fig. 4 (q) wet etching removes the silica of top, ionization by collision district (Li); Fig. 4 (r) removes photoresist, and dry etching removes the polysilicon thin layer; Fig. 4 (s) forms the ionization by collision district (Li) of device by etch polysilicon; Fig. 4 (t) silicon oxide deposition, then with silicon nitride as stopping the stratification mechanical polishing silica; Fig. 4 (u) removes the silicon nitride of channel region top, silicon oxide deposition and planarization for wet etching; (v) later process finally realizes autoregistration IMOS to Fig. 4.
Embodiment
The present invention is described in detail below in conjunction with the drawings and specific embodiments, and specifically provide one and realize that the present invention proposes the process program of autoregistration n ditch IMOS, but the scope that does not limit the present invention in any way.
Prepare n ditch IMOS according to the following step:
1. substrate is the body silicon substrate, adopts traditional shallow-trench isolation (STI-shallow trench isolation) definition active area;
2. the oxidation of grid oxygen forms silica, i.e. gate dielectric layer, thick 50
3. low-pressure chemical vapor deposition (LPCVD) polysilicon on gate dielectric layer, thick 2000
4. polysilicon As is injected, inject energy 50Kev, dosage 4 * 10
15/ cm
2
5. low-pressure chemical vapor deposition (LPCVD) silicon nitride on polysilicon, thick 2000
Shown in Fig. 4 (a);
6. resist coating on silicon nitride, the channel region of lithographic definition IMOS (Lg) and ionization by collision district (Li);
7. by reactive ion etching technology (RIE) etch silicon nitride 2000
To this silicon nitride film, and the cleaning of removing photoresist is shown in Fig. 4 (b) with the figure transfer on the photoresist;
8. be coated with source region low-pressure chemical vapor deposition (LPCVD) silica, thick about 2500
With silicon nitride for stopping stratification mechanical polishing (CMP) silica, shown in Fig. 4 (c);
10. resist coating on silicon nitride and silica, lithographic definition one through hole above the drain region is shown in Fig. 4 (d);
11. top, hydrofluoric acid excessive erosion drain region silica is shown in Fig. 4 (e);
The cleaning 12. remove photoresist is shown in Fig. 4 (f);
13. reactive ion etching technology (RIE) etching is removed the polysilicon of top, drain region, shown in Fig. 4 (g);
Inject 14. As is carried out in the zone, drain region, inject energy 10Kev, dosage 4 * 10
15/ cm
2
15. cover drain region plasma enhanced CVD (PECVD) silica, thick about 4500
16. with silicon nitride for stopping stratification mechanical polishing (CMP) silica, shown in Fig. 4 (h);
17. resist coating on silicon nitride and the silica, lithographic definition one through hole above the source region is shown in Fig. 4 (i);
18. the silica of top, hydrofluoric acid excessive erosion source region;
The cleaning 19. remove photoresist is shown in Fig. 4 (j);
20. reactive ion etching technology (RIE) is etched away the polysilicon of top, source region;
21. active area regions is carried out BF
2Inject, inject energy 10Kev, dosage 3 * 10
15/ cm
2
22. cover source region plasma enhanced CVD (PECVD) polysilicon, thick about 4500
23. with silicon nitride for stopping stratification mechanical polishing (CMP) polysilicon, shown in Fig. 4 (k);
24. reactive ion etching technology (RIE) etch polysilicon is shown in Fig. 4 (l);
25. cover source region plasma enhanced CVD (PECVD) silica, thick about 2500
26. with silicon nitride for stopping stratification mechanical polishing (CMP) silica, shown in Fig. 4 (m);
27. plasma enhanced CVD on silicon nitride and silica (PECVD) skim polysilicon, thick 200
Shown in Fig. 4 (n);
28. resist coating on the polysilicon thin layer defines a through hole by photoetching above the source region;
29. reactive ion etching technology (RIE) etch polysilicon thin layer is transferred to via hole image on the polysilicon thin layer;
30. the silica of top, source region is removed in the hydrofluoric acid excessive erosion, shown in Fig. 4 (o);
31. SPA is over-cooked the silicon nitride of removing top, ionization by collision district (Li), shown in Fig. 4 (p);
32. the silica of top, ionization by collision district (Li) is removed in the hydrofluoric acid excessive erosion, shown in Fig. 4 (q);
The cleaning 33. remove photoresist;
34. reactive ion etching technology (RIE) etching is removed polysilicon thin layer 200
Shown in Fig. 4 (r);
35. reactive ion etching technology (RIE) etching is removed the polysilicon 2000 of top, ionization by collision district
Prepare the ionization by collision district (Li) of device, shown in Fig. 4 (s);
36. cover source region and ionization by collision district plasma enhanced CVD (PECVD) silica, thick about 4500
37. with silicon nitride for stopping stratification mechanical polishing (CMP) silica, shown in Fig. 4 (t);
38. hot SPA erodes the silicon nitride of channel region top;
39. cover channel region plasma enhanced CVD (PECVD) silica, and chemico-mechanical polishing (CMP) silica, maximum ga(u)ge 4000
Shown in Fig. 4 (u);
40. with device as for 5 seconds of 1050 ℃ of rapid thermal annealings (RTP) in the nitrogen, activator impurity;
41. resist coating on the silica medium protective layer, the shape in lithographic definition device wire hole;
42.RIE etching oxidation silicon forms fairlead;
43. adopt buffered hydrofluoric acid (BHF) that the silica erosion in the fairlead is clean;
The cleaning 44. remove photoresist;
45. splash-proofing sputtering metal titanium and aluminium successively, thickness is respectively 700
With 1 μ m, form conductive metal film;
46. resist coating on conductive metal film, the shape of lithographic definition device metal lead-in wire;
47.RIE etching metallic aluminium and Titanium form lead-in wire successively;
The cleaning 48. remove photoresist;
49. alloying: N
2+ H
2In 430 ℃ of down annealing 30 minutes, form as Fig. 4 (structure v).
Above-described embodiment is used to limit the present invention, and any those skilled in the art without departing from the spirit and scope of the present invention, can do various changes and retouching, so protection scope of the present invention is looked the claim scope and defined.
Claims (10)
1. an autoregistration prepares the method for plane impact-ionization field effect transistor, may further comprise the steps:
1) on substrate, define active area by shallow-trench isolation, grow successively then gate medium, deposit polysilicon, and carry out polysilicon gate and inject;
2) the hard medium I of deposit and etching on polysilicon gate forms two parallel hard medium I masks, and wherein article one mask has defined channel region, and the interval region between second mask and two masks has defined the ionization by collision district;
3) be coated with the hard medium II of source region deposit, and with the upper surface of hard medium I mask for stopping the hard medium II of stratification mechanical polishing, wherein hard medium I and firmly medium II be different materials, can carry out selective corrosion by different chemical reagent;
4) resist coating on the mask of hard medium I and II formation, be about to form lithographic definition one through hole above the zone in drain region, remove the hard medium II of this top, zone by this through hole wet etching, remove photoresist again, be etched away the polysilicon of this top, zone subsequently, carry out n type ion doping and inject the drain region that forms device;
5) the hard medium II of deposit above the drain region, and with the upper surface of hard medium I mask for stopping the hard medium II of stratification mechanical polishing, form the hard mask in protection drain region;
6) resist coating on the mask of hard medium I and II formation, be about to form lithographic definition one through hole above the zone in source region, remove the hard medium II of this top, zone by this through hole wet etching, remove photoresist again, be etched away the polysilicon of this top, zone subsequently, carry out p type ion doping and inject the source region that forms device;
7) deposit polysilicon above the source region, with the upper surface of hard medium I mask for stopping stratification mechanical polishing polysilicon, more further top, etching source region polysilicon to the lower surface of hard medium I mask;
8) the hard medium II of deposit above the source region, and with the upper surface of hard medium I mask for stopping the hard medium II of stratification mechanical polishing;
9) deposit one polysilicon thin layer on the mask of hard medium I and II formation;
10) resist coating on the polysilicon thin layer of step 9) deposit, lithographic definition one through hole above the source region, and via hole image is transferred on the polysilicon thin layer by dry etching, remove the hard medium II of top, source region, the hard medium I of top, ionization by collision district and the hard medium II of top, ionization by collision district successively by this through hole selective wet etching, remove photoresist then;
11) etching is removed the polysilicon of polysilicon thin layer and source region and top, ionization by collision district, the hard medium II of deposit again, and with hard medium I mask upper surface for stopping the hard medium II of stratification mechanical polishing, the hard mask in source region and ionization by collision district is protected in formation;
12) the annealing activator impurity is finished the later process of transistor fabrication.
2. the method for claim 1; it is characterized in that; described step 11) and 12) increases following step between: remove the hard medium I of channel region top by wet etching,, form the hard medium II mask of the whole active area of protection again in hard medium II of this regional deposit and planarization.
3. method as claimed in claim 1 or 2 is characterized in that, described hard medium I is a silicon nitride, and hard medium II is a silica; Perhaps, hard medium I is a silica, and hard medium II is a silicon nitride.
4. method as claimed in claim 3 is characterized in that, the chemical reagent that wet etching is removed the silica employing is a hydrofluoric acid, and the chemical reagent that wet etching is removed the silicon nitride employing is a SPA.
5. the method for claim 1 is characterized in that, deposit polysilicon, hard medium I and hard medium II adopt CVD (Chemical Vapor Deposition) method, and etch polysilicon and hard medium I adopt the anisotropic dry etch technology.
6. the method for claim 1 is characterized in that, grows one deck silica as described gate medium by dry-oxygen oxidation method in the described step 1), adopts the described polysilicon of chemical vapour deposition (CVD) deposit on described gate medium.
7. the method for claim 1, it is characterized in that, described step 2) concrete grammar in definition channel region and ionization by collision district is in: the hard medium I of deposit also is coated with one deck photoresist thereon, lithographic definition channel region and ionization by collision district, then by etching with the figure transfer on the photoresist to hard medium I mask, remove photoresist subsequently.
8. the method for claim 1 is characterized in that, in step 5), 8) and/or 11) in using plasma strengthen the hard medium II of chemical vapour deposition technique deposit.
9. the method for claim 1 is characterized in that, described step 12) is the rapid thermal annealing activator impurity in nitrogen.
10. the method for claim 1 is characterized in that, later process described in the step 12) is the fairlead that forms grid, source and leakage by photoetching and etching, the conductive film of growing then, and photoetching and etching conductive film form electrode and interconnection again.
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Effective date of registration: 20130523 Address after: 100176 No. 18, Wenchang Avenue, Beijing economic and Technological Development Zone Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Peking University Address before: 100871 Haidian District the Summer Palace Road,, No. 5, Peking University Patentee before: Peking University |