CN101192574A - CMOSCMOS device stress membrane forming method and CMOS device - Google Patents
CMOSCMOS device stress membrane forming method and CMOS device Download PDFInfo
- Publication number
- CN101192574A CN101192574A CNA2006101188403A CN200610118840A CN101192574A CN 101192574 A CN101192574 A CN 101192574A CN A2006101188403 A CNA2006101188403 A CN A2006101188403A CN 200610118840 A CN200610118840 A CN 200610118840A CN 101192574 A CN101192574 A CN 101192574A
- Authority
- CN
- China
- Prior art keywords
- stress film
- stress
- pmos transistor
- photoresist layer
- nmos pass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a method for forming a stress membrane of a CMOS device and the CMOS device. The CMOS device includes a NMOS transistor and a PMOS transistor. The surface of the NMOS transistor has a first stress membrane. The surface of the PMOS transistor has a second stress membrane. The interface of the first stress membrane and the second stress membrane is an inclined plane. The method for forming the stress membrane of the CMOS device can remove the salient on the stress membrane conjunction part of the NMOS transistor and the PMOS transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method and cmos device that forms the cmos device stress film.
Background technology
In semi-conductor industry, knownly produce mechanical stress forming on the doped region on film that stress film can be by containing impurity down below or the substrate, increase the related semiconductor component speeds.Such stress has been promoted the energy of impurity.Doping or electric charge carrier that energy increases can make semiconductor element, and for example transistor has higher running speed, and therefore the applied stress film is helpful in the various suitable application.
Between more than ten years in the past, utilize reduction mos field effect transistor (Metal-oxide-semiconductor Field-effect Transistors, MOSFET) mode of size, so as to the component density and the cost of the service speed of each function element of improving integrated circuit constantly, usefulness performance, circuit, the method for reduction mainly comprises the thickness of reduction of gate length and grid oxic horizon.Make the MOSFET element in order further to promote transistorized usefulness, utilize the strained channel zone that is arranged in the Semiconductor substrate some.For complementary metal oxide semiconductor field effect transistor (CMOS), with the MOSFET of n type or the MOSFET of p type, use the strained channel zone can improve the mobility of charge carrier rate, to increase the usefulness of element.Application number is to disclose a kind of mos field effect transistor with compartmentalization stress structure in 200510093507.7 the Chinese patent application, this mos field effect transistor is on the direction of source electrode one drain electrode, in the n of NMOSFET type passage, form the stress film of elongation strain (Tensile Strain), can increase the mobility of electronics, and on the direction of source electrode one drain electrode, in the p of PMOSFET type passage, form the stress film of compression strain (Compressive Strain), can increase the mobility in hole.Fig. 1 is the stress film position view of cmos device.As shown in Figure 1, on nmos pass transistor 116, form the stress film 110 of elongation strain (TensileStrain), can increase the mobility of electronics, and on PMOS transistor 117, form the stress film 120 of compression strain (Compressive Strain), can increase the mobility in hole.But the contact site 118 in stress film 110 and 120 protruding phenomenon occurs through regular meeting, and Fig. 2 to Fig. 5 is this schematic diagram that convexes to form process of explanation.In the process that forms stress film, form wherein one deck earlier, for example on nmos pass transistor 116, form earlier the stress film 110 of elongation strain (Tensile Strain), on PMOS transistor 117 and stress film 110, deposit another ply stress film 120 then, as shown in Figure 2; On the stress film 120 that covers PMOS transistor 117, form photoresist figure 112 again, as shown in Figure 3; Utilize photoresist figure 112 to fall to cover stress film on the nmos pass transistor 116 subsequently, as shown in Figure 4 for mask etching; Because during deposition stress film 120, this stress film also covers the stress film 110 of previous formation, therefore after removing photoresist figure 112, can stay projection 113 in the junction of stress film 110 and 120, influence the carrying out of subsequent technique.
Summary of the invention
The invention provides a kind of formation method and cmos device of cmos device stress film, can eliminate the projection of nmos pass transistor and PMOS transistor stress film junction.
A kind of method that forms the cmos device stress film provided by the invention, described cmos device comprises nmos pass transistor and PMOS transistor, described method comprises the following steps:
At described nmos pass transistor and PMOS transistor surface deposition first stress film;
At the described first stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover first stress film on described nmos pass transistor surface and exposes first stress film on described PMOS transistor surface;
First stress film on the described PMOS transistor of etching surface;
Remove described photoresist layer, deposition second stress film on first stress film on described nmos pass transistor surface and described PMOS transistor;
At the described second stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover second stress film on described PMOS transistor surface and exposes second stress film that covers described nmos pass transistor surface first stress film;
Etching covers second stress film of described nmos pass transistor surface first stress film;
Remove the photoresist layer on the described second stress film surface.
The etching gas of first stress film on the described PMOS transistor of etching surface comprises argon Ar, tetrafluoromethane CF4, perfluoroethane C2F6 and fluoroform CHF3.
The flow of described argon Ar is 50sccm～400sccm; The flow of tetrafluoromethane CF4 is 10sccm～100sccm; The flow of perfluoroethane C2F6 is 10sccm～400sccm; The flow of fluoroform CHF3 is 10sccm～100sccm.
The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～250W.
Pressure in the described reative cell is 50mTorr～200mTorr.
The material of described first stress film and second stress film is a silicon nitride.
Described first stress film is the stress film with tensile stress, and described second stress film is the stress film with compression stress.
The another kind of method that forms the cmos device stress film provided by the invention, described cmos device comprises nmos pass transistor and PMOS transistor, described method comprises the following steps:
At described nmos pass transistor and PMOS transistor surface deposition first stress film;
At the described first stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover first stress film on described PMOS transistor surface and exposes first stress film on described nmos pass transistor surface;
First stress film on the described nmos pass transistor of etching surface;
Remove described photoresist layer, first stress film and described nmos pass transistor surface deposition second stress film on described PMOS transistor surface;
At the described second stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover second stress film on described nmos pass transistor surface and exposes second stress film that covers described PMOS transistor surface first stress film;
Etching covers second stress film of described PMOS transistor surface first stress film;
Remove the photoresist layer on the described second stress film surface.
The etching gas of first stress film on the described PMOS transistor of etching surface comprises argon Ar, tetrafluoromethane CF4, perfluoroethane C2F6 and fluoroform CHF3.
The flow of described argon Ar is 50sccm～400sccm; The flow of tetrafluoromethane CF4 is 10sccm～100sccm; The flow of perfluoroethane C2F6 is 10sccm～400sccm; The flow of fluoroform CHF3 is 10sccm～100sccm.
The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～250W.
Pressure in the described reative cell is 50mTorr～200mTorr.
The material of described first stress film and second stress film is a silicon nitride.
Described first stress film is the stress film with compression stress, and described second stress film is the stress film with tensile stress.
Correspondingly, a kind of cmos device provided by the invention, described cmos device comprises nmos pass transistor and PMOS transistor, described nmos pass transistor surface has first stress film, described PMOS transistor surface has second stress film, it is characterized in that: the contact-making surface of described first stress film and described second stress film is the inclined-plane.
Described bevel angle is 25 degree～75 degree.
Described first stress film is the stress film with tensile stress, and described second stress film is the stress film with compression stress.
Compared with prior art, the present invention has the following advantages:
The formation method of cmos device stress film of the present invention at first forms tensile stress film at nmos pass transistor and the transistorized surface of PMOS; Etch away the tensile stress film that covers described PMOS transistor surface then, in etching process, adopt the process conditions of etching sidewall spacer (offset spacer) to carry out etching, after making the tensile stress film that etches away PMOS transistor surface, the section of the tensile stress film of reservation is the inclined-plane.At the stretching battalion film surface deposition compression stress film of PMOS transistor surface and nmos pass transistor, etch away the compression stress film of the stretching battalion film surface deposition of nmos pass transistor subsequently then.Because the section of etching stress film is the inclined-plane for the first time, make the stress film of subsequent deposition can not form too high projection in the junction of stress film, behind the stress film of etching subsequent deposition, can form smooth composition surface, eliminate the protruding phenomenon of the junction of nmos pass transistor surface tensile stress film and PMOS transistor surface compression stress film.In addition,, therefore help eliminating the junction and concentrate, help the Stress Release of two-layer stress film junction because of the stress of reason generations such as being heated because the contact-making surface of tensile stress film and compression stress film is the inclined-plane.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 is the stress film position view of cmos device;
Fig. 2 to Fig. 5 is the schematic diagram of the forming process of the existing cmos device stress film junction of explanation projection;
Fig. 6 to Figure 13 is the generalized section according to the cmos device stress film forming process of the embodiment of the invention;
Figure 14 is the cmos device structural representation according to the embodiment of the invention.
Described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The method of stress film provided by the invention relates to PMOS transistor and the nmos pass transistor among the CMOS.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Fig. 6 to Figure 13 is the generalized section according to the cmos device stress film forming process of the embodiment of the invention.As shown in Figure 6, the cmos device that forms on Semiconductor substrate 100 comprises nmos pass transistor 116 and PMOS transistor 117, nmos pass transistor 116 and PMOS transistor 117 comprise grid, grid oxic horizon and grid side walls sept (offset spacer), and source region and drain region in the substrate of grid both sides.The STI isolated groove that in substrate, has also comprised buffer action.Substrate 100 can be the silicon materials that comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Deposition first stress film 110 on described nmos pass transistor 116 and PMOS transistor 117, the method of deposition can adopt chemical vapor deposition (CVD) technology, physical vapor deposition (PVD) technology or ald (ALD) technology, in preferred embodiment, the material of stress film 110 is a silicon nitride, and the thickness of stress film 110 is
And after forming described stress film, carry out annealing steps, in various embodiments, various method for annealing be can use, Halogen lamp LED or tungsten lamp for example used, the temperature of annealing is 800～1000 ℃, and first stress film 110 after the annealing is retes that a kind of edge laterally has tensile stress.The zone of 118 indications is the junction of the stress film and the transistorized stress film of PMOS of nmos pass transistor among Fig. 6.
Fig. 7 to Figure 13 is the partial enlarged drawing in zone 118 among Fig. 6 of explanation the inventive method.As shown in Figure 7, and in conjunction with Fig. 6, utilize spin coating (spin on) technology coating photoresist on first stress film, 110 surfaces, the thickness of photoresist is
Be preferably
And pass through photoetching processes such as exposure, development with the photoresist patterning, form photoresist figure 114.Photoresist figure 114 covers first stress film 110 on described nmos pass transistor 116 surfaces, and exposes first stress film 110 on described PMOS transistor 117 surfaces.
Next as shown in Figure 8, be mask with photoresist figure 114, first stress film 110 on etching PMOS transistor 117 surfaces.Can use above-mentioned first stress film 110 of various suitable dry etching method etchings, for example reactive ion etching or plasma etching.In etching process, in reative cell, the using plasma etching technics carries out etching.During etching, the directivity of etching can realize by the bias power and negative electrode (substrate just) substrate bias power of control plasma source.The etching gas of first stress film 110 on etching PMOS transistor surface comprises argon Ar, tetrafluoromethane CF4, perfluoroethane C2F6 and fluoroform CHF3.Feed above-mentioned gas in reative cell simultaneously, wherein argon Ar plays the effect of dilution etching gas, and its flow is 50sccm～400sccm; Rise in the gas of corrasion, the flow of tetrafluoromethane CF4 is 10sccm～100sccm; The flow of perfluoroethane C2F6 is 10sccm～400sccm; The flow of fluoroform CHF3 is 10sccm～100sccm.The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～250W.Pressure in the reative cell is set to 50mTorr～200mTorr, and underlayer temperature is controlled between 20 ℃ and 90 ℃.The process of above-mentioned plasma etching is a kind of anisotropic etching, and the acting in conjunction of etching gas and diluent gas makes the section 200 of the silicon nitride stress film 110 after the etching be the inclined-plane, and the angle of inclination on inclined-plane 200 is 25 to spend to 75 degree.Next, as shown in Figure 9, adopt wet-cleaned or oxygen ashing process to remove photoresist mask pattern 114.
Then as shown in figure 10, utilize CVD technology, PVD technology or ALD technology, deposition second stress film 120 on described nmos pass transistor surface 116 first stress films 110 and described PMOS transistor 117.The material of this second stress film 120 is a silicon nitride, and thickness is identical with the thickness of first stress film 110.Carry out annealing in process then, in various embodiments, the temperature of annealing can be used various method for annealing between 600～800 ℃, for example use Halogen lamp LED or tungsten lamp.Second stress film 120 after the annealing is retes that a kind of edge laterally has compression stress.
Next as shown in figure 11, utilize spin coating (spin on) technology coating photoresist on second stress film, 120 surfaces, the thickness of photoresist is
Be preferably
And pass through photoetching processes such as exposure, development with the photoresist patterning, form photoresist figure 115.Photoresist figure 115 covers second stress film 120 on PMOS transistor 117 surfaces and exposes second stress film 120 ' that covers described nmos pass transistor 116 surperficial first stress films 110.
Then, be second stress film 120 ' that mask etching covers first stress film 110 with photoresist mask pattern 115.Can adopt dry etching, for example the method for plasma etching is etched to and exposes a stress film 110 surfaces.In etching process, in reative cell, the using plasma etching technics carries out etching to above-mentioned each layer.During etching, the directivity of etching can realize by the bias power and negative electrode (substrate just) substrate bias power of control plasma source.In the present embodiment, feed etchant gas flow 50-400sccm in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source power output 50W-2000W.Etching agent adopts mist, and mist can comprise as SF6, CHF3, CF4, chlorine Cl
2, nitrogen N
2, helium He and oxygen O
2Mist, and inert gas (such as hydrogen Ar, neon Ne, helium He or the like) or its combination.This etching agent has very high etching selection for the second stress film material silicon nitride material.Etching second stress film 120 ' until with first stress film, 110 flush, as shown in figure 12.Adopt wet-cleaned or cineration technics to remove photoresist figure 115 at last, as shown in figure 13.The composition surface 200 of the compression stress film 120 that tensile stress film 110 that forms on nmos pass transistor 116 surfaces and PMOS transistor 117 surfaces form is the inclined-plane, help eliminating the junction and concentrate, help the Stress Release of two-layer stress film junction because of the stress of reason generations such as being heated.
Be on nmos pass transistor and PMOS transistor, to form first stress film earlier among the embodiment of the invention described above, and then form second stress film with compression stress with tensile stress.In other embodiments of the invention, also can on nmos pass transistor and PMOS transistor, form first stress film earlier with compression stress.Specifically, in another embodiment of the present invention, earlier at nmos pass transistor and PMOS transistor surface deposition first stress film; Then at the described first stress film surface coated photoresist layer; The described photoresist layer of patterning makes described photoresist layer cover first stress film on described PMOS transistor surface and exposes first stress film on described nmos pass transistor surface; First stress film on the described nmos pass transistor of etching surface; Remove described photoresist layer, first stress film and described nmos pass transistor surface deposition second stress film on described PMOS transistor surface; At the described second stress film surface coated photoresist layer; The described photoresist layer of patterning makes described photoresist layer cover second stress film on described nmos pass transistor surface and exposes second stress film that covers described PMOS transistor surface first stress film; Etching covers second stress film of described PMOS transistor surface first stress film; Remove the photoresist layer on the described second stress film surface.Described first stress film is the stress film with compression stress, and described second stress film is the stress film with tensile stress.
The etching gas of first stress film on the described PMOS transistor of etching surface comprises argon Ar, tetrafluoromethane CF4, perfluoroethane C2F6 and fluoroform CHF3.Wherein the flow of argon Ar is 50sccm～400sccm; The flow of tetrafluoromethane CF4 is 10sccm～100sccm; The flow of perfluoroethane C2F6 is 10sccm～400sccm; The flow of fluoroform CHF3 is 10sccm～100sccm.The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～250W, and the pressure in the reative cell is 50mTorr～200mTorr.The material of described first stress film and second stress film is a silicon nitride.
Figure 14 is the cmos device structural representation according to the embodiment of the invention, as shown in figure 14, cmos device of the present invention comprises nmos pass transistor 116 and PMOS transistor 117, nmos pass transistor 116 surfaces have first stress film 110, PMOS transistor 117 surfaces have second stress film 120, the contact-making surface 200 of first stress film 110 and second stress film 120 is the inclined-plane, and the angle on inclined-plane is 25 degree～75 degree.The stress film of first stress film 110 for having tensile stress, the stress film of second stress film 120 for having compression stress.The composition surface 200 of the compression stress film 120 that tensile stress film 110 that forms on nmos pass transistor 116 surfaces and PMOS transistor 117 surfaces form is the inclined-plane, helps the Stress Release of stress film junction.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (17)
1. method that forms the cmos device stress film, described cmos device comprises nmos pass transistor and PMOS transistor, described method comprises the following steps:
At described nmos pass transistor and PMOS transistor surface deposition first stress film;
At the described first stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover first stress film on described nmos pass transistor surface and exposes first stress film on described PMOS transistor surface;
First stress film on the described PMOS transistor of etching surface;
Remove described photoresist layer, deposition second stress film on first stress film on described nmos pass transistor surface and described PMOS transistor;
At the described second stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover second stress film on described PMOS transistor surface and exposes second stress film that covers described nmos pass transistor surface first stress film;
Etching covers second stress film of described nmos pass transistor surface first stress film;
Remove the photoresist layer on the described second stress film surface.
2. the method for claim 1, it is characterized in that: the etching gas of first stress film on the described PMOS transistor of etching surface comprises argon Ar, tetrafluoromethane CF4, perfluoroethane C2F6 and fluoroform CHF3.
3. method as claimed in claim 2 is characterized in that: the flow of described argon Ar is 50sccm～400sccm; The flow of tetrafluoromethane CF4 is 10sccm～100sccm; The flow of perfluoroethane C2F6 is 10sccm～400sccm; The flow of fluoroform CHF3 is 10sccm～100sccm.
4. method as claimed in claim 3 is characterized in that: the power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～250W.
5. method as claimed in claim 4 is characterized in that: the pressure in the described reative cell is 50mTorr～200mTorr.
6. the method for claim 1, it is characterized in that: the material of described first stress film and second stress film is a silicon nitride.
7. method as claimed in claim 6 is characterized in that: described first stress film is the stress film with tensile stress, and described second stress film is the stress film with compression stress.
8. method that forms the cmos device stress film, described cmos device comprises nmos pass transistor and PMOS transistor, described method comprises the following steps:
At described nmos pass transistor and PMOS transistor surface deposition first stress film;
At the described first stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover first stress film on described PMOS transistor surface and exposes first stress film on described nmos pass transistor surface;
First stress film on the described nmos pass transistor of etching surface;
Remove described photoresist layer, first stress film and described nmos pass transistor surface deposition second stress film on described PMOS transistor surface;
At the described second stress film surface coated photoresist layer;
The described photoresist layer of patterning makes described photoresist layer cover second stress film on described nmos pass transistor surface and exposes second stress film that covers described PMOS transistor surface first stress film;
Etching covers second stress film of described PMOS transistor surface first stress film;
Remove the photoresist layer on the described second stress film surface.
9. method as claimed in claim 8 is characterized in that: the etching gas of first stress film on the described PMOS transistor of etching surface comprises argon Ar, tetrafluoromethane CF4, perfluoroethane C2F6 and fluoroform CHF3.
10. method as claimed in claim 9 is characterized in that: the flow of described argon Ar is 50sccm～400sccm; The flow of tetrafluoromethane CF4 is 10sccm～100sccm; The flow of perfluoroethane C2F6 is 10sccm～400sccm; The flow of fluoroform CHF3 is 10sccm～100sccm.
11. method as claimed in claim 10 is characterized in that: the power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～250W.
12. method as claimed in claim 11 is characterized in that: the pressure in the described reative cell is 50mTorr～200mTorr.
13. method as claimed in claim 8 is characterized in that: the material of described first stress film and second stress film is a silicon nitride.
14. method as claimed in claim 13 is characterized in that: described first stress film is the stress film with compression stress, and described second stress film is the stress film with tensile stress.
15. cmos device, described cmos device comprises nmos pass transistor and PMOS transistor, described nmos pass transistor surface has first stress film, and described PMOS transistor surface has second stress film, it is characterized in that: the contact-making surface of described first stress film and described second stress film is the inclined-plane.
16. cmos device as claimed in claim 15 is characterized in that: described bevel angle is 25 degree～75 degree.
17. cmos device as claimed in claim 15 is characterized in that: described first stress film is the stress film with tensile stress, and described second stress film is the stress film with compression stress.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101188403A CN100517652C (en) | 2006-11-28 | 2006-11-28 | CMOS device stress membrane forming method and CMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101188403A CN100517652C (en) | 2006-11-28 | 2006-11-28 | CMOS device stress membrane forming method and CMOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101192574A true CN101192574A (en) | 2008-06-04 |
| CN100517652C CN100517652C (en) | 2009-07-22 |
Family
ID=39487460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101188403A Active CN100517652C (en) | 2006-11-28 | 2006-11-28 | CMOS device stress membrane forming method and CMOS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100517652C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386138A (en) * | 2011-11-24 | 2012-03-21 | 上海华力微电子有限公司 | Through hole etching method, integrated circuit manufacturing method and integrated circuit |
| CN102915911A (en) * | 2012-09-24 | 2013-02-06 | 中国电子科技集团公司第五十五研究所 | Etching method for improving bottom of silicon carbide table board |
-
2006
- 2006-11-28 CN CNB2006101188403A patent/CN100517652C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386138A (en) * | 2011-11-24 | 2012-03-21 | 上海华力微电子有限公司 | Through hole etching method, integrated circuit manufacturing method and integrated circuit |
| CN102386138B (en) * | 2011-11-24 | 2014-05-14 | 上海华力微电子有限公司 | Through hole etching method, integrated circuit manufacturing method and integrated circuit |
| CN102915911A (en) * | 2012-09-24 | 2013-02-06 | 中国电子科技集团公司第五十五研究所 | Etching method for improving bottom of silicon carbide table board |
| CN102915911B (en) * | 2012-09-24 | 2014-12-10 | 中国电子科技集团公司第五十五研究所 | Etching method for improving bottom of silicon carbide table board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100517652C (en) | 2009-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6001695A (en) | Method to form ultra-short channel MOSFET with a gate-side airgap structure | |
| CN101330053B (en) | Method for forming stress layer of complementary metal oxide semiconductor device | |
| CN101393894B (en) | Semiconductor device and manufacturing method thereof | |
| US6696334B1 (en) | Method for formation of a differential offset spacer | |
| CN101207027A (en) | Method for forming semiconductor device grids | |
| CN101894799B (en) | Method for improving electron mobility of NMOS transistor | |
| CN100517652C (en) | CMOS device stress membrane forming method and CMOS device | |
| CN101207026B (en) | Method for forming semiconductor device grids | |
| US7306681B2 (en) | Method of cleaning a semiconductor substrate | |
| CN100499079C (en) | CMOS device stress membrane forming method | |
| US7741168B2 (en) | Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks | |
| CN102054686B (en) | Method for forming stress membrane of complementary metal-oxide-semiconductor transistor (CMOS) device | |
| CN101197324A (en) | CMOS device and method for forming its stress film | |
| US7323403B2 (en) | Multi-step process for patterning a metal gate electrode | |
| US6440809B1 (en) | Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide | |
| CN112086360B (en) | SiC planar MOSFET and self-alignment process thereof | |
| CN102376573B (en) | NMOS transistor and formation method thereof | |
| TWI336111B (en) | Method for in-situ repairing plasma damage on substrate and method for fabricating transistor device | |
| US20080286884A1 (en) | Method for in-situ repairing plasma damage and method for fabricating transistor device | |
| JP2008108913A (en) | Method of manufacturing semiconductor device | |
| KR100540339B1 (en) | Method For Making Gate Structure In The Semiconductor Device Manufacture Processing | |
| KR100571654B1 (en) | A method for forming gate electrode of semiconductor device having dual-implanted polysilicon gate | |
| KR100429229B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR100396711B1 (en) | Method for Fabricating of Semiconductor Device | |
| US8466053B2 (en) | Method of manufacturing semiconductor device, and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111108 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |