KR100571654B1 - A method for forming gate electrode of semiconductor device having dual-implanted polysilicon gate - Google Patents
A method for forming gate electrode of semiconductor device having dual-implanted polysilicon gate Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 71
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000001052 transient effect Effects 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 230000009977 dual effect Effects 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 238000001878 scanning electron micrograph Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
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Abstract
본 발명은 반도체 제조기술에 관한 것으로, 특히 듀얼-폴리실리콘 게이트(dual-implanted polysilicon gate)를 가지는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다. 이를 위한 본 발명은 기판의 식각손상을 피하면서 잔유물을 제거할 수 있는 듀얼-폴리실리콘 게이트 형성방법을 제공하는데 그 목적이 있다. 상기 목적을 달성하기 위한 본 발명은, 게이트 절연막이 형성된 반도체 기판 상부에 게이트 전극용 폴리실리콘막을 형성하는 제1 단계; 상기 폴리실리콘막의 일부분에 n형 불순물을 이온주입하는 제2 단계; 상기 폴리실리콘막의 다른 부분에 p형 불순물을 이온주입하는 제3 단계; 및 상기 폴리실리콘막을 플라즈마 건식식각법을 사용하여 패터닝하여 N+ 폴리실리콘막과 P+ 폴리실리콘막으로 이루어진 듀얼 폴리실리콘 게이트를 형성하되, 과도식각 시 Cl2/O2/HBr 혼합가스를 사용하는 제4 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a gate electrode of a semiconductor device having a dual-implanted polysilicon gate. The present invention for this purpose is to provide a method for forming a dual-polysilicon gate that can remove the residue while avoiding the etching damage of the substrate. The present invention for achieving the above object, a first step of forming a polysilicon film for the gate electrode on the semiconductor substrate on which the gate insulating film is formed; A second step of ion implanting n-type impurities into a portion of the polysilicon film; A third step of ion implanting p-type impurities into another portion of the polysilicon film; And patterning the polysilicon film using a plasma dry etching method to form a dual polysilicon gate consisting of an N + polysilicon film and a P + polysilicon film, and using a Cl 2 / O 2 / HBr mixed gas during transient etching. A step is made.
듀얼-폴리실리콘 게이트Dual-polysilicon gate
Description
도 1a는 종래기술에 따라 듀얼-폴리실리콘 게이트가 형성된 웨이퍼의 주사전자현미경 사진.1A is a scanning electron micrograph of a wafer having dual-polysilicon gates formed according to the prior art.
도 1b 및 도 1c는 각각 p+폴리실리콘 영역 및 n+폴리실리콘 영역을 찍은 SEM사진.1B and 1C are SEM images of p + polysilicon regions and n + polysilicon regions, respectively.
도 2a 및 도 2b는 본 발명의 일실시예에 따라 듀얼-폴리실리콘 게이트가 형성된 웨이퍼의 주사전자현미경 사진을 나타낸 것으로, 도 2a는 p+폴리실리콘 영역을 나타낸 사진이고, 도 2b는 n+폴리실리콘 영역을 나타낸 사진.2A and 2B show scanning electron micrographs of a wafer on which a dual-polysilicon gate is formed according to an embodiment of the present invention. FIG. 2A shows a p + polysilicon region, and FIG. 2B shows n + poly. Photo showing silicon area.
본 발명은 반도체 제조기술에 관한 것으로, 특히 듀얼-폴리실리콘 게이트(dual-implanted polysilicon gate)를 가지는 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a gate electrode of a semiconductor device having a dual-implanted polysilicon gate.
잘 알려진 바와 같이 CMOS 소자에서 n+ 도핑된 폴리실리콘 게이트전극을 사용하는 p 채널 MOSFET는 실리콘기판 표면 하부로 매립채널(buried channel)이 형성되는데, 이러한 상황하에서는 실리콘기판 표면에 채널이 형성되는 n채널 MOSFET과 p 채널 MOSFET간에 문턱전압이 차이가나게 되어 소자의 설계나 제작에 여러가지 제한 요인이 작용한다. 따라서, n채널 MOSFET의 게이트 폴리실리콘에는 n+ 도핑을 적용하고, p 채널 MOSFET의 게이트 폴리실리콘에는 p+ 도핑을 적용하는 바, 이러한 구조를 통상 듀얼-게이트 구조라 부른다. 듀얼 게이트 적용을 위한 공정에 있어, n채널 MOSFET과 p 채널 MOSFET의 각 게이트전극용 폴리실리콘막은 동시에 증착되고 패터닝되기 때문에, 먼저 비도핑 폴리실리콘을 증착하고 n채널 MOSFET과 p 채널 MOSFET의 각 게이트지역에 서로 다른 타입의 불순물을 도핑하기 위하여 선택적 이온주입 공정이 적용된다. 통상적으로, n채널 MOSFET의 게이트 폴리실리콘에는 인(Phosporous, P)을 이온주입하는 방법을 적용하고, p채널 MOSFET의 게이트 폴리실리콘에는 붕소(Boron, B)을 이온주입하는 방법을 적용하고 있다.As is well known, p-channel MOSFETs using n + doped polysilicon gate electrodes in CMOS devices form buried channels beneath the silicon substrate surface, in which case n-channel channels are formed on the silicon substrate surface. The threshold voltage difference between the MOSFET and the p-channel MOSFET causes various limitations in the design and fabrication of the device. Thus, the gate polysilicon of the n-channel MOSFET is applied to the n + doped, and the polysilicon gate has a bar, the application of p + doping such a structure of the p-channel MOSFET conventional dual-gate gujora call. In the process for dual gate application, since the polysilicon film for each gate electrode of the n-channel MOSFET and the p-channel MOSFET is deposited and patterned at the same time, undoped polysilicon is deposited first and then each gate region of the n-channel MOSFET and the p-channel MOSFET Selective ion implantation processes are applied to dope different types of impurities in the. In general, a method of ion implanting phosphorous (P) is applied to the gate polysilicon of the n-channel MOSFET, and a method of ion implanting boron (B) is applied to the gate polysilicon of the p-channel MOSFET.
통상적인 듀얼- 게이트 형성방법은 먼저, 실리콘기판 상에 소자분리막을 형성하고, 게이트산화막을 성장시킨 후 게이트산화막 상부에 게이트 전극용 전도막 재료인 폴리실리콘막을 증착한다.In the conventional dual-gate forming method, a device isolation film is first formed on a silicon substrate, a gate oxide film is grown, and a polysilicon film, which is a conductive film material for a gate electrode, is deposited on the gate oxide film.
다음으로, n채널 MOSFET 영역의 게이트 폴리실리콘막에 인(P)을 선택적으로 이온주입한 후에 p채널 MOSFET 영역의 게이트 폴리실리콘막에 붕소(B)를 선택적으로 이온주입한다.Next, after phosphorus (P) is selectively implanted into the gate polysilicon film in the n-channel MOSFET region, boron (B) is selectively implanted into the gate polysilicon film in the p-channel MOSFET region.
다음으로, 열처리를 실시하여 폴리실리콘막내의 도펀트(dopant)를 활성화시킨 후 마스크 및 식각 공정을 통해 게이트를 패터닝한다.Next, heat treatment is performed to activate the dopant in the polysilicon film, and then the gate is patterned through a mask and an etching process.
한편, 건식식각 공정은 플라즈마(Plasma)를 이용하여 행하는 관계로 비등방성(Anisotropic) 특성을 보인다. 따라서, 하부공정(예컨대, 소자분리공정)에서 단차를 유발하였을 경우에는 과도식각을 많이 수행하더라도 건식식각의 특성상 단차지역의 잔유물(Residue)을 제거하기가 용이하지 않다. On the other hand, the dry etching process is performed using a plasma (Plasma) shows anisotropic characteristics (Anisotropic) characteristics. Therefore, when a step is caused in a lower process (eg, a device separation process), even if a lot of excessive etching is performed, it is not easy to remove residues in the stepped area due to the characteristics of dry etching.
이러한 이유로 폴리실리콘이나 폴리사이드(Polycide)등을 이용하여 게이트 전극을 형성할 때에 단차지역에 존재하는 잔유물로 인하여 브릿지(Bridge)를 유발할 가능성이 매우 높다.For this reason, when forming a gate electrode using polysilicon or polycide, it is very likely to cause a bridge due to residues present in the stepped area.
이러한 구조적인 문제로 인하여 듀얼-폴리실리콘 게이트를 사용하는 소자의 게이트 식각시 인(Phosphorous)을 도핑한 폴리실리콘 영역보다 상대적으로 식각속도가 느린 붕소(Boron)를 도핑한 폴리실리콘 영역에서 잔유물을 제거하기가 더욱 더 어려운 실정이다. 그 이유를 보다 구체적으로 살펴보기로 한다.Due to this structural problem, residues are removed from the boron-doped polysilicon region having a slower etching rate than the polysilicon region doped with phosphorus during gate etching of a device using a dual-polysilicon gate. It is more difficult to do. The reason for this will be described in more detail.
일반적으로, 도핑을 진행한 후의 폴리실리콘은 700 ∼800Å정도의 두께를 가진다. 이와 같은 폴리실리콘의 두께에 따른 도펀트의 깊이 프로파일(Dopant Depth Profile)을 살펴보면, 붕소가 도핑된 폴리실리콘(p+)의 도펀트의 깊이 프로파일의 변화가 인이 도핑된 폴리실리콘(n+)에 비하여 심하다.In general, the polysilicon after the doping has a thickness of about 700 ~ 800Å. Such poly Looking at the depth profile (Dopant Depth Profile) of the dopant according to the thickness of the silicon, as compared to poly-silicon (n +) a change in the depth profile of the dopant phosphorus is doped in the boron-doped poly-silicon (p +) Severe.
궁극적으로는, p+폴리실리콘 영역에 비해 식각속도가 빠른 n+폴리실리콘 영역에서 과도 식각 타겟 과다로 인한 기판의 식각손상이 발생하게 된다. 이처럼, n+폴리실리콘 영역의 식각속도가 빠른 현상은 도펀트(P, B)에 따른 근본적인 식각속도 차이와 도펀트의 깊이 프로파일의 변화에 기인하는 것으로 추정하고 있다.Ultimately, it is the p + poly etch damage of the substrate caused by excessive over-etching occurs on the target n + polysilicon region has an etching rate faster than the silicon region. As described above, it is assumed that the rapid etching speed of the n + polysilicon region is due to the fundamental difference in etching speed and the change in the depth profile of the dopant according to the dopants (P and B).
한편, 게이트 건식식각 시 보통 2단계로 식각을 수행하는데, 프로파일을 형성하기 위한 메인(Main) 식각단계와 프로파일 형성 후 잔유물을 제거하기 위한 과도식각(Over Etch)단계로 이루어진다.On the other hand, during gate dry etching, etching is usually performed in two stages, and includes a main etching step for forming a profile and an over etching step for removing residue after profile formation.
여기서, 과도식각은 하부층에 손상을 미치지 않으면서 효과적으로 잔유물을 제거할 것을 요구하므로, 통상 게이트 산화막과 높은 식각 선택비를 필요로 한다. 이에 따라, 폴리실리콘 또는 폴리사이드와 같은 물질로 이루어진 게이트 전도막을 식각하는데 있어서 Cl2 가스와 선택비 향상을 위한 O2 가스를 함께 사용하고 있다.Here, the transient etching requires effective removal of the residue without damaging the underlying layer, and thus usually requires a gate oxide film and a high etching selectivity. Accordingly, in etching the gate conductive film made of a material such as polysilicon or polyside, Cl 2 gas and O 2 gas for improving selectivity are used together.
도 1a는 종래기술에 따라 듀얼-폴리실리콘 게이트가 형성된 웨이퍼의 주사전자현미경(Scanning Electron Microscope, SEM)사진을 나타낸 것이고, 도 1b 및 도 1c는 각각 도 1a에서의 p+폴리실리콘 영역(P+ POLY) 및 n+폴리실리콘 영역(N+ POLY)을 찍은 SEM사진을 나타낸 것이다.FIG. 1A shows a scanning electron microscope (SEM) photograph of a wafer having a dual-polysilicon gate formed according to the prior art, and FIGS. 1B and 1C are p + polysilicon regions (P + POLY) in FIG. 1A, respectively. ) And SEM photographs taken of n + polysilicon regions (N + POLY).
듀얼-폴리실리콘 게이트 식각 시 과도식각을 충분히 수행하지 않았을 경우,도 1b에 도시된 바와 같이 p+폴리실리콘 영역에는 플라즈마를 이용한 건식식각의 비등방성 식각 특성 때문에 잔유물이 제거되지 않고 남아있게 된다.When the transient etching is not sufficiently performed during the dual-polysilicon gate etching, as shown in FIG. 1B, the residue is not removed in the p + polysilicon region due to the anisotropic etching characteristic of the dry etching using plasma.
한편, 단차가 심한 지역에 남는 잔유물을 제거하기 위하여 과도식각 타겟을 증가시켜 식각하는 경우, 비교적 하부의 게이트 산화막과 높은 식각 선택비를 갖는 Cl2/O2 혼합가스를 사용한다 하더라도, 도 1c에 도시된 바와 같이 잔유물은 제거되었으나 게이트 산화막 및 기판 손상을 피할 수 없었다.On the other hand, in the case of etching by increasing the over-etching target to remove the residues remaining in the stepped region, even if using a Cl 2 / O 2 mixed gas having a relatively low gate oxide film and a high etching selectivity, Figure 1c As shown, the residue was removed, but damage to the gate oxide film and the substrate could not be avoided.
결론적으로, 종래기술을 사용하여 듀얼-폴리실리콘 게이트를 식각하는 경우에는 기판 손상을 피하면서 잔유물을 완전히 제거하는 것이 거의 불가능하다고 할 수 있다. 더구나, 반도체 소자가 고집적화되어 갈수록 폴리실리콘 하부의 게이트 산화막 두께가 보다 얇아지고 있어 이러한 문제점은 더욱 심화되는 양상을 띠고 있다.In conclusion, when etching the dual-polysilicon gate using the prior art, it can be said that it is almost impossible to completely remove the residue while avoiding substrate damage. In addition, as the semiconductor devices are highly integrated, the thickness of the gate oxide layer under the polysilicon becomes thinner, and this problem is exacerbated.
본 발명은 기판의 식각손상을 피하면서 잔유물을 제거할 수 있는 듀얼-폴리실리콘 게이트 형성방법을 제공하는데 그 목적이 있다.
It is an object of the present invention to provide a method for forming a dual-polysilicon gate capable of removing residue while avoiding etching damage of a substrate.
상기 목적을 달성하기 위한 본 발명은, 게이트 절연막이 형성된 반도체 기판 상부에 게이트 전극용 폴리실리콘막을 형성하는 제1 단계; 상기 폴리실리콘막의 일부분에 n형 불순물을 이온주입하는 제2 단계; 상기 폴리실리콘막의 다른 부분에 p형 불순물을 이온주입하는 제3 단계; 및 상기 폴리실리콘막을 플라즈마 건식식각법을 사용하여 패터닝하여 N+ 폴리실리콘막과 P+ 폴리실리콘막으로 이루어진 듀얼 폴리실리콘 게이트를 형성하되, 과도식각 시 Cl2/O2/HBr 혼합가스를 사용하는 제4 단계를 포함하여 이루어진다.The present invention for achieving the above object, a first step of forming a polysilicon film for the gate electrode on the semiconductor substrate on which the gate insulating film is formed; A second step of ion implanting n-type impurities into a portion of the polysilicon film; A third step of ion implanting p-type impurities into another portion of the polysilicon film; And patterning the polysilicon film using a plasma dry etching method to form a dual polysilicon gate consisting of an N + polysilicon film and a P + polysilicon film, and using a Cl 2 / O 2 / HBr mixed gas during transient etching. A step is made.
즉, 본 발명은 듀얼-폴리실리콘 게이트 식각 시 과도식각 단계에서 기존의 Cl2/O2 혼합가스에 비등방성 식각특성을 보완하기 위한 HBr 가스를 첨가하는 기술이다.That is, the present invention is a technique of adding an HBr gas to supplement the anisotropic etching characteristics to the existing Cl 2 / O 2 mixed gas in the transient etching step during the dual-silicon gate etching.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
본 실시예는 먼저, 실리콘기판 상에 소자분리막을 형성하고, 게이트산화막을 성장시킨 후 게이트산화막 상부에 게이트 전극용 전도막 재료인 폴리실리콘막을 증착한다.In this embodiment, a device isolation film is first formed on a silicon substrate, a gate oxide film is grown, and a polysilicon film, which is a conductive film material for a gate electrode, is deposited on the gate oxide film.
다음으로, n채널 MOSFET 영역의 게이트 폴리실리콘막에 인(P)을 선택적으로 이온주입한 후에 p채널 MOSFET 영역의 게이트 폴리실리콘막에 붕소(B)를 선택적으로 이온주입한다.Next, after phosphorus (P) is selectively implanted into the gate polysilicon film in the n-channel MOSFET region, boron (B) is selectively implanted into the gate polysilicon film in the p-channel MOSFET region.
다음으로, 열처리를 실시하여 폴리실리콘막내의 도펀트(dopant)를 활성화시킨 후 마스크 및 식각 공정을 통해 게이트를 패터닝한다.Next, heat treatment is performed to activate the dopant in the polysilicon film, and then the gate is patterned through a mask and an etching process.
이때, 식각공정은 플라즈마를 이용한 건식식각법을 사용하여 수행하게 되는데, 이를 위한 식각장비로는, ICP(Inductively Coupled Plasma) 타입의 일종인 Lam Research사(社)의 TCP-9048과 AMAT사(社)의 Centura 5200 DSP를 사용하여 수행한 다.At this time, the etching process is performed by using a dry etching method using plasma, the etching equipment for this, TCP-9048 and AMAT (Lam Research Co., Ltd.), a kind of ICP (Inductively Coupled Plasma) type This is done using the Centura 5200 DSP.
건식식각은 기존과 같이 Cl2 가스를 주 식각 소오스로 사용하여 주 식각단계를 수행한다. 이어서, 과도식각 시 기존의 Cl2/O2 혼합가스에 HBr 가스를 더 첨가하여 식각을 수행한다. HBr 가스는 비등방성 식각 특성을 보완하기 위한 것으로, p+폴리실리콘 영역의 단차진 부분에서 잔유물 제거가 용이하도록 하여 n+폴리실리콘 영역에서 과도 식각 타겟의 증가에 의한 기판손상이 유발되는 것을 방지하는 작용을 한다.In the dry etching process, the main etching step is performed using Cl 2 gas as the main etching source. Subsequently, during excessive etching, etching is performed by further adding HBr gas to the existing Cl 2 / O 2 mixed gas. HBr gas is designed to compensate for anisotropic etching characteristic, p + poly and to facilitate the residue removed from the stepped portion of the silicon region to prevent the substrate damage due to the increase of the excessive etching target caused in the n + polysilicon region It works.
자세한 과도식각 레시피(Recipe)는 다음과 같다.The detailed transient etching recipe is as follows.
가) 소오스 파워 : 500 W 이하 A) Source power: 500 W or less
나) 바이어스 파워 : 200 W 이하B) Bias power: 200 W or less
다) 총 압력 : 30 mT 이하C) Total pressure: 30 mT or less
라) 가스 및 유량 : Cl2가스 - 100sccm 이하D) Gas and flow rate: Cl 2 gas-100 sccm or less
O2 및 HBr - Cl2 가스의 70％ 이하70% or less of O 2 and HBr-Cl 2 gas
마) 전극 온도 : 0 ~ 60℃E) Electrode temperature: 0 ~ 60 ℃
도 2a 및 도 2b는 본 발명의 일실시예에 따라 듀얼-폴리실리콘 게이트가 형성된 웨이퍼의 주사전자현미경 사진을 나타낸 것으로, 도 2a는 p+폴리실리콘 영역(P+ POLY)을 , 도 2b는 n+폴리실리콘 영역(N+ POLY)을 각각 나타낸 것이다.2A and 2B show scanning electron micrographs of a wafer on which a dual-polysilicon gate is formed according to an embodiment of the present invention, FIG. 2A shows a p + polysilicon region (P + POLY), and FIG. 2B shows n + Polysilicon regions (N + POLY) are shown respectively.
도 2a를 참조하면, 과도식각 단계에서 HBr가스를 도입하는 것에 의해 비등방성 식각특성을 보완함으로써, p+폴리실리콘 영역(P+ POLY)에서 잔유물이 발견되지 않음을 확인할 수 있다.Referring to FIG. 2A, it is confirmed that residues are not found in the p + polysilicon region (P + POLY) by supplementing the anisotropic etching characteristic by introducing HBr gas in the transient etching step.
또한, 도 2b를 참조하면, 과도식각 타겟을 과도하게 증가시키지 않음으로 인하여 n+폴리실리콘 영역(N+ POLY)에서 잔유물은 물론 식각손상이 발생하지 않음을 확인할 수 있다.In addition, referring to Figure 2b, it can be seen that the residue as well as the etching damage does not occur in the n + polysilicon region (N + POLY) due to not excessively increasing the transient etching target.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 듀얼-폴리실리콘 게이트 식각 시 기판의 손상을 유발하지 않으면서 잔유물을 효과적으로 제거함으로써 브릿지 페일을 방지하는 효과가 있으며, 이에 따라 반도체 소자의 동작 신뢰성을 향상 시키고 더불어 제조 수율을 높일 수 있는 효과가 있다.
The present invention has the effect of preventing bridge failure by effectively removing residues without causing damage to the substrate during dual-polysilicon gate etching, thereby improving the operational reliability of the semiconductor device and increasing the manufacturing yield. There is.
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